clean and add license header
diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl
index 3d31ce5..2e52fd8 100644
--- a/openlane/computer/config.tcl
+++ b/openlane/computer/config.tcl
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2021 cpu-dev
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -11,7 +11,6 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
diff --git a/verilog/dv/jacaranda_test/as-for-caravel.c b/verilog/dv/jacaranda_test/as-for-caravel.c
index d888ecf..e04c78e 100644
--- a/verilog/dv/jacaranda_test/as-for-caravel.c
+++ b/verilog/dv/jacaranda_test/as-for-caravel.c
@@ -1,3 +1,19 @@
+/*
+ * Copyright 2021 cpu-dev
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
diff --git a/verilog/dv/jacaranda_test/instr.c b/verilog/dv/jacaranda_test/instr.c
index 9b75e22..ca3edd7 100644
--- a/verilog/dv/jacaranda_test/instr.c
+++ b/verilog/dv/jacaranda_test/instr.c
@@ -1,3 +1,19 @@
+/*
+ * Copyright 2021 cpu-dev
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
char mem[256];
diff --git a/verilog/rtl/jacaranda-8/7SEG/bin_dec_decoder.v b/verilog/rtl/jacaranda-8/7SEG/bin_dec_decoder.v
deleted file mode 100644
index 4ed3a7c..0000000
--- a/verilog/rtl/jacaranda-8/7SEG/bin_dec_decoder.v
+++ /dev/null
@@ -1,12 +0,0 @@
-module bin_dec_decoder(bin_in, dig_3, dig_2, dig_1);
- input [7:0] bin_in;
- output [3:0] dig_3;
- output [3:0] dig_2;
- output [3:0] dig_1;
-
- assign dig_1 = bin_in % 10;
- assign dig_2 = (bin_in/10) % 10;
- assign dig_3 = (bin_in/100) % 10;
-
-endmodule
-
diff --git a/verilog/rtl/jacaranda-8/7SEG/nanaseg.v b/verilog/rtl/jacaranda-8/7SEG/nanaseg.v
deleted file mode 100644
index ffd646d..0000000
--- a/verilog/rtl/jacaranda-8/7SEG/nanaseg.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module nanaseg(bin_in, seg_dig1, seg_dig2, seg_dig3);
- input [7:0] bin_in;
- output [6:0] seg_dig1;
- output [6:0] seg_dig2;
- output [6:0] seg_dig3;
-
- wire [3:0] dig_3;
- wire [3:0] dig_2;
- wire [3:0] dig_1;
-
- bin_dec_decoder bin_dec_decoder(.bin_in(bin_in),
- .dig_3(dig_3),
- .dig_2(dig_2),
- .dig_1(dig_1));
- nanaseg_decoder seg3(.dec_in(dig_3),
- .nanaseg_out(seg_dig3));
- nanaseg_decoder seg2(.dec_in(dig_2),
- .nanaseg_out(seg_dig2));
- nanaseg_decoder seg1(.dec_in(dig_1),
- .nanaseg_out(seg_dig1));
-endmodule
-
diff --git a/verilog/rtl/jacaranda-8/7SEG/nanaseg_decoder.v b/verilog/rtl/jacaranda-8/7SEG/nanaseg_decoder.v
deleted file mode 100644
index 66990c0..0000000
--- a/verilog/rtl/jacaranda-8/7SEG/nanaseg_decoder.v
+++ /dev/null
@@ -1,25 +0,0 @@
-module nanaseg_decoder(dec_in, nanaseg_out);
- input [3:0] dec_in;
- output [6:0] nanaseg_out;
-
- assign nanaseg_out = decode(dec_in);
-
- function [6:0] decode(input [3:0] dec_in);
- begin
- case(dec_in)
- 4'b0000: decode = 7'b1000000;
- 4'b0001: decode = 7'b1111001;
- 4'b0010: decode = 7'b0100100;
- 4'b0011: decode = 7'b0110000;
- 4'b0100: decode = 7'b0011001;
- 4'b0101: decode = 7'b0010010;
- 4'b0110: decode = 7'b0000010;
- 4'b0111: decode = 7'b1111000;
- 4'b1000: decode = 7'b0000000;
- 4'b1001: decode = 7'b0010000;
- default: decode = 7'b1111111;
- endcase
- end
- endfunction
-endmodule
-
diff --git a/verilog/rtl/jacaranda-8/LED/LED4.v b/verilog/rtl/jacaranda-8/LED/LED4.v
deleted file mode 100644
index e932458..0000000
--- a/verilog/rtl/jacaranda-8/LED/LED4.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module LED4(input [7:0] in_data,
- input begin_flag,
- output reg [7:0] state_reg,
- output reg [3:0] out_data,
- input clock);
-
- reg [27:0] delay_cnt = 28'h0000000;
- reg [7:0] buffer;
-
- always @(posedge clock) begin
- if(delay_cnt == 28'h0000000 && begin_flag == 1'b0) begin
- delay_cnt <= 28'h0000000;
- state_reg <= 8'b00000000;
- buffer <= in_data;
- end else if(delay_cnt == 28'h0000000 && begin_flag == 1'b1) begin
- delay_cnt <= delay_cnt + 28'h0000001;
- state_reg <= 8'b00000001;
- buffer <= in_data;
- end else if(delay_cnt != 28'h2faf080) begin
- delay_cnt <= delay_cnt + 28'h0000001;
- state_reg <= 8'b00000001;
- buffer <= buffer;
- end else if(delay_cnt == 28'h2faf080) begin
- delay_cnt <= 28'h0000000;
- state_reg <= 8'b00000001;
- out_data <= buffer[3:0];
- end
- end
-endmodule
diff --git a/verilog/rtl/jacaranda-8/Makefile b/verilog/rtl/jacaranda-8/Makefile
deleted file mode 100644
index 16648aa..0000000
--- a/verilog/rtl/jacaranda-8/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-verilog = alu_controller.v alu.v computer.v cpu.v data_mem.v decoder.v instr_mem.v main_controller.v regfile.v test_bench.v UART/UART.v UART/tx.v UART/rx.v LED/LED4.v 7SEG/bin_dec_decoder.v 7SEG/nanaseg_decoder.v 7SEG/nanaseg.v
-output = computer
-top = test_bench
-wave = wave.vcd
-
-all: $(verilog)
- iverilog -o $(output) -s $(top) $(verilog)
- vvp $(output)
-
-$(wave):
- make all
-
-wave: $(wave)
- gtkwave $(wave) &
-
-clean:
- rm $(output) $(wave)
-
diff --git a/verilog/rtl/jacaranda-8/UART/UART.v b/verilog/rtl/jacaranda-8/UART/UART.v
index f76325d..6cfb945 100644
--- a/verilog/rtl/jacaranda-8/UART/UART.v
+++ b/verilog/rtl/jacaranda-8/UART/UART.v
@@ -1,4 +1,17 @@
-// clock must be 50MHz
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
// baud rate 115200bps, stop bit 1bit, data 8bit, no parity, no flow control
module UART(
@@ -27,14 +40,14 @@
assign clk_count_bit = clk_freq / BAUD_RATE;
always @(negedge clk) begin
- if(state == 1'b0) begin //データ待機中
+ if(state == 1'b0) begin
int_req <= 1'b0;
if(receive_flag == 1'b1) begin
state <= 1'b1;
end else begin
state <= state;
end
- end else if(state == 1'b1) begin //データが来たことをCPUに伝える
+ end else if(state == 1'b1) begin
int_req <= 1'b1;
if(access_addr == 8'd252 && reg_w_en == 1'b1) begin
state <= 1'b0;
diff --git a/verilog/rtl/jacaranda-8/UART/rx.v b/verilog/rtl/jacaranda-8/UART/rx.v
index 3afd654..83215cf 100644
--- a/verilog/rtl/jacaranda-8/UART/rx.v
+++ b/verilog/rtl/jacaranda-8/UART/rx.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module rx(clk, rx_en, rx, data, end_flag, clk_count_bit);
input wire clk;
input wire rx_en;
diff --git a/verilog/rtl/jacaranda-8/UART/tx.v b/verilog/rtl/jacaranda-8/UART/tx.v
index 60d1b4a..1fc2db0 100644
--- a/verilog/rtl/jacaranda-8/UART/tx.v
+++ b/verilog/rtl/jacaranda-8/UART/tx.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module tx(clk, reset, tx_en, begin_flag, data, tx, busy_flag, clk_count_bit);
input wire clk;
input wire reset;
diff --git a/verilog/rtl/jacaranda-8/alu.v b/verilog/rtl/jacaranda-8/alu.v
index 81ef874..2203dfb 100644
--- a/verilog/rtl/jacaranda-8/alu.v
+++ b/verilog/rtl/jacaranda-8/alu.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module alu(rd, rs, alu_ctrl, alu_out);
input [7:0] rd, rs;
input [3:0] alu_ctrl;
diff --git a/verilog/rtl/jacaranda-8/alu_controller.v b/verilog/rtl/jacaranda-8/alu_controller.v
index 8394ba8..5d840c3 100644
--- a/verilog/rtl/jacaranda-8/alu_controller.v
+++ b/verilog/rtl/jacaranda-8/alu_controller.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module alu_controller(opcode, alu_ctrl);
input [3:0] opcode;
output [3:0] alu_ctrl;
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 597d085..e0b6580 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
`default_nettype none
// module computer(
@@ -44,15 +58,10 @@
output [2:0] irq
);
-/** temporary **/
wire rx;
wire tx;
- wire [3:0] led_out_data;
- wire [6:0] seg_out_1;
- wire [6:0] seg_out_2;
- wire [6:0] seg_out_3;
-/** **/
assign io_oeb[37:0] = 38'h00_0000_0000;
+
// UART - GPIO
assign io_out[37] = tx;
assign rx = io_in[36];
@@ -68,7 +77,6 @@
wire receive_flag;
reg tx_en;
reg rx_en;
- //reg begin_flag;
wire begin_flag;
reg [7:0] tx_data;
wire [7:0] rx_data;
@@ -155,10 +163,8 @@
always @(posedge clock) begin
if(rs_data == 8'd253 && mem_w_en == 1) begin
tx_data <= rd_data;
- //begin_flag = 1;
end else begin
tx_data <= tx_data;
- //begin_flag = 0;
end
end
@@ -185,7 +191,6 @@
: (rs_data == 8'd249) ? gpio_in
: _mem_r_data;
- //割り込み要求が立っている時は割り込み不許可
always @(posedge clock) begin
if(int_req == 1'b1) begin
int_en <= 8'h00;
@@ -195,7 +200,6 @@
end
always @(posedge clock) begin
- //割り込みベクタの書き込み
if(rs_data == 8'd250 && mem_w_en == 1'b1) begin
int_vec <= rd_data;
end else begin
diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v
index d0f336a..616d825 100644
--- a/verilog/rtl/jacaranda-8/cpu.v
+++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -1,21 +1,29 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module cpu(clock, reset, instr, pc, rd_data, rs_data, mem_w_en, mem_r_data, int_req, int_en, int_vec, reg_w_en);
input clock;
input reset;
input [7:0] instr;
- //割り込み要求線
input int_req;
- //割り込みイネーブル
input [7:0] int_en;
- //割り込みベクタ
input [7:0] int_vec;
output [7:0] pc;
reg [7:0] ret_addr;
- //レジスタから読み込んだデータ
output [7:0] rd_data, rs_data;
- //メモリにデータを書き込むか
output mem_w_en;
- //メモリから読み込んだデータ
input [7:0] mem_r_data;
reg flag;
reg [7:0] pc;
@@ -24,33 +32,23 @@
wire [1:0] rd_a, rd_a_p, rs_a, rs_a_p;
wire [3:0] imm;
- //レジスタにデータを書き込むか
output reg_w_en;
- //レジスタに書き込むデータとそのバッファ
wire [7:0] reg_w_data;
wire [7:0] reg_w_data_p;
wire [7:0] reg_w_data_p_p;
wire [7:0] reg_w_imm;
- //レジスタに書き込むデータをレジスタ(0)かメモリ(1)からか選択する
wire reg_reg_mem_w_sel;
- //レジスタに書き込むデータをALUからのデータか選択する(1)でALUから(0)でそれ以外
wire reg_alu_w_sel;
- //ALUの制御信号
wire [3:0] alu_ctrl;
- //ALUからの出力
wire [7:0] alu_out;
- //flagに書き込みを行うか
wire flag_w_en;
- //即値ロードの場合のみ(1)になる信号
wire imm_en;
- //ldih(1)かldil(0)かの信号
wire ih_il_sel;
- //jmp, je実行時に(1)になる信号
wire jmp_en, je_en;
wire ret;
@@ -63,17 +61,17 @@
alu_controller alu_controller(opcode, alu_ctrl);
regfile regfile(rd_a, rs_a, reg_w_data, reg_w_en, rd_data, rs_data, clock, intr_en);
- //即値ロード時のみrd_a, rs_aを3に
+
assign rd_a = imm_en ? 2'b11 : rd_a_p;
assign rs_a = imm_en ? 2'b11 : rs_a_p;
- //レジスタに書き込むデータの出元を選択
+
assign reg_w_data_p_p = reg_reg_mem_w_sel ? mem_r_data : rs_data;
assign reg_w_data_p = reg_alu_w_sel ? alu_out : reg_w_data_p_p;
assign reg_w_imm = ih_il_sel ? {imm, rs_data[3:0]} : {rs_data[7:4], imm};
assign reg_w_data = imm_en ? reg_w_imm : reg_w_data_p;
alu alu(rd_data, rs_data, alu_ctrl, alu_out);
- //フラグレジスタ書き込み
+
always @(posedge clock) begin
if(ret) begin
flag <= _flag;
diff --git a/verilog/rtl/jacaranda-8/data_mem.v b/verilog/rtl/jacaranda-8/data_mem.v
index e04c25a..b7c59e2 100644
--- a/verilog/rtl/jacaranda-8/data_mem.v
+++ b/verilog/rtl/jacaranda-8/data_mem.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module data_mem(addr, w_data, w_en, r_data, clock);
input [7:0] addr;
input [7:0] w_data;
diff --git a/verilog/rtl/jacaranda-8/decoder.v b/verilog/rtl/jacaranda-8/decoder.v
index 69c15e7..8e7f5ac 100644
--- a/verilog/rtl/jacaranda-8/decoder.v
+++ b/verilog/rtl/jacaranda-8/decoder.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module decoder(instr, opcode, rs_a, rd_a, imm);
input [7:0] instr;
output [3:0] opcode;
diff --git a/verilog/rtl/jacaranda-8/instr_mem.v b/verilog/rtl/jacaranda-8/instr_mem.v
index 0c638e8..f8b9897 100644
--- a/verilog/rtl/jacaranda-8/instr_mem.v
+++ b/verilog/rtl/jacaranda-8/instr_mem.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module instr_mem(addr, w_data, w_en, r_data, clock, reset);
input [7:0] addr;
input [7:0] w_data;
diff --git a/verilog/rtl/jacaranda-8/main_controller.v b/verilog/rtl/jacaranda-8/main_controller.v
index cf5ad08..43733d3 100644
--- a/verilog/rtl/jacaranda-8/main_controller.v
+++ b/verilog/rtl/jacaranda-8/main_controller.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module main_controller(opcode, rd_a, reg_w_en, mem_w_en, reg_reg_mem_w_sel, reg_alu_w_sel, flag_w_en, imm_en, ih_il_sel, jmp_en, je_en, ret);
input [3:0] opcode;
input [1:0] rd_a;
diff --git a/verilog/rtl/jacaranda-8/regfile.v b/verilog/rtl/jacaranda-8/regfile.v
index d93104c..08b22b6 100644
--- a/verilog/rtl/jacaranda-8/regfile.v
+++ b/verilog/rtl/jacaranda-8/regfile.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module regfile(rd_addr, rs_addr, w_data, w_en, rd_data, rs_data, clock, intr_en);
input [1:0] rd_addr, rs_addr;
input [7:0] w_data;
diff --git a/verilog/rtl/jacaranda-8/test_bench.v b/verilog/rtl/jacaranda-8/test_bench.v
deleted file mode 100644
index 7bfd58e..0000000
--- a/verilog/rtl/jacaranda-8/test_bench.v
+++ /dev/null
@@ -1,161 +0,0 @@
-`timescale 1ns/1ps
-module test_bench();
-parameter TIMESCALE_HZ = 1000_000_000;
-parameter CLOCK_HZ = 50_000_000;
-parameter BAUD_RATE = 115200;
-parameter TIME_CLOCK = $floor(TIMESCALE_HZ / CLOCK_HZ);
-parameter TIME_BIT = $floor(TIMESCALE_HZ / BAUD_RATE);
- reg clk;
- reg rx;
- wire[7:0] data;
- wire end_flag;
- wire [3:0] led_out_data;
- wire [6:0] seg_out_1;
- wire [6:0] seg_out_2;
- wire [6:0] seg_out_3;
- computer cmptr(clk, rx, tx, led_out_data, seg_out_1, seg_out_2, seg_out_3);
-
-always #(TIME_CLOCK/2) clk = ~clk;
-
-initial begin
- $dumpfile("wave.vcd");
- $dumpvars(0, cmptr);
- clk = 1'b0;
- rx = 1'b1;
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #10000
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #1000
- #(2*TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx = 1'b0;
- #(TIME_BIT);
- rx = 1'b1;
- #(TIME_BIT);
- rx= 1'b1;
- #(2*TIME_BIT);
- #100000
- $finish;
-end
-endmodule
diff --git a/verilog/rtl/jacaranda-8/wishbone.v b/verilog/rtl/jacaranda-8/wishbone.v
index 01682f9..2577f79 100644
--- a/verilog/rtl/jacaranda-8/wishbone.v
+++ b/verilog/rtl/jacaranda-8/wishbone.v
@@ -1,3 +1,17 @@
+// Copyright 2021 cpu-dev
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
module wishbone(
input wb_clk_i,
input wb_rst_i,
