now reset is correct
diff --git a/verilog/rtl/jacaranda-8/UART/UART.v b/verilog/rtl/jacaranda-8/UART/UART.v index 6cfb945..1f9d10a 100644 --- a/verilog/rtl/jacaranda-8/UART/UART.v +++ b/verilog/rtl/jacaranda-8/UART/UART.v
@@ -39,8 +39,10 @@ assign clk_count_bit = clk_freq / BAUD_RATE; - always @(negedge clk) begin - if(state == 1'b0) begin + always @(negedge clk or posedge reset) begin + if(reset) begin + state <= 1'b0; + end else if(state == 1'b0) begin int_req <= 1'b0; if(receive_flag == 1'b1) begin state <= 1'b1; @@ -62,6 +64,6 @@ end tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag, clk_count_bit); - rx rx1(clk, rx_en, rx, rx_data, receive_flag, clk_count_bit); + rx rx1(clk, reset, rx_en, rx, rx_data, receive_flag, clk_count_bit); endmodule
diff --git a/verilog/rtl/jacaranda-8/UART/rx.v b/verilog/rtl/jacaranda-8/UART/rx.v index 83215cf..1d46160 100644 --- a/verilog/rtl/jacaranda-8/UART/rx.v +++ b/verilog/rtl/jacaranda-8/UART/rx.v
@@ -12,20 +12,21 @@ // See the License for the specific language governing permissions and // limitations under the License. -module rx(clk, rx_en, rx, data, end_flag, clk_count_bit); +module rx(clk, reset, rx_en, rx, data, end_flag, clk_count_bit); input wire clk; + input wire reset; input wire rx_en; input wire rx; - output reg[7:0] data = 8'b00000000; - output reg end_flag = 1'b0; + output reg[7:0] data; + output reg end_flag; input wire [31:0] clk_count_bit; wire [31:0] clk_begin_to_receive; - reg[1:0] state = 2'b00; - reg[31:0] clk_count = 32'd0; - reg[2:0] bit_count = 3'd0; - reg[3:0] recent = 4'b1111; + reg[1:0] state; + reg[31:0] clk_count; + reg[2:0] bit_count; + reg[3:0] recent; wire update_flag; assign clk_begin_to_receive = clk_count_bit + clk_count_bit / 2 - 4; @@ -34,40 +35,49 @@ ? clk_count == clk_begin_to_receive : clk_count == clk_count_bit - 32'd1; - always @(posedge clk) begin - case(state) - 2'b00: begin - clk_count <= 32'd0; - bit_count <= 3'd0; - end_flag <= 1'b0; - recent = {recent[2:0], rx}; - state = (recent == 4'b0000) & rx_en ? 2'b01 : state; - end - 2'b01: begin - clk_count <= clk_count + 32'd1; - if(update_flag) begin - state = 2'b11; + always @(posedge clk or posedge reset) begin + if(reset) begin + data <= 8'b0; + end_flag <= 1'b0; + state <= 2'b0; + clk_count <= 32'd0; + bit_count <= 3'd0; + recent <= 4'b1111; + end else begin + case(state) + 2'b00: begin clk_count <= 32'd0; - data[2'd0] <= rx; - bit_count <= 3'd1; + bit_count <= 3'd0; + end_flag <= 1'b0; + recent = {recent[2:0], rx}; + state = (recent == 4'b0000) & rx_en ? 2'b01 : state; end - end - 2'b11: begin - clk_count <= clk_count + 32'd1; - if(update_flag) begin - state <= (bit_count == 3'd7) ? 2'b10 : state; - data[bit_count] <= rx; - bit_count <= bit_count + 3'd1; - clk_count <= 32'd0; + 2'b01: begin + clk_count <= clk_count + 32'd1; + if(update_flag) begin + state = 2'b11; + clk_count <= 32'd0; + data[2'd0] <= rx; + bit_count <= 3'd1; + end end - end - 2'b10: begin - clk_count <= clk_count + 32'd1; - if(update_flag) begin - state <= 2'b00; - end_flag <= 1'b1; + 2'b11: begin + clk_count <= clk_count + 32'd1; + if(update_flag) begin + state <= (bit_count == 3'd7) ? 2'b10 : state; + data[bit_count] <= rx; + bit_count <= bit_count + 3'd1; + clk_count <= 32'd0; + end end - end - endcase + 2'b10: begin + clk_count <= clk_count + 32'd1; + if(update_flag) begin + state <= 2'b00; + end_flag <= 1'b1; + end + end + endcase + end end endmodule
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v index e0b6580..2b26cde 100644 --- a/verilog/rtl/jacaranda-8/computer.v +++ b/verilog/rtl/jacaranda-8/computer.v
@@ -14,17 +14,6 @@ `default_nettype none -// module computer( -// input clock, -// input rx, -// output tx, -// output [3:0] led_out_data, -// output [6:0] seg_out_1, -// output [6:0] seg_out_2, -// output [6:0] seg_out_3 -// ); - - module computer( `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply @@ -88,12 +77,6 @@ wire reg_w_en; - reg [7:0] led_in_data; - reg led_begin_flag; - wire [7:0] led_state_reg; - - reg [7:0] nanaseg_in_data; - wire [7:0] instr_mem_addr; wire [7:0] instr_mem_data; wire instr_mem_en; @@ -153,23 +136,30 @@ .int_vec(int_vec), .reg_w_en(reg_w_en)); - always @(posedge clock) begin - if(rs_data == 8'd255 && mem_w_en == 1) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + tx_en <= 1'b0; + rx_en <= 1'b0; + end else if(rs_data == 8'd255 && mem_w_en == 1) begin tx_en <= rd_data[0]; rx_en <= rd_data[1]; end end - always @(posedge clock) begin - if(rs_data == 8'd253 && mem_w_en == 1) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + tx_data <= 8'b0; + end else if(rs_data == 8'd253 && mem_w_en == 1) begin tx_data <= rd_data; end else begin tx_data <= tx_data; end end - always @(posedge clock) begin - if(rs_data == 8'd251 && mem_w_en == 1) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + gpio_out <= 8'b0; + end else if(rs_data == 8'd251 && mem_w_en == 1) begin gpio_out <= rd_data; end else begin gpio_out <= gpio_out; @@ -191,16 +181,20 @@ : (rs_data == 8'd249) ? gpio_in : _mem_r_data; - always @(posedge clock) begin - if(int_req == 1'b1) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + int_en <= 8'b0; + end else if(int_req == 1'b1) begin int_en <= 8'h00; end else if(int_req == 1'b0) begin int_en <= 8'h01; end end - always @(posedge clock) begin - if(rs_data == 8'd250 && mem_w_en == 1'b1) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + int_vec <= 8'b0; + end else if(rs_data == 8'd250 && mem_w_en == 1'b1) begin int_vec <= rd_data; end else begin int_vec <= int_vec;
diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v index 616d825..8024a38 100644 --- a/verilog/rtl/jacaranda-8/cpu.v +++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -72,8 +72,10 @@ alu alu(rd_data, rs_data, alu_ctrl, alu_out); - always @(posedge clock) begin - if(ret) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + flag <= 0; + end if(ret) begin flag <= _flag; end else if(je_en) begin flag <= 0; @@ -84,16 +86,20 @@ end end - always @(posedge clock) begin - if(ret) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + intr_en <= 1'b0; + end else if(ret) begin intr_en <= 1'b0; end else if(int_req && int_en[0]) begin - intr_en <= 1'b1; + intr_en <= 1'b1; end end - always @(posedge clock) begin - if(int_req == 1'b1 && int_en[0]) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + ret_addr <= 8'b0; + end else if(int_req == 1'b1 && int_en[0]) begin if(jmp_en) begin ret_addr <= rs_data; end else if(je_en && flag) begin @@ -106,16 +112,11 @@ end end - always @(posedge reset) begin - ret_addr<= 8'h00; - flag <= 1'b0; - pc <= 8'h00; - intr_en <= 1'b0; - _flag <= 1'b0; - end - - always @(posedge clock) begin - if(int_req && int_en[0]) begin + always @(posedge clock or posedge reset) begin + if(reset) begin + _flag <= 1'b0; + pc <= 8'b0; + end else if(int_req && int_en[0]) begin _flag <= flag; pc <= int_vec; end else if(ret) begin
diff --git a/verilog/rtl/jacaranda-8/wishbone.v b/verilog/rtl/jacaranda-8/wishbone.v index 2577f79..70bc797 100644 --- a/verilog/rtl/jacaranda-8/wishbone.v +++ b/verilog/rtl/jacaranda-8/wishbone.v
@@ -58,6 +58,10 @@ always @(posedge clk) begin if(reset) begin ready <= 1'b0; + instr_mem_addr <= 8'b0; + instr_mem_data <= 8'b0; + instr_mem_en <= 1'b0; + uart_freq <= 32'd50_000_000; end else begin if(ready) begin ready <= 1'b0;