fornow
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c94b7a0..2811b1e 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -32,7 +32,17 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+ $script_dir/../../verilog/rtl/user_project_wrapper.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/alu.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/cpu.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/decoder.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/alu_controller.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/computer.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/data_mem.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/instr_mem.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/main_controller.v \
+ $script_dir/../../verilog/rtl/jacaranda-8/regfile.v"
+
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 461733b..7354a20 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -156,29 +156,29 @@
end
end
- UART UART(.clk(wb_clk_i),
- .tx_en(tx_en),
- .rx_en(rx_en),
- .begin_flag(begin_flag),
- .rx(rx),
- .tx_data(tx_data),
- .tx(tx),
- .rx_data(rx_data),
- .busy_flag(busy_flag),
- .receive_flag(receive_flag),
- .int_req(int_req),
- .access_addr(rs_data),
- .reg_w_en(reg_w_en));
-
- LED4 LED4(.in_data(led_in_data),
- .begin_flag(led_begin_flag),
- .state_reg(led_state_reg),
- .out_data(led_out_data),
- .clock(wb_clk_i));
-
- nanaseg nanaseg(.bin_in(nanaseg_in_data),
- .seg_dig1(seg_out_1),
- .seg_dig2(seg_out_2),
- .seg_dig3(seg_out_3));
+// UART UART(.clk(wb_clk_i),
+// .tx_en(tx_en),
+// .rx_en(rx_en),
+// .begin_flag(begin_flag),
+// .rx(rx),
+// .tx_data(tx_data),
+// .tx(tx),
+// .rx_data(rx_data),
+// .busy_flag(busy_flag),
+// .receive_flag(receive_flag),
+// .int_req(int_req),
+// .access_addr(rs_data),
+// .reg_w_en(reg_w_en));
+//
+// LED4 LED4(.in_data(led_in_data),
+// .begin_flag(led_begin_flag),
+// .state_reg(led_state_reg),
+// .out_data(led_out_data),
+// .clock(wb_clk_i));
+//
+// nanaseg nanaseg(.bin_in(nanaseg_in_data),
+// .seg_dig1(seg_out_1),
+// .seg_dig2(seg_out_2),
+// .seg_dig3(seg_out_3));
endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..67113ee 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,13 @@
`else
`include "user_project_wrapper.v"
`include "user_proj_example.v"
-`endif
\ No newline at end of file
+ `include "jacaranda-8/alu.v"
+ `include "jacaranda-8/cpu.v"
+ `include "jacaranda-8/decoder.v"
+ `include "jacaranda-8/alu_controller.v"
+ `include "jacaranda-8/computer.v"
+ `include "jacaranda-8/data_mem.v"
+ `include "jacaranda-8/instr_mem.v"
+ `include "jacaranda-8/main_controller.v"
+ `include "jacaranda-8/regfile.v"
+`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..b4c9f64 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,7 +82,8 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+//user_proj_example mprj (
+computer computer (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
