ありがとうAhmed
diff --git a/gds/computer.gds.gz b/gds/computer.gds.gz
index 68667f0..408da89 100644
--- a/gds/computer.gds.gz
+++ b/gds/computer.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 0b624ab..a347b52 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/maglef/computer.mag b/maglef/computer.mag
index a396d14..ea98a6b 100644
--- a/maglef/computer.mag
+++ b/maglef/computer.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1636476711
+timestamp 1636622036
<< obsli1 >>
rect 1104 2159 198812 197489
<< obsm1 >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index d241aaf..682dbda 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1636477471
+timestamp 1636642865
<< obsli1 >>
rect 41429 2873 582423 540923
<< obsm1 >>
diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl
index e7e6944..79ff7a8 100644
--- a/openlane/computer/config.tcl
+++ b/openlane/computer/config.tcl
@@ -41,6 +41,12 @@
$script_dir/../../verilog/rtl/jacaranda-8/regfile.v \
$script_dir/../../verilog/rtl/jacaranda-8/wishbone.v"
+#set ::env(EXTRA_GDS_FILES) "\
+# $::env(PDK_ROOT)open_pdks/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__decap_12.gds"
+
+#set ::env(EXTRA_LEFS) "\
+# $::env(PDK_ROOT)open_pdks/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__decap_12.lef"
+
set ::env(CLOCK_PORT) wb_clk_i
set ::env(CLOCK_NET) wb_clk_i
set ::env(CLOCK_PERIOD) 500
@@ -53,6 +59,8 @@
#set ::env(FP_CORE_UTIL) 6
#set ::env(FP_SIZING) relative
+set ::(DECAP_CELL) "sky130_ef_sc_hd__decap_12"
+
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.2
diff --git a/openlane/computer/runs/computer/reports/final_summary_report.csv b/openlane/computer/runs/computer/reports/final_summary_report.csv
index 21c55f9..2033baf 100644
--- a/openlane/computer/runs/computer/reports/final_summary_report.csv
+++ b/openlane/computer/runs/computer/reports/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/computer,computer,computer,flow_completed,0h16m15s,-1,30982.0,1.0,15491.0,21.69,2007.01,15491,0,-1,-1,-1,-1,0,0,-1,0,0,-1,760979,168955,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,406501995.0,0.08,28.85,24.98,4.58,0.25,-1,9839,14827,645,5562,0,0,0,13616,0,0,0,0,0,0,0,4,5027,5129,42,718,13718,0,14436,1.996007984031936,501,500,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/computer,computer,computer,flow_completed,0h15m57s,-1,30982.0,1.0,15491.0,21.69,1994.01,15491,0,-1,-1,-1,-1,0,0,-1,0,0,-1,760979,168955,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,406501995.0,0.08,28.85,24.98,4.58,0.25,-1,9839,14827,645,5562,0,0,0,13616,0,0,0,0,0,0,0,4,5027,5129,42,718,13718,0,14436,1.996007984031936,501,500,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 80c8d8c..56b277f 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -35,6 +35,8 @@
set ::env(ROUTING_CORES) 16
+set ::(DECAP_CELL) "sky130_ef_sc_hd__decap_12"
+
## Clock configurations
set ::env(CLOCK_PORT) computer.wb_clk_i
set ::env(CLOCK_NET) computer.wb_clk_i
diff --git a/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv b/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv
index 5399c49..6ce5fdc 100644
--- a/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv
+++ b/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h8m30s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,601.44,1,0,0,0,0,0,0,0,0,0,-1,-1,1382954,2005,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40145.38,1.31,4.4,0.51,0.67,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1.996007984031936,501,500,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h8m29s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,602.36,1,0,0,0,0,0,0,0,0,0,-1,-1,1382954,2005,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40145.38,1.31,4.4,0.51,0.67,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1.996007984031936,501,500,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/computer/PDK_SOURCES b/signoff/computer/PDK_SOURCES
index 15a0b88..7bcd30f 100644
--- a/signoff/computer/PDK_SOURCES
+++ b/signoff/computer/PDK_SOURCES
@@ -1,3 +1,2 @@
-openlane e8f4a88f668b366f126bba40861153bf478a33c1
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
open_pdks 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/computer/final_summary_report.csv b/signoff/computer/final_summary_report.csv
index 21c55f9..2033baf 100644
--- a/signoff/computer/final_summary_report.csv
+++ b/signoff/computer/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/computer,computer,computer,flow_completed,0h16m15s,-1,30982.0,1.0,15491.0,21.69,2007.01,15491,0,-1,-1,-1,-1,0,0,-1,0,0,-1,760979,168955,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,406501995.0,0.08,28.85,24.98,4.58,0.25,-1,9839,14827,645,5562,0,0,0,13616,0,0,0,0,0,0,0,4,5027,5129,42,718,13718,0,14436,1.996007984031936,501,500,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/computer,computer,computer,flow_completed,0h15m57s,-1,30982.0,1.0,15491.0,21.69,1994.01,15491,0,-1,-1,-1,-1,0,0,-1,0,0,-1,760979,168955,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,406501995.0,0.08,28.85,24.98,4.58,0.25,-1,9839,14827,645,5562,0,0,0,13616,0,0,0,0,0,0,0,4,5027,5129,42,718,13718,0,14436,1.996007984031936,501,500,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 15a0b88..7bcd30f 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,3 +1,2 @@
-openlane e8f4a88f668b366f126bba40861153bf478a33c1
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
open_pdks 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 5399c49..6ce5fdc 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h8m30s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,601.44,1,0,0,0,0,0,0,0,0,0,-1,-1,1382954,2005,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40145.38,1.31,4.4,0.51,0.67,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1.996007984031936,501,500,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h8m29s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,602.36,1,0,0,0,0,0,0,0,0,0,-1,-1,1382954,2005,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40145.38,1.31,4.4,0.51,0.67,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1.996007984031936,501,500,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
