fornow
diff --git a/verilog/dv/jacaranda_test/Makefile b/verilog/dv/jacaranda_test/Makefile index cd42435..5c9e648 100644 --- a/verilog/dv/jacaranda_test/Makefile +++ b/verilog/dv/jacaranda_test/Makefile
@@ -42,7 +42,7 @@ PATTERN = jacaranda_test -all: ${PATTERN:=.vcd} +all: ${PATTERN:=.fst} hex: ${PATTERN:=.hex} @@ -59,7 +59,7 @@ $< -o $@ endif -%.vcd: %.vvp +%.fst: %.vvp vvp $< %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env @@ -91,6 +91,6 @@ # ---- Clean ---- clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + rm -f *.elf *.hex *.bin *.vvp *.fst *.log .PHONY: clean hex all
diff --git a/verilog/dv/jacaranda_test/jacaranda_test.c b/verilog/dv/jacaranda_test/jacaranda_test.c index a47ef4a..df7b26b 100644 --- a/verilog/dv/jacaranda_test/jacaranda_test.c +++ b/verilog/dv/jacaranda_test/jacaranda_test.c
@@ -21,25 +21,46 @@ // -------------------------------------------------------- +// -void main() +#define BASE_ADDR 0x30000000 +#define IMEM_WRITE (BASE_ADDR + 0x100) + +static void +write(uint32_t addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +void +reset() +{ + reg_la0_iena = 0; + reg_la0_oenb = 0; + + reg_la0_data = 0; +} + +void +main() { #include "instr.c" reg_spimaster_config = 0xa002; - // Configure LA probes [31:0] as inputs to the cpu - reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] + + reset(); // set reset to high - reg_la0_data = 1 << 16; + reg_la0_data = 1; - for(int i = 0; i < 256; ++i) - reg_la0_data = 1 << 16 | i << 8 | mem[i]; - + write(IMEM_WRITE + 0x00, 0b11000000); + write(IMEM_WRITE + 0x01, 0b11010000); + write(IMEM_WRITE + 0x02, 0b10110011); + // reg_la0_data = 1 << 16 | 0x00 << 8 | 0b11000000; // ldih 0 0xC0 // reg_la0_data = 1 << 16 | 0x01 << 8 | 0b11010000; // ldil 0 0xD0 // reg_la0_data = 1 << 16 | 0x02 << 8 | 0b10110011; // jmp r3 0xB3 - reg_la0_data = 0 << 16; + reg_la0_data = 0; while(1) {} }
diff --git a/verilog/dv/jacaranda_test/jacaranda_test_tb.v b/verilog/dv/jacaranda_test/jacaranda_test_tb.v index 3f480f0..ea5a2dc 100644 --- a/verilog/dv/jacaranda_test/jacaranda_test_tb.v +++ b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
@@ -42,11 +42,11 @@ end initial begin - $dumpfile("jacaranda_test.vcd"); + $dumpfile("jacaranda_test.fst"); $dumpvars(0, jacaranda_test_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (10) begin + repeat (30) begin repeat (1000) @(posedge clock); $display("+1000 cycles"); end
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v index cba21b7..2e84175 100644 --- a/verilog/rtl/jacaranda-8/computer.v +++ b/verilog/rtl/jacaranda-8/computer.v
@@ -88,22 +88,36 @@ wire [7:0] instr_mem_addr; wire [7:0] instr_mem_data; + wire instr_mem_en; wire reset; - assign reset = la_data_in[16]; - assign instr_mem_addr = reset ? la_data_in[15:8] : pc; - assign instr_mem_data = la_data_in[7:0]; + assign reset = la_data_in[0]; + wire clock; + assign clock = ~reset & wb_clk_i; + + wishbone wb(.wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbs_stb_i(wbs_stb_i), + .wbs_cyc_i(wbs_cyc_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o), + .wbs_dat_o(wbs_dat_o), + .instr_mem_addr(instr_mem_addr), + .instr_mem_data(instr_mem_data), + .instr_mem_en(instr_mem_en)); instr_mem instr_mem(.addr(instr_mem_addr), .w_data(instr_mem_data), - .w_en(reset), + .w_en(instr_mem_en), .r_data(instr), - .clock(wb_clk_i), - .reset(reset)); + .clock(wb_clk_i)); - cpu cpu(.raw_clock(wb_clk_i), + cpu cpu(.clock(clock), .reset(reset), .instr(instr), .pc(pc), @@ -116,14 +130,14 @@ .int_vec(int_vec), .reg_w_en(reg_w_en)); - always @(posedge wb_clk_i) begin + always @(posedge clock) begin if(rs_data == 8'd255 && mem_w_en == 1) begin tx_en <= rd_data[0]; rx_en <= rd_data[1]; end end - always @(posedge wb_clk_i) begin + always @(posedge clock) begin if(rs_data == 8'd253 && mem_w_en == 1) begin tx_data <= rd_data; begin_flag = 1; @@ -137,7 +151,7 @@ .w_data(rd_data), .w_en(mem_w_en), .r_data(_mem_r_data), - .clock(wb_clk_i)); + .clock(clock)); assign mem_r_data = (rs_data == 8'd254) ? {6'b0, receive_flag, busy_flag} : (rs_data == 8'd252) ? rx_data @@ -145,7 +159,7 @@ : (rs_data == 8'd249) ? led_state_reg : _mem_r_data; - always @(posedge wb_clk_i) begin + always @(posedge clock) begin if(rs_data == 8'd251 && mem_w_en == 1) begin led_in_data <= rd_data; led_begin_flag <= 1'b1; @@ -155,7 +169,7 @@ end end - always @(posedge wb_clk_i) begin + always @(posedge clock) begin if(rs_data == 8'd248 && mem_w_en == 1) begin nanaseg_in_data <= rd_data; end else begin @@ -165,7 +179,7 @@ //割り込み要求が立っている時は割り込み不許可 - always @(posedge wb_clk_i) begin + always @(posedge clock) begin if(int_req == 1'b1) begin int_en <= 8'h00; end else if(int_req == 1'b0) begin @@ -173,7 +187,7 @@ end end - always @(posedge wb_clk_i) begin + always @(posedge clock) begin //割り込みベクタの書き込み if(rs_data == 8'd250 && mem_w_en == 1'b1) begin int_vec <= rd_data; @@ -182,7 +196,7 @@ end end - UART UART(.clk(wb_clk_i), + UART UART(.clk(clock), .reset(reset), .tx_en(tx_en), .rx_en(rx_en),
diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v index d854802..d0f336a 100644 --- a/verilog/rtl/jacaranda-8/cpu.v +++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -1,5 +1,5 @@ -module cpu(raw_clock, reset, instr, pc, rd_data, rs_data, mem_w_en, mem_r_data, int_req, int_en, int_vec, reg_w_en); - input raw_clock; +module cpu(clock, reset, instr, pc, rd_data, rs_data, mem_w_en, mem_r_data, int_req, int_en, int_vec, reg_w_en); + input clock; input reset; input [7:0] instr; //割り込み要求線 @@ -37,9 +37,6 @@ //レジスタに書き込むデータをALUからのデータか選択する(1)でALUから(0)でそれ以外 wire reg_alu_w_sel; - wire clock; - assign clock = reset ? 1'b1 : raw_clock; - //ALUの制御信号 wire [3:0] alu_ctrl; //ALUからの出力
diff --git a/verilog/rtl/jacaranda-8/instr_mem.v b/verilog/rtl/jacaranda-8/instr_mem.v index ab1d7d5..115fb11 100644 --- a/verilog/rtl/jacaranda-8/instr_mem.v +++ b/verilog/rtl/jacaranda-8/instr_mem.v
@@ -1,14 +1,13 @@ -module instr_mem(addr, w_data, w_en, r_data, clock, reset); +module instr_mem(addr, w_data, w_en, r_data, clock); input [7:0] addr; input [7:0] w_data; input w_en; input clock; output [7:0] r_data; - input reset; reg [7:0] mem[0:255]; - assign r_data = reset ? 8'h00 : mem[addr]; + assign r_data = mem[addr]; always @(posedge clock) begin if(w_en) begin
diff --git a/verilog/rtl/jacaranda-8/wishbone.v b/verilog/rtl/jacaranda-8/wishbone.v new file mode 100644 index 0000000..57a1ded --- /dev/null +++ b/verilog/rtl/jacaranda-8/wishbone.v
@@ -0,0 +1,70 @@ +module wishbone( + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_adr_i, + input [31:0] wbs_dat_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + output reg [7:0] instr_mem_addr, + output reg [7:0] instr_mem_data, + output reg instr_mem_en +); + +// 0x3000_0100 - 0x3000_01FF: IMEM_WRITE +parameter IMEM_WRITE_PREFIX = 24'h3000_01; + +wire valid; +wire we; +wire [31:0] rdata; +wire [31:0] wdata; +wire [31:0] addr; +wire sel; +wire reset; +wire clk; +reg ready; + +assign valid = wbs_cyc_i & wbs_stb_i; +assign wbs_ack_o = ready; +assign we = wbs_we_i; +assign wbs_dat_o = rdata; +assign wdata = wbs_dat_i; +assign addr = wbs_adr_i; +assign sel = wbs_sel_i; + +assign reset = wb_rst_i; +assign clk = wb_clk_i; + +always @(posedge clk) begin + if(reset) begin + // reset + ready <= 1'b0; + end else begin + if(ready) begin + ready <= 1'b0; + instr_mem_en <= 1'b0; + end + // Read + if (valid && !ready && !we) begin + //case(addr) + //endcase + ready <= 1'b1; + // Write + end else if (valid && !ready && we) begin + case(addr[31:8]) + IMEM_WRITE_PREFIX: begin + instr_mem_addr <= addr[7:0]; + instr_mem_data <= wdata[7:0]; + instr_mem_en <= 1'b1; + end + endcase + ready <= 1'b1; + end + end +end +endmodule +
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index c8c2487..5ca1629 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -37,4 +37,5 @@ `include "jacaranda-8/instr_mem.v" `include "jacaranda-8/main_controller.v" `include "jacaranda-8/regfile.v" + `include "jacaranda-8/wishbone.v" `endif