commit	10b8f649476bfa7d69a0de7f486b9652c42fc418	[log] [tgz]
author	Yuki Azuma <yuhki.yasuda@gmail.com>	Tue Oct 05 15:52:38 2021 +0900
committer	Yuki Azuma <yuhki.yasuda@gmail.com>	Tue Oct 05 15:52:38 2021 +0900
tree	467dfad90a9d2c7c1c870c8f2e93da3899e2a0d4
parent	fc583ec64d0e153d10e4e28146342af0d0fecd6e [diff]

initial commit

verilog/rtl/jacaranda-8/7SEG/bin_dec_decoder.v[Added - diff]
verilog/rtl/jacaranda-8/7SEG/nanaseg.v[Added - diff]
verilog/rtl/jacaranda-8/7SEG/nanaseg_decoder.v[Added - diff]
verilog/rtl/jacaranda-8/LED/LED4.v[Added - diff]
verilog/rtl/jacaranda-8/Makefile[Added - diff]
verilog/rtl/jacaranda-8/UART/UART.v[Added - diff]
verilog/rtl/jacaranda-8/UART/rx.v[Added - diff]
verilog/rtl/jacaranda-8/UART/tx.v[Added - diff]
verilog/rtl/jacaranda-8/alu.v[Added - diff]
verilog/rtl/jacaranda-8/alu_controller.v[Added - diff]
verilog/rtl/jacaranda-8/computer.v[Added - diff]
verilog/rtl/jacaranda-8/cpu.v[Added - diff]
verilog/rtl/jacaranda-8/data_mem.v[Added - diff]
verilog/rtl/jacaranda-8/decoder.v[Added - diff]
verilog/rtl/jacaranda-8/instr_mem.v[Added - diff]
verilog/rtl/jacaranda-8/main_controller.v[Added - diff]
verilog/rtl/jacaranda-8/regfile.v[Added - diff]
verilog/rtl/jacaranda-8/test_bench.v[Added - diff]

18 files changed

tree: 467dfad90a9d2c7c1c870c8f2e93da3899e2a0d4

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.