Merge branch 'main' of https://github.com/efabless/caravel_project_example into main

verilog/dv/mprj_stimulus/Makefile

diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 8c5f729..d94ea22 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -59,7 +59,7 @@
 	vvp $<
 
 %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 

verilog/dv/mprj_stimulus/mprj_stimulus.c

diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 4b6d899..2fae0f1 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -15,7 +15,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "../../../caravel/verilog/dv/caravel/defs.h"
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
 
 // --------------------------------------------------------
 
@@ -23,7 +24,7 @@
 {
     // The upper GPIO pins are configured to be output
     // and accessble to the management SoC.
-    // Used to flad the start/end of a test
+    // Used to flag the start/end of a test
     // The lower GPIO pins are configured to be output
     // and accessible to the user project.  They show
     // the project count value, although this test is
@@ -37,12 +38,12 @@
     reg_mprj_datal = 0x00000000;
     reg_mprj_datah = 0x00000000;
 
-    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
     reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
     reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
 
     reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -87,12 +88,12 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    /* TEST:  Recast channels 37 to 34 to allow input to user project	*/
+    /* TEST:  Recast channels 35 to 32 to allow input to user project	*/
     /* This is done locally only:  Do not run reg_mprj_xfer!		*/
-    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
     reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
 
     // Configure LA probes [31:0], [127:64] as inputs to the cpu
     // Configure LA probes [63:32] as outputs from the cpu
@@ -115,9 +116,9 @@
 
     // Test ability to force data on channel 37
     // NOTE:  Only the low 6 bits of reg_mprj_datah are meaningful
-    reg_mprj_datah = 0xffffff28;
+    reg_mprj_datah = 0xffffffca;
     reg_mprj_datah = 0x00000000;
-    reg_mprj_datah = 0x0f0f0f14;
+    reg_mprj_datah = 0x0f0f0fc5;
     reg_mprj_datah = 0x00000000;
 
     // Test ability to read back data generated by the user project

verilog/dv/mprj_stimulus/mprj_stimulus_tb.v

diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 0aaca76..1409015 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -45,7 +45,7 @@
 
     // Signals Assignment
     assign checkbits  = mprj_io[31:16];
-    assign status = mprj_io[37:34];
+    assign status = mprj_io[35:32];
     assign uart_tx = mprj_io[6];
     assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
 

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7cf8dad..796d3aa 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -70,7 +70,7 @@
     // Note that analog I/O is not available on the 7 lowest-numbered
     // GPIO pads, and so the analog_io indexing is offset from the
     // GPIO indexing by 7.
-    inout [`MPRJ_IO_PADS-8:0] analog_io,
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
 
     // Independent clock (on independent integer divider)
     input   user_clock2