Fix comments broken by search-and-replace
diff --git a/verilog/rtl/cpu_core.v b/verilog/rtl/cpu_core.v
index bfe8830..930a627 100644
--- a/verilog/rtl/cpu_core.v
+++ b/verilog/rtl/cpu_core.v
@@ -99,12 +99,6 @@
100 000 1 00 0011 100 iiiiiiiiiiiiiiii
011 010 1 01 0011 011 jjjjjjjjjjjjjjjj
-Parameters:
-DATA_WIDTH = processor word size
-PC_WIDTH = size of program counter, should be <= `DATA_WIDTH
-ADDR_WIDTH = size of mem_mesh addresses, should be <= `DATA_WIDTH
-SPREAD_WIDTH = size of mem_mesh spread value
-INSTR_WIDTH = combined size of opcode & immediate, should be kept at 32
*/
module cpu_core (
@@ -130,15 +124,15 @@
reg [`DATA_WIDTH-1:0] reg1; // general-purpose registers
reg [`DATA_WIDTH-1:0] reg2;
-reg carry; // carry flag
+reg carry; // carry flag
reg [`DATA_WIDTH-1:0] pc; // register for program counter
reg [`DATA_WIDTH-1:0] timer; // clock ticks since last reset
reg [`ADDR_WIDTH-1:0] raddr; // next read address
-reg we; // write to memory on next cycle
+reg we; // write to memory on next cycle
reg [`ADDR_WIDTH-1:0] waddr; // next write address
reg [`SPREAD_WIDTH-1:0] wspread; // next write spread
reg [`DATA_WIDTH-1:0] wdata; // next write data
-reg stopped; // cpu core is stopped
+reg stopped; // cpu core is stopped
assign progctr = pc;
assign mem_we = we;
@@ -187,12 +181,12 @@
wire in1_oh = in1_orig[`DATA_WIDTH-1]; // highest bit of in1_orig
wire [`DATA_WIDTH-1:0] in1 = op_extra_carry ? op_immed : in1_orig; // data to use as alu input 1
wire [`DATA_WIDTH-1:0] in2 = sources2[op_in2]; // data to use as alu input 2
-wire carry_def = op_rst_carry ? 0 : carry; // carry to use as alu input, unless overridden by op_extra_carry
-wire carry_ovr = op_rst_carry ? ~in1_oh : in1_oh; // override value if op_extra_carry is set
-wire alu_cin = op_extra_carry ? carry_ovr : carry_def; // consolidated carry input for alu
+wire carry_def = op_rst_carry ? 0 : carry; // carry to use as alu input, unless overridden by op_extra_carry
+wire carry_ovr = op_rst_carry ? ~in1_oh : in1_oh; // override value if op_extra_carry is set
+wire alu_cin = op_extra_carry ? carry_ovr : carry_def; // consolidated carry input for alu
wire [`DATA_WIDTH-1:0] alu_out; // data output from alu
-wire alu_cout; // carry output from alu
+wire alu_cout; // carry output from alu
alu alu_inst (
.opcode(op_alu),
diff --git a/verilog/rtl/debug_mux.v b/verilog/rtl/debug_mux.v
index a4b5149..04709a7 100644
--- a/verilog/rtl/debug_mux.v
+++ b/verilog/rtl/debug_mux.v
@@ -12,7 +12,7 @@
module debug_mux (
input [`LOG_CORES-1:0] sel, // controller interface
- input [4:0] addr, // 0xxxx affects status register xxxx, 10000 affects running/stopped state
+ input [4:0] addr, // 0xxxx affects status register xxxx, 10000 affects running/stopped state
input we,
input [`DATA_WIDTH-1:0] wdata,
output [`DATA_WIDTH-1:0] rdata,
diff --git a/verilog/rtl/io_pads.v b/verilog/rtl/io_pads.v
index 8fd7714..d6769dd 100644
--- a/verilog/rtl/io_pads.v
+++ b/verilog/rtl/io_pads.v
@@ -5,11 +5,6 @@
/*
Connection to Caravel IO pads & logic analyzer
-
-IO_PINS = logical pins accessible for the program running on the cpu cores
-IO_PADS = pads made available by Caravel for user projects (maps to MPRJ_IO_PADS)
-LOGIC_PROBES = logic analyzer probes
-FIRST_PAD = map pin 0 to pad `FIRST_PAD, pin 1 to pad `FIRST_PAD+1 etc.
*/
module io_pads (
@@ -46,10 +41,10 @@
assign rst_soft_n = la_oenb[2] ? (!wb_rst_i & !programming) : la_data_in[2];
assign rst_prng_n = la_oenb[3] ? !wb_rst_i : la_data_in[3];
-localparam LA_DIR = 4; // index of logic analyzer probes for pin directions
-localparam LA_PIN = LA_DIR + `IO_PINS; // index of logic analyzer probes for pin values
-localparam LA_PAD = LA_PIN + `IO_PINS; // index of logic analyzer probes for pad values
-localparam LA_END = LA_PAD + `IO_PADS; // index of first unused logic analyzer probe
+localparam LA_DIR = 4; // index of logic analyzer probes for pin directions
+localparam LA_PIN = LA_DIR + `IO_PINS; // index of logic analyzer probes for pin values
+localparam LA_PAD = LA_PIN + `IO_PINS; // index of logic analyzer probes for pad values
+localparam LA_END = LA_PAD + `IO_PADS; // index of first unused logic analyzer probe
localparam LA_REM = `LOGIC_PROBES - LA_END; // unused logic analyzer probes
localparam PAD_REM = `IO_PADS - `IO_PINS - `FIRST_PAD; // unused pads remaining after the last io pin
diff --git a/verilog/rtl/mcu.v b/verilog/rtl/mcu.v
index 0f65f18..9abc600 100644
--- a/verilog/rtl/mcu.v
+++ b/verilog/rtl/mcu.v
@@ -33,14 +33,14 @@
*/
module mcu (
- input wb_clk_i, // wishbone clock
- input wb_rst_i, // wb reset, active high
- input wbs_stb_i, // wb strobe
- input wbs_cyc_i, // wb cycle
- input wbs_we_i, // wb write enable
+ input wb_clk_i, // wishbone clock
+ input wb_rst_i, // wb reset, active high
+ input wbs_stb_i, // wb strobe
+ input wbs_cyc_i, // wb cycle
+ input wbs_we_i, // wb write enable
input [`WB_WIDTH-1:0] wbs_adr_i, // wb address
input [`WB_WIDTH-1:0] wbs_dat_i, // wb input data
- output wbs_ack_o, // wb acknowledge
+ output wbs_ack_o, // wb acknowledge
output [`WB_WIDTH-1:0] wbs_dat_o, // wb output data
input [`LOGIC_PROBES-1:0] la_data_in, // logic analyzer probes input
output [`LOGIC_PROBES-1:0] la_data_out, // la probes output
@@ -99,10 +99,10 @@
wire [`CORES*`INSTR_WIDTH-1:0] im_wdata_raw; // im < pmux
// between memory mesh and io filter
-wire [MEM_IO_PORTS-1:0] mem_io_active_in; // mesh < iof
-wire [MEM_IO_PORTS-1:0] mem_io_active_out; // mesh > iof
-wire [MEM_IO_PORTS*`DATA_WIDTH-1:0] mem_io_data_in; // mesh < iof
-wire [MEM_IO_PORTS*`DATA_WIDTH-1:0] mem_io_data_out; // mesh > iof
+wire [MEM_IO_PORTS-1:0] mem_io_active_in; // mesh < iof
+wire [MEM_IO_PORTS-1:0] mem_io_active_out; // mesh > iof
+wire [MEM_IO_PORTS*`DATA_WIDTH-1:0] mem_io_data_in; // mesh < iof
+wire [MEM_IO_PORTS*`DATA_WIDTH-1:0] mem_io_data_out; // mesh > iof
// between debugging multiplexer and cpu core (unpacked versions for cpu core)
wire [1:0] debug_cpu_mode[`CORES-1:0]; // dmux > cpu
@@ -121,28 +121,28 @@
wire [`CORES*`DATA_WIDTH-1:0] debug_reg_rdata_raw; // dmux < cpu
// between wishbone multiplexer and programming multiplexer
-wire prog_we; // wbmux > pmux
-wire [`LOG_CORES-1:0] prog_sel; // wbmux > pmux
-wire [`PC_WIDTH-1:0] prog_waddr; // wbmux > pmux
-wire [`INSTR_WIDTH-1:0] prog_wdata; // wbmux > pmux
+wire prog_we; // wbmux > pmux
+wire [`LOG_CORES-1:0] prog_sel; // wbmux > pmux
+wire [`PC_WIDTH-1:0] prog_waddr; // wbmux > pmux
+wire [`INSTR_WIDTH-1:0] prog_wdata; // wbmux > pmux
// between wishbone multiplexer and io pads
-wire pads_we; // wbmux > pads
-wire pads_waddr; // wbmux > pads
-wire [`IO_PINS-1:0] pads_wdata; // wbmux > pads
+wire pads_we; // wbmux > pads
+wire pads_waddr; // wbmux > pads
+wire [`IO_PINS-1:0] pads_wdata; // wbmux > pads
// between wishbone multiplexer and debugging multiplexer
-wire [`LOG_CORES-1:0] debug_sel; // wbmux > dmux
-wire [4:0] debug_addr; // wbmux > dmux
-wire debug_we; // wbmux > dmux
-wire [`DATA_WIDTH-1:0] debug_wdata; // wbmux > dmux
-wire [`DATA_WIDTH-1:0] debug_rdata; // wbmux < dmux
+wire [`LOG_CORES-1:0] debug_sel; // wbmux > dmux
+wire [4:0] debug_addr; // wbmux > dmux
+wire debug_we; // wbmux > dmux
+wire [`DATA_WIDTH-1:0] debug_wdata; // wbmux > dmux
+wire [`DATA_WIDTH-1:0] debug_rdata; // wbmux < dmux
// between wishbone multiplexer and entropy pool
-wire [`WB_WIDTH-1:0] entropy_word; // wbmux > ep
+wire [`WB_WIDTH-1:0] entropy_word; // wbmux > ep
// between entropy pool and prng's
-wire entropy_bit; // ep > prng
+wire entropy_bit; // ep > prng
// repeat for each cpu core
generate genvar core;
diff --git a/verilog/rtl/mem_mesh.v b/verilog/rtl/mem_mesh.v
index 25a219c..5e18600 100644
--- a/verilog/rtl/mem_mesh.v
+++ b/verilog/rtl/mem_mesh.v
@@ -6,45 +6,34 @@
/*
Generates a DFF RAM block for each core with a tree-like interconnect mesh between them
-Parameters:
-`CORES = number of cpu cores, also specifies the number of ram blocks
-`MEM_DEPTH = number of words per ram block
-`DATA_WIDTH = word size, number of bits per memory cell
-`ADDR_WIDTH = address bus width, should be clog2(`MEM_DEPTH)
-`LOG_CORES = number of spread layers, should be clog2(`CORES)
-`SPREAD_WIDTH = spread bus width, should be clog2(2+`LOG_CORES)
-`MEM_IO_PORTS = number of io ports, should be <= `MEM_DEPTH
-`MEM_IO_FIRST = memory cell mapped to the first io port
-`MEM_IO_LAST1 = memory cell mapped to the last io port + 1
-
A value of wspread > 0 on write operations specifies that the same address should also be written in some
other memory blocks. In particular, blocks whose number only differ in the lowest wspread bits are affected.
If several simultaneous write operations affect the same memory cell, writes with higher wspread have
priority. For writes having equal wspread the core with the lowest number wins.
-If addresses < IO_BUS_WIDTH are written with wspread > `LOG_CORES, wdata is also sent to the io bus.
+If addresses >= `MEM_IO_FIRST are written with wspread > `LOG_CORES, wdata is also sent to the io bus.
Incoming data on the io bus is written to the respective cells with maximal spread (affecting all cores).
*/
module mem_mesh (
- input clk, // clock signal
- input rst_n, // reset, active low
- input [`CORES-1:0] we, // write enable
- input [`CORES*`ADDR_WIDTH-1:0] waddr, // write address
- input [`CORES*`SPREAD_WIDTH-1:0] wspread, // write spread
- input [`CORES*`DATA_WIDTH-1:0] wdata, // write data
- input [`CORES*`ADDR_WIDTH-1:0] raddr, // read address
- output [`CORES*`DATA_WIDTH-1:0] rdata, // read data
- input [`MEM_IO_PORTS-1:0] io_active_in, // is receiving data on io bus
- output [`MEM_IO_PORTS-1:0] io_active_out, // is sending data on io bus
+ input clk, // clock signal
+ input rst_n, // reset, active low
+ input [`CORES-1:0] we, // write enable
+ input [`CORES*`ADDR_WIDTH-1:0] waddr, // write address
+ input [`CORES*`SPREAD_WIDTH-1:0] wspread, // write spread
+ input [`CORES*`DATA_WIDTH-1:0] wdata, // write data
+ input [`CORES*`ADDR_WIDTH-1:0] raddr, // read address
+ output [`CORES*`DATA_WIDTH-1:0] rdata, // read data
+ input [`MEM_IO_PORTS-1:0] io_active_in, // is receiving data on io bus
+ output [`MEM_IO_PORTS-1:0] io_active_out, // is sending data on io bus
input [`MEM_IO_PORTS*`DATA_WIDTH-1:0] io_data_in, // io bus input
output [`MEM_IO_PORTS*`DATA_WIDTH-1:0] io_data_out // io bus output
);
reg [`DATA_WIDTH-1:0] mem[`CORES-1:0][`MEM_DEPTH-1:0]; // memory cells
-wire presel[`CORES-1:0][`MEM_DEPTH-1:0]; // is address selected before spreading
-wire uspread[`CORES-1:0][`LOG_CORES+1-1:0]; // is spreading to layer
-wire postsel[`CORES-1:0][`MEM_DEPTH-1:0]; // is address selected after spreading
+wire presel[`CORES-1:0][`MEM_DEPTH-1:0]; // is address selected before spreading
+wire uspread[`CORES-1:0][`LOG_CORES+1-1:0]; // is spreading to layer
+wire postsel[`CORES-1:0][`MEM_DEPTH-1:0]; // is address selected after spreading
wire [`DATA_WIDTH-1:0] postdata[`CORES-1:0][`MEM_DEPTH-1:0]; // data to be written after spreading
generate genvar core, addr, layer, group, spl;
diff --git a/verilog/rtl/prng.v b/verilog/rtl/prng.v
index 2a2fa89..9bdfef6 100644
--- a/verilog/rtl/prng.v
+++ b/verilog/rtl/prng.v
@@ -5,19 +5,15 @@
/*
Pseudorandom number generator using a Fibonacci-style XNOR linear feedback shift register
-
-`PRNG_STATE_BITS = number of bits for prng state
-POLYNOMIAL = bit mask used for feedback, should be chosen so that the prng repeats ifself after 2^(`PRNG_STATE_BITS-1) cycles
-STATE_INIT = used to seed the prng on reset
-`DATA_WIDTH = number of bits shifted out every clock cycle
*/
module prng (
input clk,
input rst_n,
- input [`PRNG_STATE_BITS-1:0] polynomial,
- input [`PRNG_STATE_BITS-1:0] state_init,
- input entropy, // optional external entropy for more randomness
+ input [`PRNG_STATE_BITS-1:0] polynomial, // bit mask used for feedback, should be chosen so that
+ // the prng repeats ifself after 2^(`PRNG_STATE_BITS-1) cycles
+ input [`PRNG_STATE_BITS-1:0] state_init, // used to seed the prng on reset
+ input entropy, // optional external entropy for more randomness
output [`DATA_WIDTH-1:0] random
);
diff --git a/verilog/rtl/prng_wrap.v b/verilog/rtl/prng_wrap.v
index 9bb2290..c8d3d75 100644
--- a/verilog/rtl/prng_wrap.v
+++ b/verilog/rtl/prng_wrap.v
@@ -6,7 +6,7 @@
/*
Wrapper for prng with known good polynomials (having a cycle length of 2^32-1 and a minimal bit count)
-Different choices of 0 <= INDEX < 256 generate independent prng's. For even more, the table below should be extended.
+Different choices of 0 <= index < 256 generate independent prng's. For even more, the table below should be extended.
*/
module prng_wrap (
