commit 9512e73aa3f0db800dd354187ef76ff0c05a939f
author Tamas Hubai <mpw@htamas.net> Wed Oct 27 00:31:25 2021 +0200
committer Tamas Hubai <mpw@htamas.net> Wed Oct 27 00:31:25 2021 +0200
tree 1618d803869ff49e33df8d8853a345cb751b8a7c
parent bfcdc2c360b506201540e7ff32506d113797b328

Refactor shift in alu that yosys complained about

verilog/rtl/alu.v

diff --git a/verilog/rtl/alu.v b/verilog/rtl/alu.v
index 9a72dee..75894e0 100644
--- a/verilog/rtl/alu.v
+++ b/verilog/rtl/alu.v
@@ -133,7 +133,7 @@
          assign subseq = in1d;
       end else begin:i_nfirst
          wire [i+1:0] index = {log_bits[i+1], {(i+1){1'b0}}};
-         assign subseq = g_bit[i+1].subseq[index +: 1<<(i+1)];
+         assign subseq = g_bit[i+1].subseq >> index;
       end
       assign log_bits[i] = |subseq[1<<i +: 1<<i];
    end