commit: ad46115ba4a965b4d01ccfc81afdfca17e52798a
[log] [tgz]
author: Tamas Hubai <mpw@htamas.net>
Wed Oct 27 11:20:26 2021 +0200
committer: Tamas Hubai <mpw@htamas.net>
Wed Oct 27 11:20:26 2021 +0200
tree: 4c37f42d68771895558e47f537859fdfbd4c838d
parent: 485ef63e6e059e48ee0a6672ebb83955d7762159 [diff]

Qualify spread & collect in mem_mesh for yosys

verilog/rtl/mem_mesh.v[diff]

1 file changed

tree: 4c37f42d68771895558e47f537859fdfbd4c838d

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.