commit	86056735f8974f88f928c182697549212d22720e	[log] [tgz]
author	Tamas Hubai <mpw@htamas.net>	Mon Nov 15 12:10:23 2021 +0100
committer	Tamas Hubai <mpw@htamas.net>	Mon Nov 15 12:10:23 2021 +0100
tree	fa65bad58990c6a8966462a4cb1b2f8a6b14f315
parent	9d4892197408ae6e4fa411c630ab5afaf90293de [diff]

Clean example repo for new project

def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
docs/source/index.rst[diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
openlane/user_project/config.json[Renamed from openlane/user_proj_example/config.json - diff]
openlane/user_project/config.tcl[Renamed from openlane/user_proj_example/config.tcl - diff]
openlane/user_project/pin_order.cfg[Renamed from openlane/user_proj_example/pin_order.cfg - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/config.tcl[diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_proj_example/PDK_SOURCES[Deleted - diff]
signoff/user_proj_example/final_summary_report.csv[Deleted - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Deleted - diff]
signoff/user_project_wrapper/PDK_SOURCES[Deleted - diff]
signoff/user_project_wrapper/final_summary_report.csv[Deleted - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project.v[Renamed from verilog/rtl/user_proj_example.v - diff]
verilog/rtl/user_project_wrapper.v[diff]

46 files changed

tree: fa65bad58990c6a8966462a4cb1b2f8a6b14f315

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.