add README
diff --git a/README.md b/README.md
index b6dd62f..4b98435 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,5 @@
# Pre-Trained Neural Network for MNIST
-This project implements a pre-trained neural network for hand-written digits from MNIST dataset.
\ No newline at end of file
+This project implements a pre-trained fully connected neural network (FCNN) for hand-written digits from MNIST dataset. It takes images from MNIST dataset (28x28) and output single digit prediction. All parameters (weights and bias) are pre-trained and hard-coded.
+
+This repository contains a Verilog implementation of the FCNN, targeting the OpenLane flow for the Skywater 130nm process and is an entry for the Google/Efabless MPW-3 shuttle.
\ No newline at end of file
diff --git a/verilog/rtl/LICENSE b/verilog/rtl/LICENSE
new file mode 100644
index 0000000..7190840
--- /dev/null
+++ b/verilog/rtl/LICENSE
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2020 Vipin Kizheppatt
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 351d409..65ca516 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -244,200 +244,6 @@
end
end
- // wire [`numNeuronLayer2-1:0] o2_valid;
- // wire [`numNeuronLayer2*`dataWidth-1:0] x2_out;
- // reg [`numNeuronLayer2*`dataWidth-1:0] holdData_2;
- // reg [`dataWidth-1:0] out_data_2;
- // reg data_out_valid_2;
-
- // Layer_2 #(.NN(`numNeuronLayer2),.numWeight(`numWeightLayer2),.dataWidth(`dataWidth),.layerNum(2),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer2ActType)) l2(
- // .clk(clk),
- // .rst(reset),
- // // .weightValid(weightValid),
- // // .biasValid(biasValid),
- // // .weightValue(weightValue),
- // // .biasValue(biasValue),
- // // .config_layer_num(config_layer_num),
- // // .config_neuron_num(config_neuron_num),
- // .x_valid(data_out_valid_1),
- // .x_in(out_data_1),
- // .o_valid(o2_valid),
- // .x_out(x2_out)
- // );
-
- // //State machine for data pipelining
-
- // reg state_2;
- // integer count_2;
- // always @(posedge clk)
- // begin
- // if(reset)
- // begin
- // state_2 <= IDLE;
- // count_2 <= 0;
- // data_out_valid_2 <=0;
- // end
- // else
- // begin
- // case(state_2)
- // IDLE: begin
- // count_2 <= 0;
- // data_out_valid_2 <=0;
- // if (o2_valid[0] == 1'b1)
- // begin
- // holdData_2 <= x2_out;
- // state_2 <= SEND;
- // end
- // end
- // SEND: begin
- // out_data_2 <= holdData_2[`dataWidth-1:0];
- // holdData_2 <= holdData_2>>`dataWidth;
- // count_2 <= count_2 +1;
- // data_out_valid_2 <= 1;
- // if (count_2 == `numNeuronLayer2)
- // begin
- // state_2 <= IDLE;
- // data_out_valid_2 <= 0;
- // end
- // end
- // endcase
- // end
- // end
-
- // wire [`numNeuronLayer3-1:0] o3_valid;
- // wire [`numNeuronLayer3*`dataWidth-1:0] x3_out;
- // reg [`numNeuronLayer3*`dataWidth-1:0] holdData_3;
- // reg [`dataWidth-1:0] out_data_3;
- // reg data_out_valid_3;
-
- // Layer_3 #(.NN(`numNeuronLayer3),.numWeight(`numWeightLayer3),.dataWidth(`dataWidth),.layerNum(3),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer3ActType)) l3(
- // .clk(clk),
- // .rst(reset),
- // // .weightValid(weightValid),
- // // .biasValid(biasValid),
- // // .weightValue(weightValue),
- // // .biasValue(biasValue),
- // // .config_layer_num(config_layer_num),
- // // .config_neuron_num(config_neuron_num),
- // .x_valid(data_out_valid_2),
- // .x_in(out_data_2),
- // .o_valid(o3_valid),
- // .x_out(x3_out)
- // );
-
- // //State machine for data pipelining
-
- // reg state_3;
- // integer count_3;
- // always @(posedge clk)
- // begin
- // if(reset)
- // begin
- // state_3 <= IDLE;
- // count_3 <= 0;
- // data_out_valid_3 <=0;
- // end
- // else
- // begin
- // case(state_3)
- // IDLE: begin
- // count_3 <= 0;
- // data_out_valid_3 <=0;
- // if (o3_valid[0] == 1'b1)
- // begin
- // holdData_3 <= x3_out;
- // state_3 <= SEND;
- // end
- // end
- // SEND: begin
- // out_data_3 <= holdData_3[`dataWidth-1:0];
- // holdData_3 <= holdData_3>>`dataWidth;
- // count_3 <= count_3 +1;
- // data_out_valid_3 <= 1;
- // if (count_3 == `numNeuronLayer3)
- // begin
- // state_3 <= IDLE;
- // data_out_valid_3 <= 0;
- // end
- // end
- // endcase
- // end
- // end
-
- // wire [`numNeuronLayer4-1:0] o4_valid;
- // wire [`numNeuronLayer4*`dataWidth-1:0] x4_out;
- // reg [`numNeuronLayer4*`dataWidth-1:0] holdData_4;
- // reg [`dataWidth-1:0] out_data_4;
- // reg data_out_valid_4;
-
- // Layer_4 #(.NN(`numNeuronLayer4),.numWeight(`numWeightLayer4),.dataWidth(`dataWidth),.layerNum(4),.sigmoidSize(`sigmoidSize),.weightIntWidth(`weightIntWidth),.actType(`Layer4ActType)) l4(
- // .clk(clk),
- // .rst(reset),
- // // .weightValid(weightValid),
- // // .biasValid(biasValid),
- // // .weightValue(weightValue),
- // // .biasValue(biasValue),
- // // .config_layer_num(config_layer_num),
- // // .config_neuron_num(config_neuron_num),
- // .x_valid(data_out_valid_1),
- // .x_in(out_data_1),
- // .o_valid(o4_valid),
- // .x_out(x4_out)
- // );
-
- // //State machine for data pipelining
-
- // reg state_4;
- // integer count_4;
- // always @(posedge clk)
- // begin
- // if(reset)
- // begin
- // state_4 <= IDLE;
- // count_4 <= 0;
- // data_out_valid_4 <=0;
- // end
- // else
- // begin
- // case(state_4)
- // IDLE: begin
- // count_4 <= 0;
- // data_out_valid_4 <=0;
- // if (o4_valid[0] == 1'b1)
- // begin
- // holdData_4 <= x4_out;
- // state_4 <= SEND;
- // end
- // end
- // SEND: begin
- // out_data_4 <= holdData_4[`dataWidth-1:0];
- // holdData_4 <= holdData_4>>`dataWidth;
- // count_4 <= count_4 +1;
- // data_out_valid_4 <= 1;
- // if (count_4 == `numNeuronLayer4)
- // begin
- // state_4 <= IDLE;
- // data_out_valid_4 <= 0;
- // end
- // end
- // endcase
- // end
- // end
-
- // reg [`numNeuronLayer4*`dataWidth-1:0] holdData_5;
- // assign rdata = holdData_5[`dataWidth-1:0];
-
- // always @(posedge clk)
- // begin
- // if (o4_valid[0] == 1'b1)
- // holdData_5 <= x4_out;
- // else if(!ready)
- // begin
- // holdData_5 <= holdData_5>>`dataWidth;
- // end
- // end
-
-
maxFinder #(.numInput(`numNeuronLayer1),.inputWidth(`dataWidth))
mFind(
.i_clk(clk),
@@ -447,91 +253,6 @@
.o_data_valid(out_valid)
);
- // always @(posedge clk) begin
- // if(rst)
- // count <= 32'b0;
- // else if(wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i == USER_ADDRESS) begin
- // count <= wbs_dat_i;
- // end
- // end
-
- // // acks
- // always @(posedge clk) begin
- // if(rst)
- // wack <= 0;
- // else
- // // return ack immediately
- // wack <= (wbs_stb_i && wbs_adr_i == USER_ADDRESS);
- // end
-
endmodule
-
-// reg ready;
-// reg [BITS-1:0] count;
-// reg [BITS-1:0] rdata;
-
-// always @(posedge clk) begin
-// if (reset) begin
-// count <= 0;
-// ready <= 0;
-// end else begin
-// ready <= 1'b0;
-// count <= count + 1;
-
-// if (valid && !ready) begin
-// ready <= 1'b1;
-// rdata <= count;
-// if (wstrb[0]) count[7:0] <= wdata[7:0];
-// if (wstrb[1]) count[15:8] <= wdata[15:8];
-// if (wstrb[2]) count[23:16] <= wdata[23:16];
-// if (wstrb[3]) count[31:24] <= wdata[31:24];
-// end
-// end
-// end
-
-// endmodule
-
-// module counter #(
-// parameter BITS = 32
-// )(
-// input clk,
-// input reset,
-// input valid,
-// input [3:0] wstrb,
-// input [BITS-1:0] wdata,
-// input [BITS-1:0] la_write,
-// input [BITS-1:0] la_input,
-// output ready,
-// output [BITS-1:0] rdata,
-// output [BITS-1:0] count
-// );
-// reg ready;
-// reg [BITS-1:0] count;
-// reg [BITS-1:0] rdata;
-
-// always @(posedge clk) begin
-// if (reset) begin
-// count <= 0;
-// ready <= 0;
-// end else begin
-// ready <= 1'b0;
-// if (~|la_write) begin
-// count <= count + 1;
-// end
-// if (valid && !ready) begin
-// ready <= 1'b1;
-// rdata <= count;
-// if (wstrb[0]) count[7:0] <= wdata[7:0];
-// if (wstrb[1]) count[15:8] <= wdata[15:8];
-// if (wstrb[2]) count[23:16] <= wdata[23:16];
-// if (wstrb[3]) count[31:24] <= wdata[31:24];
-// end else if (|la_write) begin
-// count <= la_write & la_input;
-// end
-// end
-// end
-
-// endmodule
-
`default_nettype wire
