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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-003
/
slot-016
/
f068a8db75e884fd18d192dc24921d161df00857
commit
f068a8db75e884fd18d192dc24921d161df00857
[
log
]
author
manarabdelaty <manarabdelatty@aucegypt.edu>
Thu Sep 02 19:30:49 2021 +0200
committer
manarabdelaty <manarabdelatty@aucegypt.edu>
Thu Sep 02 19:30:49 2021 +0200
tree
e9390c840f6382a2875f7812420bfe63f87a689f
parent
a734b9443f0d48cd098b579cc9e69d0ecd8ba13e
[
diff
]
Update Makefile to work with EF style
verilog/dv/mprj_por/Makefile
[
diff
]
1 file changed
tree: e9390c840f6382a2875f7812420bfe63f87a689f
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.