commit	0c573eb941f5b7183d31bdb3b578504973e06cc6	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Tue Sep 28 10:50:49 2021 -0400
committer	Tim Edwards <tim@opencircuitdesign.com>	Tue Sep 28 10:50:49 2021 -0400
tree	ac34c32719e92a95375578a447b5324b10c11f4d
parent	1675c2dfe438548385188f218e9b961347bb0bf8 [diff]

Modified the user_analog_project_wrapper layouts (empty and example)
to add the metal4 and metal5 layers on io_analog[6:4] that are part
of the top level layout.  This will show users where the layers are
so that they do not route close enough to create DRC violations where
they cannot see them.

mag/user_analog_project_wrapper.mag[diff]
mag/user_analog_project_wrapper_empty.mag[diff]

2 files changed

tree: ac34c32719e92a95375578a447b5324b10c11f4d

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.