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1c44e4c5bd0288eb53431e271d29ae272f7a7939
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1c44e4c5bd0288eb53431e271d29ae272f7a7939
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author
manarabdelaty <manarabdelatty@aucegypt.edu>
Sat May 08 18:32:32 2021 +0200
committer
manarabdelaty <manarabdelatty@aucegypt.edu>
Sat May 08 18:32:32 2021 +0200
tree
25983ce662c2bcd49d9e0e7a2672aa355eb5b058
parent
5e6a144956639585352ed90c83efb5af97f3b2c4
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Doc updates
docs/source/index.rst
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verilog/dv/README.md
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tree: 25983ce662c2bcd49d9e0e7a2672aa355eb5b058
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.