aligned the sram data output with wishbone ack
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index cce0713..45016e1 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -30,6 +30,7 @@
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
+ input [`DATA_SIZE-1:0] wbs_sram8_data,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// SRAM data outputs to be captured
@@ -106,6 +107,7 @@
wire [31:0] ram_din0;
wire [31:0] ram_dout0;
+
always @ (posedge clk) begin
if(!resetn) begin
sram_register <= {`TOTAL_SIZE{1'b0}};
@@ -128,7 +130,6 @@
sram_register[`WMASK_SIZE+1:0]};
end
end
-
wishbone_wrapper WRAPPER(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -146,14 +147,14 @@
.ram_web0(ram_web0), // (output) active low write control
.ram_wmask0(ram_wmask0), // (output) write (byte) mask
.ram_addr0(ram_addr0), // (output)
- .ram_din0(read_data0), // (input) read from sram and sent through wb
+ .ram_din0(wbs_sram8_data), // (input) read from sram and sent through wb
.ram_dout0(ram_din0) // (output) read from wb and sent to sram
);
// Splitting register bits into fields
always @(*) begin
if(wbs_stb_i && wbs_cyc_i) begin
- chip_select = 0;
+ chip_select = 8;
csb0_temp = ram_csb0;
addr0 = ram_addr0;
din0 = ram_din0;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bfdfc21..8a6fe42 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -158,6 +158,7 @@
.wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
+ .wbs_sram8_data(sram8_dout0),
// Shared control/data to the SRAMs
.addr0(addr0),
.din0(din0),
@@ -241,7 +242,6 @@
wire [`DATA_SIZE-1:0] sram15_dout0 = 0;
wire [`DATA_SIZE-1:0] sram15_dout1 = 0;
-// temporarily making this sram 8
sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
(
`ifdef USE_POWER_PINS
@@ -365,7 +365,6 @@
wire disconn8, disconn9, disconn10, disconn11, disconn12;
-// temporarily making this sram 0
sky130_sram_1kbyte_1rw_32x256_8 SRAM8
(
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/wishbone_wrapper.v b/verilog/rtl/wishbone_wrapper.v
index 10e4b33..e5ffb3f 100644
--- a/verilog/rtl/wishbone_wrapper.v
+++ b/verilog/rtl/wishbone_wrapper.v
@@ -39,7 +39,6 @@
wire ram_cs;
assign ram_cs = wbs_stb_i && wbs_cyc_i && ((wbs_adr_i & ADDR_HI_MASK) == BASE_ADDR) && !wb_rst_i;
-
reg ram_cs_r;
reg ram_wbs_ack_r;
always @(negedge wb_clk_i) begin
