Add back clocks and fix verilog path.
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index a9b5d79..3ce11b8 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -1,7 +1,7 @@
## Clock configurations
-set ::env(CLOCK_PORT) {io_in[17]}
+set ::env(CLOCK_PORT) {io_in\[17\]}
set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
-set ::env(RESET_PORT) {io_in[15] wb_rst_i}
+set ::env(RESET_PORT) {io_in\[15\] wb_rst_i}
set ::env(CLOCK_PERIOD) "30"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 3840603..64b5789 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -107,7 +107,8 @@
set ::env(RUN_KLAYOUT_XOR) 0
# Spray diodes
-set ::env(DIODE_INSERTION_STRATEGY) 1
+set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FILL_INSERTION) 1
# The following is because there are no std cells in the example wrapper project.
#set ::env(SYNTH_TOP_LEVEL) 1
#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
