Change SDC to base and make self contained

def/user_project_wrapper.def

diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index a4b95d1..1b490a5 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
Binary files differ

openlane/user_project_wrapper/base.sdc

diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
new file mode 100644
index 0000000..f3f6f89
--- /dev/null
+++ b/openlane/user_project_wrapper/base.sdc
@@ -0,0 +1,37 @@
+## Clock configurations
+set ::env(CLOCK_PORT) {io_in\[17\]}
+set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
+set ::env(RESET_PORT) {io_in\[15\] wb_rst_i}
+
+set ::env(CLOCK_PERIOD) "30"
+set ::env(IO_PCT) 0.2
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) 17.65
+
+create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+set rst_indx [lsearch [all_inputs] [get_port $::env(RESET_PORT)]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+#set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+
+# correct resetn
+set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)]
+set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 7e55970..c045adc 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -33,10 +33,10 @@
 ## Clock configurations
 set ::env(CLOCK_PORT) {io_in\[17\]}
 set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
-set ::env(RESET_PORT) {io_in\[15\] wb_rst_i}
+set ::env(RESET_PORT) {io_in\[15\] wb_rst_i
 
 set ::env(CLOCK_PERIOD) "30"
-set ::env(BASE_SDC_FILE) "$script_dir/user_project_wrapper.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
 ## Internal Macros
 ### Macro Placement