made the clock select multiplexer compatible to take more than two input sources for future wishbone clock
diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index e94f754..d263a89 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -53,6 +53,7 @@
assign mprj_io[15] = 1'b1; // reset
assign mprj_io[16] = 1'b1; // in_select
+ assign mprj_io[23] = 1'b0; // in_select
assign mprj_io[17] = gpio_clk;
assign mprj_io[18] = gpio_in;
assign mprj_io[19] = gpio_scan;
diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index 19402d9..f71d7c3 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -58,7 +58,9 @@
wire gpio_out = mprj_io[22];
assign mprj_io[15] = 1'b1; // resetn
- assign mprj_io[16] = 1'b0; // in_select
+ // assigning `b00 to pin 16 and 23 enables the clock from la
+ assign mprj_io[16] = 1'b0; // in_select[0]
+ assign mprj_io[23] = 1'b0; // in_select[1]
assign mprj_io[17] = gpio_clk;
assign mprj_io[18] = gpio_in;
assign mprj_io[19] = gpio_scan;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 58b9127..22a8315 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -95,7 +95,7 @@
wire [`MAX_CHIPS-1:0] csb0;
wire [`MAX_CHIPS-1:0] csb1;
- wire in_select = io_in[16];
+ wire [1:0] in_select = {io_in[23],io_in[16]};
wire gpio_resetn = io_in[15];
wire gpio_clk = io_in[17];
wire gpio_scan = io_in[19];
@@ -118,7 +118,12 @@
// Selecting clock pin
reg clk;
always @(*) begin
- clk = in_select ? gpio_clk : la_clk;
+ case (in_select)
+ 2'b00 : clk = la_clk;
+ 2'b01 : clk = gpio_clk;
+ default : clk = 0;
+ endcase
+ //clk = in_select ? gpio_clk : la_clk;
end
// global csb is low with either GPIO or LA csb
