corrected a comment

verilog/rtl/wishbone_ram_mux.v

diff --git a/verilog/rtl/wishbone_ram_mux.v b/verilog/rtl/wishbone_ram_mux.v
index df15428..6421992 100644
--- a/verilog/rtl/wishbone_ram_mux.v
+++ b/verilog/rtl/wishbone_ram_mux.v
@@ -70,7 +70,7 @@
 assign wbs_or9_sel_o = wbs_ufp_sel_i & {4{sram9_select}};
 assign wbs_or9_dat_o = wbs_ufp_dat_i & {32{sram9_select}};
 
-// HyperRAM or OpenRAM -> UFP
+// SRAM8 or SRAM9 -> UFP
 assign wbs_ufp_ack_o = (wbs_or8_ack_i & sram8_select) | (wbs_or9_ack_i & sram9_select);
 assign wbs_ufp_dat_o = (wbs_or8_dat_i & {32{sram8_select}}) | (wbs_or9_dat_i & {32{sram9_select}});