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foss-eda-tools/third_party/shuttle/sky130/mpw-003/slot-015/5e4df0dfda5fa6c50cbf1ec601d6ce3ca5bf8a4d^2..5e4df0dfda5fa6c50cbf1ec601d6ce3ca5bf8a4d/.
commit
5e4df0dfda5fa6c50cbf1ec601d6ce3ca5bf8a4d
[log] [tgz]
author
hadirkhan10 <hadirkhan10@gmail.com>
Fri Dec 17 20:57:36 2021 -0800
committer
hadirkhan10 <hadirkhan10@gmail.com>
Fri Dec 17 20:57:36 2021 -0800
tree
d5938e7904964c375b16c8dd0e4b216c67752568
parent
14ef1c5901ca745d354cb6edfeafe00a2b5f6434 [diff]
parent
ce65f0064ab72841112285bce9212c6673d290ce [diff]
resolved the merge conflicts and made the la_test working again

diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index 41e6b76..db532ef 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c

@@ -18,7 +18,6 @@
 // This include is relative to $CARAVEL_PATH (see Makefile)
 #include "verilog/dv/caravel/defs.h"
 #include "verilog/dv/caravel/stub.c"
-
 /*
 	LA Test:
 		- Reads to and writes from each SRAM
@@ -124,7 +123,6 @@
 	// Toggle clock to store into dout FF
 	reg_la3_data = 0x00000000 | sel << 12;
 	reg_la3_data = 0x80000000 | sel << 12;
-
 	// Toggle clock to replace din with dout
 	reg_la3_data = 0x10000000 | sel << 12;
 	reg_la3_data = 0x90000000 | sel << 12;
@@ -213,33 +211,32 @@
                                         // connect to housekeeping SPI
 
 	// This is to signal when the code is ready to the test bench
-	reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
-	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
-
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ 
 	/* Apply configuration */
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
-
-	// To start, set pin 0 to 1
-	reg_mprj_datal = 0x00000001;
-
+	
+	// To start, set pin 28 to 1
+	reg_mprj_datal = 0x10000000;
 	/* DUAL PORT MEMORIES */
 
 	//SRAM 0
 	write_dp_sram(0);
 	read_dp_sram(0);
 
-	//SRAM 1
-	write_dp_sram(1);
-	read_dp_sram(1);
+        //SRAM 1
+        write_dp_sram(1);
+        read_dp_sram(1);
 
 	// SRAM 2
 	write_dp_sram(2);
@@ -249,7 +246,7 @@
 	write_dp_sram(3);
 	read_dp_sram(3);
 
-	// SRAM 4
+        // SRAM 4
 	write_dp_sram(4);
 	read_dp_sram(4);
 
@@ -271,6 +268,6 @@
 	write_sp_sram(11);
 	read_sp_sram(11);
 
-	// On end, set pin 0 to 0
+	// On end, set pin 8 to 0
 	reg_mprj_datal = 0x00000000;
 }

diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index e34f8aa..19402d9 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v

@@ -30,16 +30,16 @@
 
 	wire gpio;
 	wire [37:0] mprj_io;
-	wire mprj_io_0 = mprj_io[0];
-	wire mprj_io_1 = mprj_io[1];
-	wire mprj_io_2 = mprj_io[2];
-	wire mprj_io_3 = mprj_io[3];
-	wire mprj_io_4 = mprj_io[4];
-	wire mprj_io_5 = mprj_io[5];
-	wire mprj_io_6 = mprj_io[6];
-	wire mprj_io_7 = mprj_io[7];
-	wire mprj_io_8 = mprj_io[8];
-	wire mprj_io_9 = mprj_io[9];
+	wire mprj_io_28 = mprj_io[28];
+	wire mprj_io_29 = mprj_io[29];
+	wire mprj_io_30 = mprj_io[30];
+	wire mprj_io_31 = mprj_io[31];
+	wire mprj_io_32 = mprj_io[32];
+	wire mprj_io_33 = mprj_io[33];
+	wire mprj_io_34 = mprj_io[34];
+	wire mprj_io_35 = mprj_io[35];
+	wire mprj_io_36 = mprj_io[36];
+	wire mprj_io_37 = mprj_io[37];
 
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
@@ -50,7 +50,6 @@
 	initial begin
 		clock = 0;
 	end
-
 	wire gpio_clk = 1'b1;
 	wire gpio_scan = 1'b0;
 	wire gpio_sram_load = 1'b0;
@@ -65,75 +64,72 @@
 	assign mprj_io[19] = gpio_scan;
 	assign mprj_io[20] = gpio_sram_load;
 	assign mprj_io[21] = global_csb;
-
 	initial begin
 
-		wait(mprj_io_0 == 1'b1);
+		wait(mprj_io_28 == 1'b1);
 		$display($time, " Saw bit 1: VCD starting");
 
 		$dumpfile("la_test.vcd");
 		$dumpvars(0, la_test_tb);
 
-		wait(mprj_io_0 == 1'b0);
+		wait(mprj_io_28 == 1'b0);
 		$display($time, " Saw bit 0: VCD stopping");
 		$display("Done with tests");
 		$finish;
 
 	end // initial begin
+	
+	initial begin
+		wait (mprj_io_29 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 0!"); 
+	end
+	
+	initial begin
+		wait (mprj_io_30 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 1!"); 
+	end
+		
+	initial begin 
+		wait (mprj_io_31 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 2!"); 
+	end
 
-	// initial begin
-	// 	wait (mprj_io_1 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 0!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_32 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 3!"); 
+	end
 
-	// initial begin
-	// 	wait (mprj_io_2 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 1!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_33 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 4!"); 
+	end
 
-	// initial begin
-	// 	wait (mprj_io_3 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 2!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_34 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 8!"); 
+	end
 
-	// initial begin
-	// 	wait (mprj_io_4 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 3!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_35 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 9!"); 
+	end
 
-	// initial begin
-	// 	wait (mprj_io_5 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 4!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_36 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 10!");
+	end
 
-	// initial begin
-	// 	wait (mprj_io_6 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 8!"); $finish;
-	// end
+	initial begin
+		wait (mprj_io_37 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 11!");
+	end
 
-	// initial begin
-	// 	wait (mprj_io_7 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 9!"); $finish;
-	// end
+   initial begin
+      #5000000
+      $display("Timeout");
+      $finish;
+   end
 
-	// initial begin
-	// 	wait (mprj_io_8 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 10!"); $finish;
-	// end
-
-	// initial begin
-	// 	wait (mprj_io_9 == 1'b1);
-	// 	$display($time, " Data mismatch while reading byte from SRAM 11!"); $finish;
-	// end
-
-   // initial begin
-   //    //$dumpfile("foo.vcd");
-   //    //$dumpvars(0, la_test_tb);
-
-   //    #5000000
-   //    $display("Timeout");
-   //    $finish;
-   // end