commit 537b0d03137badb81c895e997539fa9fdac14da9
author mrg <mrg@ucsc.edu> Tue Nov 09 09:03:53 2021 -0800
committer mrg <mrg@ucsc.edu> Tue Nov 09 09:03:53 2021 -0800
tree 75864a2bd1b671756be6dce7bc4591f8f80f6d9c
parent 0a4a2e22f83289b38806849657c74afb7c03c653

Remove input path constraints and report clock skew

openlane/user_project_wrapper/base.sdc

diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index 40e90a2..a9b5d79 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -4,11 +4,12 @@
 set ::env(RESET_PORT) {io_in[15] wb_rst_i}
 
 set ::env(CLOCK_PERIOD) "30"
+
 set ::env(IO_PCT) 0.2
-set ::env(SYNTH_MAX_FANOUT) 5
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) 17.65
+set ::env(SYNTH_CAP_LOAD) "33.5"
+set ::env(SYNTH_MAX_FANOUT) "4"
 
 create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
 set_propagated_clock [get_ports $::env(CLOCK_PORT)]
@@ -28,8 +29,8 @@
 
 
 # correct resetn
-set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
-set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)]
+#set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)]
 set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
 
 # TODO set this as parameter
@@ -37,3 +38,5 @@
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
+
+report_clock_skew
\ No newline at end of file

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f648f57..647c895 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -31,9 +31,9 @@
 	$script_dir/../../verilog/rtl/user_project_wrapper.v "
 
 ## Clock configurations
-set ::env(CLOCK_PORT) {io_in\[17\]}
+set ::env(CLOCK_PORT) {io_in[17]}
 set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
-set ::env(RESET_PORT) {io_in\[15\] wb_rst_i}
+set ::env(RESET_PORT) {io_in[15] wb_rst_i}
 
 set ::env(CLOCK_PERIOD) "30"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"