commit 4dfef12259a8f1d4895adb5e114b4d9e3c18a910
author mrg <mrg@ucsc.edu> Tue Nov 09 16:08:14 2021 -0800
committer mrg <mrg@ucsc.edu> Tue Nov 09 16:08:14 2021 -0800
tree 39561ce88e202b2047a1a522cbb2942b82e47af9
parent 47c4dee655fdaa5d564c0f019976f228f0664279

Config needs escaped brackets

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 26dea6d..0624fbe 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -37,9 +37,9 @@
 	$script_dir/../../verilog/rtl/testchip/openram_testchip.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) {io_in[17]}
+set ::env(CLOCK_PORT) {io_in\[17\]}
 set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
-set ::env(RESET_PORT) {io_in[15] wb_rst_i}
+set ::env(RESET_PORT) {io_in\[15\] wb_rst_i}
 
 set ::env(CLOCK_PERIOD) "30"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"