| commit | 5fafe4cf6eb7619b809cfa56d1a047f301f5b2ad | [log] [tgz] |
|---|---|---|
| author | ssprasad <ssprasad12a@gmail.com> | Fri Oct 29 00:19:06 2021 +0530 |
| committer | ssprasad <ssprasad12a@gmail.com> | Fri Oct 29 00:19:06 2021 +0530 |
| tree | efba78a78066879d69a6bb6e43cb4199b8ba203a | |
| parent | ac1c8ef47a275b4bca13d8fc2d6b82b73c0ee59d [diff] |
Changed readme
Refer to README for this sample project documentation. This Project integrates various IP‘s like I2C, I2S, SPI ,QSPI, PWM, GPIO, UART, JTAG to the caravel SoC. The IP’s connect to the Caravel Wishbone Bus and use the User Adddessable space from address 0x3000_0000.