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foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-013 / HEAD
  1. 6c02c21 final gds oasis by Jeff DiCorpo · 3 years ago main
  2. c69c77e uart master interface added by dineshannayya · 3 years ago
  3. cb2d94c block diagram and doc update by dineshannayya · 3 years ago
  4. aa9f18a MPW-4 submission with 8KB WishBone and 4KB TCM Memory by dineshannayya · 3 years ago
  5. 24e8606 add new caravel by dineshannayya · 3 years ago
  6. 1bf4c82 removed older version of caravel by dineshannayya · 3 years ago
  7. 98c936d met5 density fix by dineshannayya · 3 years ago
  8. 9f5fede metal denisty fix for met5 by dineshannayya · 3 years ago
  9. 6841a57 pdn drc fix by dineshannayya · 3 years ago
  10. f6bd64e timing clean, syntacore gds link fix, 8KB SRAM added by dineshannayya · 3 years ago
  11. 4222ec0 area clean up by dineshannayya · 3 years, 1 month ago
  12. a26a0ad docker images hardcoded and pdk path local docker path/opt/pdk by dineshannayya · 3 years, 1 month ago
  13. 6f545ba full chip sta folder created by dineshannayya · 3 years, 1 month ago
  14. e379668 Timing clean-up + Signature Register Added in PinMux by dineshannayya · 3 years, 1 month ago
  15. 62e7538 wb host output timing fix by dineshannayya · 3 years, 1 month ago
  16. 968530f syntacore ip area reduction by dineshannayya · 3 years, 1 month ago
  17. a8decc7 IP area optimization by dineshannayya · 3 years, 1 month ago
  18. 2bbc152 wb_host regenerated by dineshannayya · 3 years, 1 month ago
  19. 02d4392 clk_ctl bug fix in wb_host by dineshannayya · 3 years, 1 month ago
  20. 8599270 wbhost reset bug fix and clocking cleanup by dineshannayya · 3 years, 1 month ago
  21. 17b4ecc typical timing closed tape-in database by dineshannayya · 3 years, 1 month ago
  22. bfb3be0 Adding clock skew inside the subIO + Precheck cleanup by dineshannayya · 3 years, 1 month ago
  23. aef8802 temporary deleting of riscv complaint submodule to pass the efabless precheck by dineshannayya · 3 years, 2 months ago
  24. 299e1c1 golden git module update by dineshannayya · 3 years, 2 months ago
  25. 6585fcb sram blockage for magic drc fix by dineshannayya · 3 years, 2 months ago
  26. 7b99b86 directory clean up by dineshannayya · 3 years, 2 months ago
  27. 5c55998 Rebase on caravel by dineshannayya · 3 years, 2 months ago
  28. b37c581 caraval rebase to mpw-3 tag by dineshannayya · 3 years, 2 months ago
  29. b174af6 removed caravel by dineshannayya · 3 years, 2 months ago
  30. a66e9ef rebase the caravel project by dineshannayya · 3 years, 2 months ago
  31. 453bb7f rebase caravel by dineshannayya · 3 years, 2 months ago
  32. 05393e8 Basic Verification and Physical design cleanup by dineshannayya · 3 years, 2 months ago
  33. 1bbdb71 Block digram update by dineshannayya · 3 years, 3 months ago
  34. 71e8b5a Document and Floor planning image update by dineshannayya · 3 years, 3 months ago
  35. cff2094 caravel update by dineshannayya · 3 years, 3 months ago
  36. aacc9b7 caravel repo added by dineshannayya · 3 years, 3 months ago
  37. 64fec54 Removed older version of caravel by dineshannayya · 3 years, 3 months ago
  38. 665a2af drc clean project ver1.0 by dineshannayya · 3 years, 3 months ago
  39. 6d8d774 test bench clean-up by dineshannayya · 3 years, 3 months ago
  40. 39fb862 first version of riscduino with sdram removed, pinmux and sar_adc added by dineshannayya · 3 years, 3 months ago
  41. fb75213 git module by dineshannayya · 3 years, 3 months ago
  42. 2528024 caravel lite by dineshannayya · 3 years, 3 months ago
  43. cdf8fb5 comit gitmodule by dineshannayya · 3 years, 3 months ago
  44. ef10901 doc update by dineshannayya · 3 years, 3 months ago
  45. 65b54cf documentation update by dineshannayya · 3 years, 3 months ago
  46. 8ff9600 MPW-3 caravel link updated by dineshannayya · 3 years, 3 months ago
  47. 4e66c95 Readme and caravel link deleted by dineshannayya · 3 years, 3 months ago
  48. a752b44 riscv regression with coremark test passing by dineshannayya · 3 years, 4 months ago
  49. be01ead sdram ctrl bug fix tRAS violation, changed the define to ASIC by dineshannayya · 3 years, 4 months ago
  50. 0081f48 timer_irq connectivity bug fix by dineshannayya · 3 years, 4 months ago
  51. 66179f7 riscv_regress simulation works through docker by dineshannayya · 3 years, 4 months ago
  52. f83393a riscv regression suite, riscv_isa and riscv_compliance test integrated by dineshannayya · 3 years, 4 months ago
  53. d134e4f Riscv Unalign access fix and sdr ctrl 8 bit address mode fix by dineshannayya · 3 years, 4 months ago
  54. 26743b2 modelsim compile cleanup by dineshannayya · 3 years, 4 months ago
  55. 337d9f8 synta core cleanup by dineshannayya · 3 years, 4 months ago
  56. 2223fbd pdk file are copied /opt/pdk inside the docker by dineshannayya · 3 years, 4 months ago
  57. 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 4 months ago
  58. c6a2a5d antenna fix by dineshannayya · 3 years, 5 months ago
  59. c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 3 years, 5 months ago
  60. c3362ee efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 5 months ago
  61. c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 5 months ago
  62. 47e853b block diagram updated by dineshannayya · 3 years, 5 months ago
  63. fbc351b SPDX Non compliant text fix by dineshannayya · 3 years, 5 months ago
  64. 3ae1a2b usb1 host is integrated by dineshannayya · 3 years, 5 months ago
  65. 1bfec4f Register Map detail updated by dineshannayya · 3 years, 5 months ago
  66. 8adb7e4 Register Map updated in Readme by dineshannayya · 3 years, 5 months ago
  67. 9daed32 README updated with i2c info by dineshannayya · 3 years, 5 months ago
  68. 4a4e2b8 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 3 years, 5 months ago
  69. 4f74e2f i2cm integrated and share same uart io by dineshannayya · 3 years, 5 months ago
  70. 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 5 months ago
  71. 9fdcbca syntacore timing fix by dineshannayya · 3 years, 5 months ago
  72. 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 3 years, 5 months ago
  73. 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years, 5 months ago
  74. 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 5 months ago
  75. a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years, 5 months ago
  76. 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 5 months ago
  77. 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 6 months ago
  78. 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years, 6 months ago
  79. daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 3 years, 6 months ago
  80. 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years, 6 months ago
  81. ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 6 months ago
  82. 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 6 months ago
  83. dcf9534 first version of pre-check clean database by dineshannayya · 3 years, 6 months ago
  84. a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years, 6 months ago
  85. 311a4e0 precheck cleanup by dineshannayya · 3 years, 6 months ago
  86. c184ad2 License Text Added by dineshannayya · 3 years, 6 months ago
  87. 76d58fb DRC clean user_project_wrapper by dineshannayya · 3 years, 6 months ago
  88. a908000 updated database by dineshannayya · 3 years, 6 months ago
  89. 81d24ed wb_host rtl and openlane setup added by dineshannayya · 3 years, 6 months ago
  90. feb1877 backand cleanup by dineshannayya · 3 years, 6 months ago
  91. 9112eeb user project def,lef,gds added by dineshannayya · 3 years, 6 months ago
  92. ed94965 database update by dineshannayya · 3 years, 6 months ago
  93. 3f698f9 script update by dineshannayya · 3 years, 6 months ago
  94. 1431d7b def,gds,lef addition by dineshannayya · 3 years, 6 months ago
  95. e08e2a5 uart test case integration by dineshannayya · 3 years, 6 months ago
  96. b547314 uart test case integration by dineshannayya · 3 years, 6 months ago
  97. 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 3 years, 6 months ago
  98. 35b181f Merge branch 'master' of https://github.com/dineshannayya/yifive_r0 by DESKTOP-QFPBD39\dinesha · 3 years, 6 months ago
  99. ea1e6f3 floor planning cleanup by dineshannayya · 3 years, 6 months ago
  100. a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 3 years, 6 months ago