Log - HEAD - third_party/shuttle/sky130/mpw-003/slot-013

6c02c21 final gds oasis by Jeff DiCorpo · 4 years, 10 months ago main

c69c77e uart master interface added by dineshannayya · 4 years, 10 months ago

cb2d94c block diagram and doc update by dineshannayya · 4 years, 10 months ago

aa9f18a MPW-4 submission with 8KB WishBone and 4KB TCM Memory by dineshannayya · 4 years, 10 months ago

24e8606 add new caravel by dineshannayya · 4 years, 10 months ago

1bf4c82 removed older version of caravel by dineshannayya · 4 years, 10 months ago

98c936d met5 density fix by dineshannayya · 4 years, 11 months ago

9f5fede metal denisty fix for met5 by dineshannayya · 4 years, 11 months ago

6841a57 pdn drc fix by dineshannayya · 4 years, 11 months ago

f6bd64e timing clean, syntacore gds link fix, 8KB SRAM added by dineshannayya · 4 years, 11 months ago

4222ec0 area clean up by dineshannayya · 5 years ago

a26a0ad docker images hardcoded and pdk path local docker path/opt/pdk by dineshannayya · 5 years ago

6f545ba full chip sta folder created by dineshannayya · 5 years ago

e379668 Timing clean-up + Signature Register Added in PinMux by dineshannayya · 5 years ago

62e7538 wb host output timing fix by dineshannayya · 5 years ago

968530f syntacore ip area reduction by dineshannayya · 5 years ago

a8decc7 IP area optimization by dineshannayya · 5 years ago

2bbc152 wb_host regenerated by dineshannayya · 5 years ago

02d4392 clk_ctl bug fix in wb_host by dineshannayya · 5 years ago

8599270 wbhost reset bug fix and clocking cleanup by dineshannayya · 5 years ago

17b4ecc typical timing closed tape-in database by dineshannayya · 5 years ago

bfb3be0 Adding clock skew inside the subIO + Precheck cleanup by dineshannayya · 5 years ago

aef8802 temporary deleting of riscv complaint submodule to pass the efabless precheck by dineshannayya · 5 years ago

299e1c1 golden git module update by dineshannayya · 5 years ago

6585fcb sram blockage for magic drc fix by dineshannayya · 5 years ago

7b99b86 directory clean up by dineshannayya · 5 years ago

5c55998 Rebase on caravel by dineshannayya · 5 years ago

b37c581 caraval rebase to mpw-3 tag by dineshannayya · 5 years ago

b174af6 removed caravel by dineshannayya · 5 years ago

a66e9ef rebase the caravel project by dineshannayya · 5 years ago

453bb7f rebase caravel by dineshannayya · 5 years ago

05393e8 Basic Verification and Physical design cleanup by dineshannayya · 5 years ago

1bbdb71 Block digram update by dineshannayya · 5 years ago

71e8b5a Document and Floor planning image update by dineshannayya · 5 years ago

cff2094 caravel update by dineshannayya · 5 years ago

aacc9b7 caravel repo added by dineshannayya · 5 years ago

64fec54 Removed older version of caravel by dineshannayya · 5 years ago

665a2af drc clean project ver1.0 by dineshannayya · 5 years ago

6d8d774 test bench clean-up by dineshannayya · 5 years ago

39fb862 first version of riscduino with sdram removed, pinmux and sar_adc added by dineshannayya · 5 years ago

fb75213 git module by dineshannayya · 5 years ago

2528024 caravel lite by dineshannayya · 5 years ago

cdf8fb5 comit gitmodule by dineshannayya · 5 years ago

ef10901 doc update by dineshannayya · 5 years ago

65b54cf documentation update by dineshannayya · 5 years ago

8ff9600 MPW-3 caravel link updated by dineshannayya · 5 years ago

4e66c95 Readme and caravel link deleted by dineshannayya · 5 years ago

a752b44 riscv regression with coremark test passing by dineshannayya · 5 years ago

be01ead sdram ctrl bug fix tRAS violation, changed the define to ASIC by dineshannayya · 5 years ago

0081f48 timer_irq connectivity bug fix by dineshannayya · 5 years ago

66179f7 riscv_regress simulation works through docker by dineshannayya · 5 years ago

f83393a riscv regression suite, riscv_isa and riscv_compliance test integrated by dineshannayya · 5 years ago

d134e4f Riscv Unalign access fix and sdr ctrl 8 bit address mode fix by dineshannayya · 5 years ago

26743b2 modelsim compile cleanup by dineshannayya · 5 years ago

337d9f8 synta core cleanup by dineshannayya · 5 years ago

2223fbd pdk file are copied /opt/pdk inside the docker by dineshannayya · 5 years ago

5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 5 years ago

c6a2a5d antenna fix by dineshannayya · 5 years ago

c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 5 years ago

c3362ee efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago

c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago

47e853b block diagram updated by dineshannayya · 5 years ago

fbc351b SPDX Non compliant text fix by dineshannayya · 5 years ago

3ae1a2b usb1 host is integrated by dineshannayya · 5 years ago

1bfec4f Register Map detail updated by dineshannayya · 5 years ago

8adb7e4 Register Map updated in Readme by dineshannayya · 5 years ago

9daed32 README updated with i2c info by dineshannayya · 5 years ago

4a4e2b8 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 5 years ago

4f74e2f i2cm integrated and share same uart io by dineshannayya · 5 years ago

80d1ad8 spi master with qddr mode support added by dineshannayya · 5 years ago

9fdcbca syntacore timing fix by dineshannayya · 5 years ago

77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 5 years ago

8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 5 years ago

9242ac2 SPI Preftech logic added by dineshannayya · 5 years ago

a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 5 years ago

93bc315 clk_skew power hook fix by dineshannayya · 5 years ago

14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 5 years ago

5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 5 years ago

daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 5 years ago

4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 5 years ago

ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 5 years ago

63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 5 years ago

dcf9534 first version of pre-check clean database by dineshannayya · 5 years ago

a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 5 years ago

311a4e0 precheck cleanup by dineshannayya · 5 years ago

c184ad2 License Text Added by dineshannayya · 5 years ago

76d58fb DRC clean user_project_wrapper by dineshannayya · 5 years ago

a908000 updated database by dineshannayya · 5 years ago

81d24ed wb_host rtl and openlane setup added by dineshannayya · 5 years ago

feb1877 backand cleanup by dineshannayya · 5 years ago

9112eeb user project def,lef,gds added by dineshannayya · 5 years ago

ed94965 database update by dineshannayya · 5 years ago

3f698f9 script update by dineshannayya · 5 years ago

1431d7b def,gds,lef addition by dineshannayya · 5 years ago

e08e2a5 uart test case integration by dineshannayya · 5 years ago

b547314 uart test case integration by dineshannayya · 5 years ago

46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 5 years ago

35b181f Merge branch 'master' of https://github.com/dineshannayya/yifive_r0 by DESKTOP-QFPBD39\dinesha · 5 years ago

ea1e6f3 floor planning cleanup by dineshannayya · 5 years ago

a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 5 years ago