uart test case integration
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index c2ec988..77ade33 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m29s,0h4m0s,58333.33333333334,0.09,29166.66666666667,48,595.32,2625,0,0,0,0,0,0,0,9,0,0,0,112279,21278,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,81244573,0.0,28.2,24.76,3.22,-1,-1,2478,2670,463,655,0,0,0,2625,1,0,3,1,468,0,0,560,577,533,10,212,1078,10,1300,100.0,10.0,10,AREA 0,5,50,1,80,10.8,0.9,0,sky130_fd_sc_hd,0,3
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h54m51s,0h36m45s,47033.33333333334,0.12,23516.66666666667,42,521.1,2822,0,0,0,0,0,0,0,5,0,0,0,152285,24010,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,116244427,0.0,47.37,33.22,6.24,0.64,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,204,1404,0,1608,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 3fff53d..4fdf5fa 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h7m32s,0h4m3s,43333.333333333336,0.3,21666.666666666668,30,603.28,6500,0,0,0,0,0,0,0,43,0,0,0,362096,48694,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,313618208,0.0,40.99,11.75,11.06,0.0,-1,6475,6645,1150,1320,0,0,0,6500,130,107,82,102,354,211,31,2197,1190,1123,28,204,3638,0,3842,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m5s,0h4m14s,48162.962962962956,0.27,24081.481481481478,39,623.69,6502,0,0,0,0,0,0,0,6,0,0,0,365524,56020,-0.56,-0.56,-0.72,-0.72,-0.78,-16.15,-16.15,-136.64,-136.64,-161.07,297911924,0.0,53.29,21.57,24.67,0.05,-1,6477,6647,1150,1320,0,0,0,6502,131,107,82,107,352,213,29,2197,1190,1123,28,204,3274,0,3478,92.7643784786642,10.78,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 7325d8c..ed09f26 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m4s,0h4m20s,19293.333333333336,0.3,9646.666666666668,15,567.92,2894,0,0,0,0,0,0,1,5,1,0,0,150790,24828,-1.25,-1.25,-1.79,-1.79,-2.3,-107.03,-107.03,-394.49,-394.49,-544.26,121832965,0.0,12.02,8.74,0.89,0.0,-1,2872,2970,449,547,0,0,0,2894,85,0,95,81,1125,90,20,923,529,465,27,358,3708,13,4079,81.30081300813008,12.3,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,0,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m32s,0h4m29s,20520.0,0.3,10260.0,18,567.37,3078,0,0,0,0,0,0,0,0,0,0,0,173426,28976,-3.48,-3.48,-4.43,-4.43,-5.17,-122.15,-122.15,-1136.48,-1136.48,-1380.14,132659104,0.0,20.89,14.82,5.05,0.13,-1,3056,3154,447,545,0,0,0,3078,85,0,94,81,1122,89,19,921,527,463,28,350,3628,0,3978,65.91957811470007,15.17,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index c99599e..190648b 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h35m28s,0h27m5s,29668.888888888887,1.8,14834.444444444443,20,1125.28,26702,0,0,0,0,0,0,0,69,0,0,0,1591280,222490,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1348931410,0.0,19.87,15.65,3.42,0.14,-1,26588,26826,2335,2573,0,0,0,26702,508,0,693,1900,3881,2188,1037,6599,2386,2349,100,866,22835,255,23956,20.0,50.0,50,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h33m4s,1h2m48s,34500.0,1.8,17250.0,26,1273.99,31050,0,0,0,0,0,0,0,11,0,403,0,1857830,282475,-11.66,-11.66,-11.09,-11.09,-12.36,-10251.82,-10251.82,-6187.35,-6187.35,-7506.05,1508810185,0.0,35.33,24.08,13.41,3.08,-1,30938,31176,2811,3049,0,0,0,31050,619,0,692,2059,4036,2095,1327,7438,2842,2789,96,866,22835,0,23701,44.72271914132379,22.36,10,AREA 0,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 7b324d7..c03cd8f 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h5m21s,0h3m7s,7321.739130434781,0.23,3660.8695652173906,4,510.27,842,0,0,0,0,0,0,0,14,0,0,0,399186,10637,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,371301320,0.0,48.62,5.88,23.46,-1,-1,583,1159,59,635,0,0,0,842,146,0,3,75,33,0,0,107,318,318,14,64,2750,195,3009,100.0,10.0,10,AREA 0,5,50,1,80,10.8,0.9,0,sky130_fd_sc_hd,0,3
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m26s,0h2m49s,6888.8888888888905,0.36,3444.4444444444453,6,511.24,1240,0,0,0,0,0,0,0,22,0,0,0,496524,14916,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,454520392,0.0,52.93,9.22,42.06,0.0,-1,1005,1557,201,753,0,0,0,1240,247,0,75,5,69,0,0,181,426,402,10,94,4159,0,4253,100.0,10.0,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot.hex b/verilog/dv/risc_boot/risc_boot.hex
deleted file mode 100755
index 3a5d43e..0000000
--- a/verilog/dv/risc_boot/risc_boot.hex
+++ /dev/null
@@ -1,125 +0,0 @@
-@00000000
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-87 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-07 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-C7 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-87 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 06 09 67 13 07 97 80 98 C3 B7 07 00 26 05 47
-98 C3 01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE
-01 00 72 44 05 61 82 80
diff --git a/verilog/dv/risc_boot/run_iverilog b/verilog/dv/risc_boot/run_iverilog
index 65f8bd5..a75e2ff 100755
--- a/verilog/dv/risc_boot/run_iverilog
+++ b/verilog/dv/risc_boot/run_iverilog
@@ -2,7 +2,7 @@
#add -DWFDUMP to enable waveform dump
iverilog -DWFDUMP -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
-I $CARAVEL_ROOT/verilog/dv/caravel -I $CARAVEL_ROOT/verilog/rtl \
--I ../model -I ../../../verilog/rtl \
+-I ../model -I ../agents -I ../../../verilog/rtl \
-I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs \
risc_boot_tb.v -o risc_boot.vvp
diff --git a/verilog/dv/risc_boot/user_risc_boot.hex b/verilog/dv/risc_boot/user_risc_boot.hex
deleted file mode 100755
index 5ab43fa..0000000
--- a/verilog/dv/risc_boot/user_risc_boot.hex
+++ /dev/null
@@ -1,79 +0,0 @@
-@00000000
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 13 00 00 00 6F 00 00 00 FF FF FF FF
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-6F 00 E0 18 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
-93 00 00 00 13 01 00 00 93 01 00 00 13 02 00 00
-93 02 00 00 13 03 00 00 93 03 00 00 13 04 00 00
-93 04 00 00 13 05 00 00 93 05 00 00 13 06 00 00
-93 06 00 00 13 07 00 00 93 07 00 00 13 08 00 00
-93 08 00 00 13 09 00 00 93 09 00 00 13 0A 00 00
-93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00
-93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00
-93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 00 20
-93 81 41 62 13 05 00 40 97 05 00 20 93 85 85 D7
-17 06 00 20 13 06 06 E3 63 0D B5 00 29 A0 14 41
-94 C1 11 05 91 05 E3 9C C5 FE 17 06 00 20 13 06
-66 E1 97 05 00 20 93 85 E5 E0 21 A0 23 20 06 00
-11 06 E3 9D C5 FE 17 01 01 20 13 01 A1 D3 17 05
-00 20 13 05 25 DF 17 06 00 20 13 06 A6 DE B3 05
-A6 40 17 07 01 20 13 07 E7 91 33 02 B7 40 92 85
-17 06 00 20 13 06 06 DD 29 A0 14 41 94 C1 11 05
-91 05 E3 1C C5 FE 21 A0 23 A0 05 00 91 05 E3 9D
-E5 FE B7 02 49 00 05 43 23 A0 62 00 B7 02 49 00
-91 02 13 03 30 06 23 A0 62 00 B7 02 49 00 C1 02
-7D 53 23 A0 62 00 23 A2 62 00 01 45 81 45 97 02
-00 20 E7 80 22 CC 97 02 00 20 93 82 A2 D1 6D 71
-06 C2 0A C4 0E C6 12 C8 16 CA 1A CC 1E CE 22 D0
-26 D2 2A D4 2E D6 32 D8 36 DA 3A DC 3E DE C2 C0
-C6 C2 CA C4 CE C6 D2 C8 D6 CA DA CC DE CE E2 D0
-E6 D2 EA D4 EE D6 F2 D8 F6 DA FA DC FE DE 73 25
-20 34 F3 25 10 34 0A 86 EF 00 80 04 92 40 22 41
-B2 41 42 42 D2 42 62 43 F2 43 02 54 92 54 22 55
-B2 55 42 56 D2 56 62 57 F2 57 06 48 96 48 26 49
-B6 49 46 4A D6 4A 66 4B F6 4B 06 5C 96 5C 26 5D
-B6 5D 46 5E D6 5E 66 5F F6 5F 51 61 73 00 20 30
-6F F0 5F D1 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-@00000400
-37 37 22 11 B7 07 00 30 93 02 47 34 37 43 33 22
-23 AC 57 00 93 03 53 45 37 55 44 33 23 AE 77 00
-93 05 65 56 37 66 55 44 8C D3 93 06 76 67 37 78
-66 55 D4 D3 93 08 88 78 37 9E 77 66 23 A4 17 03
-93 0E 9E 89 23 A6 D7 03 01 A0 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-97 02 00 E0 93 82 42 09 82 82 13 00 00 00 13 00
-00 00 13 00 00 00 13 00 00 00 13 00 00 00 01 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-@000004A0
-13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
