Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1)

commit: a8d65905df44b70353b42900296c3fb8b5a7b47d [log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com> Mon Jul 12 22:56:32 2021 +0530
committer: dineshannayya <dinesh.annayya@gmail.com> Mon Jul 12 22:56:32 2021 +0530
tree: dfef0df91bbc6f97cf380070ef88d90dbed8a166
parent: 93bc3159c67b218ea426ba0d9f425ab4ce8ea0b6 [diff]
diff --git a/checks/erase_box_user_project_wrapper.gds.log b/checks/erase_box_user_project_wrapper.gds.log
index f1b10a8..e833e84 100644
--- a/checks/erase_box_user_project_wrapper.gds.log
+++ b/checks/erase_box_user_project_wrapper.gds.log

@@ -21,41 +21,41 @@
 Reading "sky130_fd_sc_hd__decap_6".
 Reading "sky130_fd_sc_hd__decap_12".
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__decap_4".
-Reading "sky130_fd_sc_hd__o22a_4".
 Reading "sky130_fd_sc_hd__fill_1".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__decap_4".
 Reading "sky130_fd_sc_hd__and2_4".
-Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
 Reading "sky130_fd_sc_hd__or2_4".
 Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__buf_2".
 Reading "sky130_fd_sc_hd__and3_4".
-Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
 Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__inv_2".
 Reading "sky130_fd_sc_hd__a32o_4".
-Reading "sky130_fd_sc_hd__a2bb2o_4".
 Reading "sky130_fd_sc_hd__diode_2".
 Reading "sky130_fd_sc_hd__dfrtp_4".
-Reading "sky130_fd_sc_hd__a211o_4".
 Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
 Reading "sky130_fd_sc_hd__a21boi_4".
 Reading "sky130_fd_sc_hd__or4_4".
-Reading "sky130_fd_sc_hd__or3_4".
-Reading "sky130_fd_sc_hd__buf_4".
 Reading "sky130_fd_sc_hd__a21oi_4".
-Reading "sky130_fd_sc_hd__and4_4".
-Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__or3_4".
 Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__and4_4".
 Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__a22oi_4".
-Reading "sky130_fd_sc_hd__a2111o_4".
-Reading "sky130_fd_sc_hd__buf_8".
-Reading "sky130_fd_sc_hd__o32a_4".
 Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
 Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
 Reading "scr1_top_wb".
     100 uses
     200 uses
@@ -1823,9 +1823,21 @@
     176400 uses
     176500 uses
     176600 uses
+    176700 uses
+    176800 uses
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
 Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__mux2_4".
 Reading "clk_skew_adjust".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
 Reading "sky130_ef_sc_hd__fakediode_2".
+Reading "sky130_fd_sc_hd__bufbuf_16".
 Reading "wb_host".
     100 uses
     200 uses
@@ -1948,85 +1960,6 @@
     11900 uses
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-    12200 uses
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-    20000 uses
 Reading "sdrc_top".
     100 uses
     200 uses
@@ -2377,505 +2310,147 @@
     34700 uses
     34800 uses
     34900 uses
-Reading "sky130_fd_sc_hd__inv_4".
-Reading "uart_core".
-    100 uses
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-Reading "wb_interconnect".
-    100 uses
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-    35800 uses
-    35900 uses
-Reading "glbl_cfg".
+Reading "uart_core".
+    100 uses
+    200 uses
+    300 uses
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+    13500 uses
+    13600 uses
+    13700 uses
+Reading "wb_interconnect".
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@@ -3019,6 +2594,272 @@
     14100 uses
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+    14400 uses
+    14500 uses
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+    26000 uses
+    26100 uses
+    26200 uses
+    26300 uses
+    26400 uses
+    26500 uses
+    26600 uses
+Reading "glbl_cfg".
+    100 uses
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+    9200 uses
+    9300 uses
+    9400 uses
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+    11000 uses
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+    11300 uses
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+    12200 uses
+    12300 uses
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+    13300 uses
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+    13500 uses
+    13600 uses
+    13700 uses
+    13800 uses
+    13900 uses
+    14000 uses
+    14100 uses
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
 Reading "sky130_fd_sc_hd__o41a_4".
 Reading "spim_top".
     100 uses
@@ -3268,7 +3109,6 @@
     24500 uses
     24600 uses
     24700 uses
-    24800 uses
 Reading "user_project_wrapper".
 Root cell box:
            width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)

diff --git a/checks/full_log.log b/checks/full_log.log
index 2484dda..6d28b11 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log

@@ -3,8 +3,8 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 8: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 691 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/a', '/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/test.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-fastroute_4.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.param', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/21-fastroute_5.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/19-fastroute_3.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/18-fastroute_2.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext']
+ SPDX COMPLIANCE Found 971 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/user_project_wrapper.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_host.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/sdrc_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_interconnect.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/scr1_top_wb.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/glbl_cfg.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/test.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/uart_core.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_skew_adjust.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_buf.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/spef/spim_top.spef', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot']
  Executing Step 2 of 8: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.
@@ -32,11 +32,8 @@
 Step 4 done without fatal errors.
  Executing Step 5 of 8: XOR Consistency Checks
  Running XOR Checks...
-Total XOR differences = 0
- XOR Checks on User Project GDS Passed!
-Step 5 done without fatal errors.
+Total XOR differences = 2488
+ XOR Checks on GDS Failed, Reason: XOR Differences count is 2488. Please view /home/dinesha/workarea/opencore/git/yifive_r0/checks/*.xor.* for more details.
+TEST FAILED AT STEP 5
  Executing Step 6 of 8: DRC Violations Checks
  Running Magic DRC Checks...
- DRC Checks on User Project GDS Passed!
-Step 6 done without fatal errors.
- All Checks PASSED !!!

diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index 7f275df..c1fe571 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log

@@ -18,41 +18,41 @@
 Reading "sky130_fd_sc_hd__decap_6".
 Reading "sky130_fd_sc_hd__decap_12".
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__decap_4".
-Reading "sky130_fd_sc_hd__o22a_4".
 Reading "sky130_fd_sc_hd__fill_1".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__decap_4".
 Reading "sky130_fd_sc_hd__and2_4".
-Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
 Reading "sky130_fd_sc_hd__or2_4".
 Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__buf_2".
 Reading "sky130_fd_sc_hd__and3_4".
-Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
 Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__inv_2".
 Reading "sky130_fd_sc_hd__a32o_4".
-Reading "sky130_fd_sc_hd__a2bb2o_4".
 Reading "sky130_fd_sc_hd__diode_2".
 Reading "sky130_fd_sc_hd__dfrtp_4".
-Reading "sky130_fd_sc_hd__a211o_4".
 Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
 Reading "sky130_fd_sc_hd__a21boi_4".
 Reading "sky130_fd_sc_hd__or4_4".
-Reading "sky130_fd_sc_hd__or3_4".
-Reading "sky130_fd_sc_hd__buf_4".
 Reading "sky130_fd_sc_hd__a21oi_4".
-Reading "sky130_fd_sc_hd__and4_4".
-Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__or3_4".
 Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__and4_4".
 Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__a22oi_4".
-Reading "sky130_fd_sc_hd__a2111o_4".
-Reading "sky130_fd_sc_hd__buf_8".
-Reading "sky130_fd_sc_hd__o32a_4".
 Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
 Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
 Reading "scr1_top_wb".
     100 uses
     200 uses
@@ -1820,1460 +1820,5 @@
     176400 uses
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-Reading "sky130_fd_sc_hd__mux2_1".
-Reading "clk_skew_adjust".
-Reading "sky130_ef_sc_hd__fakediode_2".
-Reading "wb_host".
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-Reading "sdrc_top".
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-Reading "sky130_fd_sc_hd__inv_4".
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-Reading "wb_interconnect".
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-Reading "glbl_cfg".
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-Reading "sky130_fd_sc_hd__o41a_4".
-Reading "spim_top".
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-    24800 uses
-Reading "user_project_wrapper".
-[INFO]: Loading user_project_wrapper
-
-DRC style is now "drc(full)"
-Loading DRC CIF style.
-No errors found.
-[INFO]: COUNT: 0
-[INFO]: Should be divided by 3 or 4
-[INFO]: DRC Checking DONE (/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc)
-[INFO]: Saving mag view with DRC errors(/home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.magic.drc.mag)
-[INFO]: Saved
+    176700 uses
+    176800 uses

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 1496967..44d9a3b 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log

@@ -1,8 +1,17 @@
 FULL RUN LOG:
 SPDX NON-COMPLIANT FILES
-/home/dinesha/workarea/opencore/git/yifive_r0/a
 /home/dinesha/workarea/opencore/git/yifive_r0/README.md
-/home/dinesha/workarea/opencore/git/yifive_r0/test.v
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/user_project_wrapper.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_host.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/sdrc_top.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/wb_interconnect.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/scr1_top_wb.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/glbl_cfg.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/test.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/uart_core.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_skew_adjust.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/clk_buf.spef
+/home/dinesha/workarea/opencore/git/yifive_r0/spef/spim_top.spef
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl
@@ -12,11 +21,10 @@
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/23-tritonRoute.guide
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-fastroute_4.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.param
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/23-tritonRoute.param
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/21-fastroute_5.guide
-/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.guide
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/19-fastroute_3.guide
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/18-fastroute_2.guide
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext
@@ -64,35 +72,34 @@
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/runtime_summary_report.rpt.parsable
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/runtime_summary_report.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/manufacturability_report.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/26-opensta_spef_wns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_4.chk.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/26-opensta_spef.min_max.rpt
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/26-opensta_spef_tns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta.min_max.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/1-yosys_pre.stat
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/2-opensta_tns.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn.rpt
 /home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/reports/synthesis/11-opensta_post_openphysyn_tns.rpt
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 /home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/model/s25fl256s.sv
+/home/dinesha/workarea/opencore/git/yifive_r0/verilog/dv/wb_port/run_verilog
 /home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md
-/home/dinesha/workarea/opencore/git/yifive_r0/work/_info
-/home/dinesha/workarea/opencore/git/yifive_r0/work/_vmake

diff --git a/checks/xor.log b/checks/xor.log
index 73bb66b..caf81f2 100644
--- a/checks/xor.log
+++ b/checks/xor.log

@@ -10,30 +10,30 @@
 "_input" in: xor.drc:38
 Elapsed: 0.010s
 "^" in: xor.drc:38
-Elapsed: 0.000s
+Elapsed: 0.010s
 XOR differences: 0
 "_output" in: xor.drc:41
-Elapsed: 0.010s
+Elapsed: 0.000s
 --- Running XOR for 70/20 ---
 "_input" in: xor.drc:38
-Elapsed: 0.000s
-"_input" in: xor.drc:38
 Elapsed: 0.010s
-"^" in: xor.drc:38
+"_input" in: xor.drc:38
 Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.010s
 XOR differences: 0
 "_output" in: xor.drc:41
-Elapsed: 0.010s
+Elapsed: 0.000s
 --- Running XOR for 71/20 ---
 "_input" in: xor.drc:38
-Elapsed: 0.000s
+Elapsed: 0.010s
 "_input" in: xor.drc:38
-Elapsed: 0.010s
-"^" in: xor.drc:38
-Elapsed: 0.010s
-XOR differences: 0
-"_output" in: xor.drc:41
 Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 358
+"_output" in: xor.drc:41
+Elapsed: 0.010s
 --- Running XOR for 71/44 ---
 "_input" in: xor.drc:38
 Elapsed: 0.010s
@@ -41,7 +41,7 @@
 Elapsed: 0.000s
 "^" in: xor.drc:38
 Elapsed: 0.010s
-XOR differences: 0
+XOR differences: 1144
 "_output" in: xor.drc:41
 Elapsed: 0.000s
 --- Running XOR for 72/20 ---
@@ -51,7 +51,7 @@
 Elapsed: 0.000s
 "^" in: xor.drc:38
 Elapsed: 0.010s
-XOR differences: 0
+XOR differences: 984
 "_output" in: xor.drc:41
 Elapsed: 0.010s
 --- Running XOR for 81/14 ---
@@ -61,8 +61,8 @@
 Elapsed: 0.010s
 "^" in: xor.drc:38
 Elapsed: 0.000s
-XOR differences: 0
+XOR differences: 2
 "_output" in: xor.drc:41
 Elapsed: 0.010s
 Writing layout file: /home/dinesha/workarea/opencore/git/yifive_r0/checks/user_project_wrapper.xor.gds ..
-Total run time: 0.140s
+Total run time: 0.170s

diff --git a/checks/xor_total.txt b/checks/xor_total.txt
index 05b29a4..a8b880e 100644
--- a/checks/xor_total.txt
+++ b/checks/xor_total.txt

@@ -1 +1 @@
-Total XOR differences = 0
\ No newline at end of file
+Total XOR differences = 2488
\ No newline at end of file

diff --git a/def/glbl_cfg.def.gz b/def/glbl_cfg.def.gz
index df368f8..abcd60b 100644
--- a/def/glbl_cfg.def.gz
+++ b/def/glbl_cfg.def.gz
Binary files differ

diff --git a/def/sdram.def.gz b/def/sdram.def.gz
index 3ef2e1a..d884185 100644
--- a/def/sdram.def.gz
+++ b/def/sdram.def.gz
Binary files differ

diff --git a/def/spi_master.def.gz b/def/spi_master.def.gz
index 42c723a..e1d3e4a 100644
--- a/def/spi_master.def.gz
+++ b/def/spi_master.def.gz
Binary files differ

diff --git a/def/syntacore.def.gz b/def/syntacore.def.gz
index fded9b2..fca7476 100644
--- a/def/syntacore.def.gz
+++ b/def/syntacore.def.gz
Binary files differ

diff --git a/def/uart.def.gz b/def/uart.def.gz
index cd10f8a..884d46f 100644
--- a/def/uart.def.gz
+++ b/def/uart.def.gz
Binary files differ

diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 66a5961..d21d1b8 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ

diff --git a/gds/clk_buf.gds.gz b/gds/clk_buf.gds.gz
index f81bcb7..302dc6b 100644
--- a/gds/clk_buf.gds.gz
+++ b/gds/clk_buf.gds.gz
Binary files differ

diff --git a/gds/clk_skew_adjust.gds.gz b/gds/clk_skew_adjust.gds.gz
index 2113716..79df2d8 100644
--- a/gds/clk_skew_adjust.gds.gz
+++ b/gds/clk_skew_adjust.gds.gz
Binary files differ

diff --git a/gds/glbl_cfg.gds.gz b/gds/glbl_cfg.gds.gz
index 7e3c9cd..86fed6e 100644
--- a/gds/glbl_cfg.gds.gz
+++ b/gds/glbl_cfg.gds.gz
Binary files differ

diff --git a/gds/sdram.gds.gz b/gds/sdram.gds.gz
index ab34fcd..2abab3f 100644
--- a/gds/sdram.gds.gz
+++ b/gds/sdram.gds.gz
Binary files differ

diff --git a/gds/spi_master.gds.gz b/gds/spi_master.gds.gz
index 395803c..c08f789 100644
--- a/gds/spi_master.gds.gz
+++ b/gds/spi_master.gds.gz
Binary files differ

diff --git a/gds/syntacore.gds.gz b/gds/syntacore.gds.gz
index 63b437e..319a263 100644
--- a/gds/syntacore.gds.gz
+++ b/gds/syntacore.gds.gz
Binary files differ

diff --git a/gds/uart.gds.gz b/gds/uart.gds.gz
index 17f2175..35db17d 100644
--- a/gds/uart.gds.gz
+++ b/gds/uart.gds.gz
Binary files differ

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 3cba282..2743c7c 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
index 83b230a..159245a 100644
--- a/gds/wb_host.gds.gz
+++ b/gds/wb_host.gds.gz
Binary files differ

diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz
index 9d8118f..81bd0b6 100644
--- a/gds/wb_interconnect.gds.gz
+++ b/gds/wb_interconnect.gds.gz
Binary files differ

diff --git a/lef/glbl_cfg.lef.gz b/lef/glbl_cfg.lef.gz
index f4861d4..5a4f1da 100644
--- a/lef/glbl_cfg.lef.gz
+++ b/lef/glbl_cfg.lef.gz
Binary files differ

diff --git a/lef/sdram.lef.gz b/lef/sdram.lef.gz
index 57e521a..d980e33 100644
--- a/lef/sdram.lef.gz
+++ b/lef/sdram.lef.gz
Binary files differ

diff --git a/lef/spi_master.lef.gz b/lef/spi_master.lef.gz
index 3627d45..06f5f75 100644
--- a/lef/spi_master.lef.gz
+++ b/lef/spi_master.lef.gz
Binary files differ

diff --git a/lef/syntacore.lef.gz b/lef/syntacore.lef.gz
index 4860e37..71f2163 100644
--- a/lef/syntacore.lef.gz
+++ b/lef/syntacore.lef.gz
Binary files differ

diff --git a/lef/uart.lef.gz b/lef/uart.lef.gz
index 537ef18..7221619 100644
--- a/lef/uart.lef.gz
+++ b/lef/uart.lef.gz
Binary files differ

diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 5467c25..9992430 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ

diff --git a/mag/glbl_cfg.mag.gz b/mag/glbl_cfg.mag.gz
index c86d951..5443966 100644
--- a/mag/glbl_cfg.mag.gz
+++ b/mag/glbl_cfg.mag.gz
Binary files differ

diff --git a/mag/sdram.mag.gz b/mag/sdram.mag.gz
index 8528222..bef18d8 100644
--- a/mag/sdram.mag.gz
+++ b/mag/sdram.mag.gz
Binary files differ

diff --git a/mag/spi_master.mag.gz b/mag/spi_master.mag.gz
index b743581..9fad270 100644
--- a/mag/spi_master.mag.gz
+++ b/mag/spi_master.mag.gz
Binary files differ

diff --git a/mag/syntacore.mag.gz b/mag/syntacore.mag.gz
index cabc7a6..93ef92f 100644
--- a/mag/syntacore.mag.gz
+++ b/mag/syntacore.mag.gz
Binary files differ

diff --git a/mag/uart.mag.gz b/mag/uart.mag.gz
index 60b8b44..c5d9557 100644
--- a/mag/uart.mag.gz
+++ b/mag/uart.mag.gz
Binary files differ

diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 68bd2e2..7c25204 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ

diff --git a/maglef/glbl_cfg.mag.gz b/maglef/glbl_cfg.mag.gz
index 9e58cb7..3c0b843 100644
--- a/maglef/glbl_cfg.mag.gz
+++ b/maglef/glbl_cfg.mag.gz
Binary files differ

diff --git a/maglef/sdram.mag.gz b/maglef/sdram.mag.gz
index 8d867e9..338c3bd 100644
--- a/maglef/sdram.mag.gz
+++ b/maglef/sdram.mag.gz
Binary files differ

diff --git a/maglef/spi_master.mag.gz b/maglef/spi_master.mag.gz
index 49d4ec1..6f6e25f 100644
--- a/maglef/spi_master.mag.gz
+++ b/maglef/spi_master.mag.gz
Binary files differ

diff --git a/maglef/syntacore.mag.gz b/maglef/syntacore.mag.gz
index fcc1ea2..82c4514 100644
--- a/maglef/syntacore.mag.gz
+++ b/maglef/syntacore.mag.gz
Binary files differ

diff --git a/maglef/uart.mag.gz b/maglef/uart.mag.gz
index 064263b..f4b4154 100644
--- a/maglef/uart.mag.gz
+++ b/maglef/uart.mag.gz
Binary files differ

diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index 3bc90c8..0c356d2 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ

diff --git a/openlane/Makefile b/openlane/Makefile
index 0dbb3a1..c85d10d 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -21,7 +21,7 @@
 OPENLANE_TAG ?= v0.15
 OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
-OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 
 all: $(BLOCKS)
 

diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index 0c4cbcf..887e651 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl

@@ -78,5 +78,5 @@
 
 set ::env(FP_PDN_VPITCH) 100
 set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5

diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index e2ec32c..63d486b 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg

@@ -4,16 +4,16 @@
 #W
 mclk                   0000 0
 rst_n                  
-io_in\[5\]             0200 0
+io_in\[3\]             0200 0
 io_out\[5\]        
 io_oeb\[5\]  
-io_in\[4\]         
+io_in\[2\]         
 io_out\[4\]        
 io_oeb\[4\]  
-io_in\[3\]         
+io_in\[1\]         
 io_out\[3\]        
 io_oeb\[3\]  
-io_in\[2\]         
+io_in\[0\]         
 io_out\[2\]        
 io_oeb\[2\]  
 io_out\[1\]        

diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index 818dec9..b1eadeb 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl

@@ -87,5 +87,5 @@
 
 set ::env(FP_PDN_VPITCH) 100
 set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index b63ffed..9c9e20a 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -47,6 +47,8 @@
 set ::env(FP_SIZING) "absolute"
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
 
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
@@ -96,8 +98,8 @@
 
 set ::env(RUN_KLAYOUT_DRC) 0
 
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
+set ::env(VDD_PIN) [list {vdda1 vdda2 vccd1 vccd2}]
+set ::env(GND_PIN) [list {vssa1 vssa2 vssd1 vssd2}]
 
 set ::env(VDD_NETS) [list {vccd1}]
 set ::env(GND_NETS) [list {vssd1}]

diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 751ec7f..a6604a1 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h6m21s,0h4m2s,45883.33333333334,0.12,22941.66666666667,40,558.82,2753,0,0,0,0,0,0,0,3,0,-1,0,141434,23871,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,28.84,28.31,0.23,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h9m28s,0h6m33s,45883.33333333334,0.12,22941.66666666667,40,557.22,2753,0,0,0,0,0,0,0,0,0,-1,0,142255,24043,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,28.84,28.31,0.23,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4

diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index efe606d..22e101d 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m52s,0h5m32s,41131.42857142857,0.35,20565.714285714286,27,652.35,7198,0,0,0,0,0,0,0,11,0,-1,0,307721,51643,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h10m32s,0h5m40s,41131.42857142857,0.35,20565.714285714286,27,651.62,7198,0,0,0,0,0,0,0,11,0,-1,0,307721,51643,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3

diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 909798e..8d0d32b 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h10m10s,0h6m52s,45758.33333333334,0.24,22879.16666666667,33,621.43,5491,0,0,0,0,0,0,0,2,4,-1,0,246103,42258,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h12m59s,0h8m21s,45758.33333333334,0.24,22879.16666666667,33,608.8,5491,0,0,0,0,0,0,0,2,4,-1,0,246103,42258,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3

diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index a7d32d3..d84a6e7 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h2m32s,0h38m33s,34498.88888888888,1.8,17249.44444444444,23,1214.57,31049,0,0,0,0,0,0,0,95,10,-1,0,1627641,253589,-4.82,-4.82,-4.79,-4.79,-4.89,-38.56,-38.56,-38.91,-38.91,-39.32,1349556396,0.0,18.61,16.76,4.8,0.61,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,67.15916722632639,14.89,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h1m47s,0h39m1s,34498.88888888888,1.8,17249.44444444444,23,1212.41,31049,0,0,0,0,0,0,0,95,10,-1,0,1627641,253589,-4.82,-4.82,-4.79,-4.79,-4.89,-38.56,-38.56,-38.91,-38.91,-39.32,1349556396,0.0,18.61,16.76,4.8,0.61,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,67.15916722632639,14.89,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3

diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index c2b4760..5d02b7b 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m3s,0h2m57s,46166.66666666667,0.12,23083.333333333336,35,548.05,2770,0,0,0,0,0,0,0,0,0,-1,0,93312,20907,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h6m24s,0h4m13s,46166.66666666667,0.12,23083.333333333336,35,545.14,2770,0,0,0,0,0,0,0,0,0,-1,0,93784,20982,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 82ad7d4..f17a8a9 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m37s,0h5m15s,3.3079078455790785,10.2784,1.6539539227895392,0,604.07,17,0,0,0,0,0,0,0,0,4,-1,-1,1189768,4428,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.39,4.32,0.78,1.79,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h37m42s,0h4m32s,3.3079078455790785,10.2784,1.6539539227895392,0,552.07,17,0,0,0,0,0,0,0,0,1,-1,-1,1189479,3954,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.26,4.31,0.72,1.81,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0

diff --git a/spi/lvs/glbl_cfg.spice.gz b/spi/lvs/glbl_cfg.spice.gz
index d3c150a..7dda41d 100644
--- a/spi/lvs/glbl_cfg.spice.gz
+++ b/spi/lvs/glbl_cfg.spice.gz
Binary files differ

diff --git a/spi/lvs/sdram.spice.gz b/spi/lvs/sdram.spice.gz
index 3ed82d1..3dd9589 100644
--- a/spi/lvs/sdram.spice.gz
+++ b/spi/lvs/sdram.spice.gz
Binary files differ

diff --git a/spi/lvs/spi_master.spice.gz b/spi/lvs/spi_master.spice.gz
index 4050a30..b3a6fe4 100644
--- a/spi/lvs/spi_master.spice.gz
+++ b/spi/lvs/spi_master.spice.gz
Binary files differ

diff --git a/spi/lvs/syntacore.spice.gz b/spi/lvs/syntacore.spice.gz
index be36351..edddec6 100644
--- a/spi/lvs/syntacore.spice.gz
+++ b/spi/lvs/syntacore.spice.gz
Binary files differ

diff --git a/spi/lvs/uart.spice.gz b/spi/lvs/uart.spice.gz
index 17014d6..92acfde 100644
--- a/spi/lvs/uart.spice.gz
+++ b/spi/lvs/uart.spice.gz
Binary files differ

diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 8db684b..a3ff377 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ

diff --git a/verilog/gl/spi_master.v b/verilog/gl/spi_master.v
index a3d2d9a..f5bb31e 100644
--- a/verilog/gl/spi_master.v
+++ b/verilog/gl/spi_master.v

@@ -22,7 +22,7 @@
  input wbd_we_i;
  input vccd1;
  input vssd1;
- input [5:2] io_in;
+ input [3:0] io_in;
  output [5:0] io_oeb;
  output [5:0] io_out;
  output [31:0] spi_debug;
@@ -20788,7 +20788,7 @@
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__o22a_4 _07388_ (.A1(io_in[5]),
+ sky130_fd_sc_hd__o22a_4 _07388_ (.A1(io_in[3]),
     .A2(_03397_),
     .B1(\u_spictrl.u_rxreg.data_int[2] ),
     .B2(_03391_),
@@ -20831,7 +20831,7 @@
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__o22a_4 _07394_ (.A1(io_in[4]),
+ sky130_fd_sc_hd__o22a_4 _07394_ (.A1(io_in[2]),
     .A2(_03397_),
     .B1(\u_spictrl.u_rxreg.data_int[1] ),
     .B2(_03391_),
@@ -20874,7 +20874,7 @@
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__o22a_4 _07400_ (.A1(io_in[3]),
+ sky130_fd_sc_hd__o22a_4 _07400_ (.A1(io_in[1]),
     .A2(_03397_),
     .B1(\u_spictrl.u_rxreg.data_int[0] ),
     .B2(_02288_),
@@ -20917,9 +20917,9 @@
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__o22a_4 _07406_ (.A1(io_in[2]),
+ sky130_fd_sc_hd__o22a_4 _07406_ (.A1(io_in[0]),
     .A2(_02299_),
-    .B1(io_in[3]),
+    .B1(io_in[1]),
     .B2(_02288_),
     .X(_03415_),
     .VGND(vssd1),

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 17a2a58..8d26387 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v

@@ -7,6 +7,12 @@
     wbs_we_i,
     vccd1,
     vssd1,
+    vccd2,
+    vssd2,
+    vdda1,
+    vssa1,
+    vdda2,
+    vssa2,
     analog_io,
     io_in,
     io_oeb,
@@ -28,6 +34,12 @@
  input wbs_we_i;
  input vccd1;
  input vssd1;
+ input vccd2;
+ input vssd2;
+ input vdda1;
+ input vssa1;
+ input vdda2;
+ input vssa2;
  inout [28:0] analog_io;
  input [37:0] io_in;
  output [37:0] io_oeb;

diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 35bcd62..515cc18 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv

@@ -103,7 +103,7 @@
     output logic                 [31:0]  spi_debug,
 
     // PAD I/f
-    input  logic [5:2]                   io_in    ,
+    input  logic  [3:0]                  io_in    ,
     output logic  [5:0]                  io_out   ,
     output logic  [5:0]                  io_oeb
 
@@ -221,10 +221,10 @@
 logic                          spi_sdo3_dl;
 
 
-assign  spi_sdi0  =  io_in[2];
-assign  spi_sdi1  =  io_in[3];
-assign  spi_sdi2  =  io_in[4];
-assign  spi_sdi3  =  io_in[5];
+assign  spi_sdi0  =  io_in[0];
+assign  spi_sdi1  =  io_in[1];
+assign  spi_sdi2  =  io_in[2];
+assign  spi_sdi3  =  io_in[3];
 
 assign  io_out[0] =  spi_clk;
 assign  io_out[1] =  spi_csn0;// No hold fix for CS#, as it asserted much eariler than SPI clock
commit	a8d65905df44b70353b42900296c3fb8b5a7b47d	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Mon Jul 12 22:56:32 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Mon Jul 12 22:56:32 2021 +0530
tree	dfef0df91bbc6f97cf380070ef88d90dbed8a166
parent	93bc3159c67b218ea426ba0d9f425ab4ce8ea0b6 [diff]