riscv regression with coremark test passing
diff --git a/verilog/dv/model/mt48lc8m8a2.v b/verilog/dv/model/mt48lc8m8a2.v
index 0906d4d..cf309f1 100755
--- a/verilog/dv/model/mt48lc8m8a2.v
+++ b/verilog/dv/model/mt48lc8m8a2.v
@@ -114,6 +114,8 @@
// Internal system clock
reg CkeZ, Sys_clk;
+ event error_detected;
+
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
@@ -270,17 +272,17 @@
if (Debug) $display ("at time %t AREF : Auto Refresh", $time);
// Auto Refresh to Auto Refresh
if ($time - RC_chk < tRC) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if ($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Record Current tRC time
@@ -331,19 +333,19 @@
end
end else begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// REF to LMR
if ($time - RC_chk < tRC) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// LMR to LMR
if (MRD_chk < tMRD) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
MRD_chk = 0;
@@ -360,7 +362,7 @@
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);
end
end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
@@ -372,7 +374,7 @@
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);
end
end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
@@ -384,7 +386,7 @@
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 2", $time);
end
end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
@@ -396,42 +398,42 @@
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRP violation during Activate bank 3", $time);
end
end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);
end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);
end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);
end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);
end
// Active Bank A to Active Bank B
if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RC_chk < tRC) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
@@ -453,14 +455,22 @@
if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||
($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time);
+ if($time - RAS_chk0 < tRAS)
+ $display("ERROR: RAS_CHK0 Rxp: %t Exd: %t",$time - RAS_chk0,tRAS);
+ if($time - RAS_chk1 < tRAS)
+ $display("ERROR: RAS_CHK1 Rxp: %t Exd: %t",$time - RAS_chk1,tRAS);
+ if($time - RAS_chk2 < tRAS)
+ $display("ERROR: RAS_CHK2 Rxp: %t Exd: %t",$time - RAS_chk2,tRAS);
+ if($time - RAS_chk3 < tRAS)
+ $display("ERROR: RAS_CHK3 Rxp: %t Exd: %t",$time - RAS_chk3,tRAS);
end
// tWR violation check for write
if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) ||
($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tWR violation during Precharge all bank", $time);
end
end else if (Addr[10] == 1'b0) begin
@@ -471,7 +481,7 @@
// Activate to Precharge Bank 0
if ($time - RAS_chk0 < tRAS) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time);
end
end else if (Ba == 2'b01) begin
@@ -481,7 +491,7 @@
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time);
end
end else if (Ba == 2'b10) begin
@@ -491,7 +501,7 @@
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time);
end
end else if (Ba == 2'b11) begin
@@ -501,14 +511,14 @@
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);
end
end
// tWR violation check for write
if ($time - WR_chk[Ba] < tWRp) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba);
end
end
@@ -549,13 +559,13 @@
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time);
end
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 8aac4cc..1958002 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -15,7 +15,7 @@
override ARCH := IMC
override VECT_IRQ := 1
override IPIC := 1
- override TCM := 1
+ override TCM := 0
override SIM_CFG_DEF := SCR1_CFG_RV32IMC_MAX
else
ifeq ($(CFG), BASE)
@@ -23,7 +23,7 @@
override ARCH := IC
override VECT_IRQ := 1
override IPIC := 1
- override TCM := 1
+ override TCM := 0
override SIM_CFG_DEF := SCR1_CFG_RV32IC_BASE
else
ifeq ($(CFG), MIN)
@@ -31,7 +31,7 @@
override ARCH := EC
override VECT_IRQ := 0
override IPIC := 0
- override TCM := 1
+ override TCM := 0
override SIM_CFG_DEF := SCR1_CFG_RV32EC_MIN
else
# CUSTOM configuration. Parameters can be overwritten
@@ -156,8 +156,8 @@
export CROSS_PREFIX ?= riscv64-unknown-elf-
export RISCV_GCC ?= $(CROSS_PREFIX)gcc
export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
-export RISCV_ROM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -j .text.init -j .text -O verilog
-export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -O verilog
+export RISCV_ROM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -j .text.init -j .text -j .rodata -j .rodata.str1.4 -O verilog
+export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -O verilog
export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
ifneq (,$(findstring e,$(ARCH_lowercase)))
@@ -179,10 +179,10 @@
endif
# Comment this target if you don't want to run the isr_sample
-TARGETS += isr_sample
+#TARGETS += isr_sample
# Comment this target if you don't want to run the coremark
-#TARGETS += coremark
+TARGETS += coremark
# Comment this target if you don't want to run the dhrystone
#TARGETS += dhrystone21
@@ -215,7 +215,8 @@
$(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
coremark: | $(bld_dir)
- -$(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
+ @echo "core marks"
+ $(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
riscv_isa: | $(bld_dir)
$(MAKE) -C $(tst_dir)/riscv_isa ARCH=$(ARCH)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 37d6fb2..57964a4 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -177,9 +177,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(2, user_risc_regress_tb);
- $dumpvars(3, user_risc_regress_tb.u_top.u_sdram_ctrl);
- $dumpvars(4, user_risc_regress_tb.u_top.u_riscv_top);
+ $dumpvars(1, user_risc_regress_tb);
+ $dumpvars(0, user_risc_regress_tb.u_top.u_sdram_ctrl);
+ $dumpvars(0, user_risc_regress_tb.u_sdram8);
+ //$dumpvars(1, user_risc_regress_tb.u_top.u_riscv_top);
end
`endif
@@ -234,7 +235,7 @@
repeat (2) @(posedge clock);
#1;
//------------ SDRAM Config - 1
- wb_user_core_write('h3000_0010,'h2F17_2246);
+ wb_user_core_write('h3000_0010,'h2F17_2266);
repeat (2) @(posedge clock);
#1;
@@ -293,7 +294,7 @@
);
-logic [15:0] riscv_dmem_req_cnt; // cnt dmem req
+logic [31:0] riscv_dmem_req_cnt; // cnt dmem req
initial
begin
riscv_dmem_req_cnt = 0;
@@ -302,6 +303,8 @@
always @(posedge u_top.wbd_riscv_dmem_stb_i)
begin
riscv_dmem_req_cnt = riscv_dmem_req_cnt+1;
+ if((riscv_dmem_req_cnt %200) == 0)
+ $display("STATUS: Total Dmem Req Cnt: %d ",riscv_dmem_req_cnt);
end
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index bf69fd0..c852e19 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -446,7 +446,7 @@
//-----------------------------------------------------------------------
// reg-4
// recommended Default value:
-// 1'b1,3'h3,2'h3,4'h1,4'h7',4'h2,4'h2,4'h4,2'b01,2'b10 = 32'h2F17_2246
+// 1'b1,3'h3,2'h3,4'h1,4'h7',4'h2,4'h2,4'h6,2'b01,2'b10 = 32'h2F17_2266
//-----------------------------------------------------------------
assign cfg_sdr_width = reg_4[1:0] ; // 2'b10 // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
assign cfg_colbits = reg_4[3:2] ; // 2'b00 8 Bit column address, 2'b01 - 9 Bit column address,
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile
index 90ba866..3903cd9 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile
+++ b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile
@@ -1,5 +1,5 @@
src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
-depend_dir := $(src_dir)/../../../dependencies/coremark
+depend_dir := $(src_dir)/../../../../dependencies/coremark
ifeq ("$(ITERATIONS)","")
ITERATIONS=1
@@ -15,10 +15,12 @@
include $(inc_dir)/common.mk
+
default: log_requested_tgt $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump
log_requested_tgt:
echo coremark.hex>> $(bld_dir)/test_info
+ echo $(inc_dir)/common.mk
clean:
$(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
index 8a1d054..2d35442 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
@@ -58,6 +58,9 @@
$(bld_dir)/%.hex: $(bld_dir)/%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
+ #assign 0x2000_0xxx to 0x0000_0xxx to map to sdram
+ sed -i 's/@20000/@00000/g' $@.ram
+
$(bld_dir)/%.dump: $(bld_dir)/%.elf
$(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index d907410..cb87b13 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -27,8 +27,7 @@
MEMORY {
ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
- TCM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
}
STACK_SIZE = 1024;
@@ -60,7 +59,7 @@
*(sc_test_section)
. = ALIGN(CL_SIZE);
PROVIDE(__TEXT_END__ = .);
- } >TCM AT>RAM
+ } >ROM
.rodata ALIGN(CL_SIZE) : {
__global_pointer$ = . + 0x800;
@@ -68,7 +67,7 @@
. = ALIGN(CL_SIZE);
LONG(0x13);
. = ALIGN(CL_SIZE);
- } >TCM AT>RAM
+ } >ROM
/* data segment */
@@ -76,14 +75,14 @@
PROVIDE(__DATA_START__ = .);
*(.data .data.*)
. = ALIGN(CL_SIZE);
- } >TCM AT>RAM
+ }>RAM
.sdata ALIGN(CL_SIZE) : {
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(CL_SIZE);
PROVIDE(__DATA_END__ = .);
- } >TCM AT>RAM
+ } >RAM
/* thread-local data segment */
.tdata ALIGN(CL_SIZE) : {
@@ -92,14 +91,14 @@
*(.tdata .tdata.*)
PROVIDE(_tdata_end = .);
. = ALIGN(CL_SIZE);
- } >TCM AT>RAM
+ } >RAM
.tbss ALIGN(CL_SIZE) : {
PROVIDE(_tbss_begin = .);
*(.tbss .tbss.*)
. = ALIGN(CL_SIZE);
PROVIDE(_tbss_end = .);
- } >TCM AT>RAM
+ } >RAM
/* bss segment */
.sbss ALIGN(CL_SIZE) : {
@@ -107,25 +106,25 @@
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(CL_SIZE);
- } >TCM AT>RAM
+ } >RAM
.bss ALIGN(CL_SIZE) : {
*(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
. = ALIGN(CL_SIZE);
PROVIDE(__BSS_END__ = .);
- } >TCM AT>RAM
+ } >RAM
_end = .;
PROVIDE(__end = .);
/* End of uninitalized data segement */
- .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
+ .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : {
PROVIDE(__STACK_START__ = .);
. += STACK_SIZE;
PROVIDE(__C_STACK_TOP__ = .);
PROVIDE(__STACK_END__ = .);
- } >TCM
+ } >RAM
/DISCARD/ : {
*(.eh_frame .eh_frame.*)
