4x SRAM + 4x MBIST integrated with wishbone interconnect
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/glbl_cfg/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/glbl_cfg/PDK_SOURCES b/signoff/glbl_cfg/PDK_SOURCES new file mode 100644 index 0000000..ca3684a --- /dev/null +++ b/signoff/glbl_cfg/PDK_SOURCES
@@ -0,0 +1,6 @@ +-ne openlane +8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b +-ne skywater-pdk +c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +-ne open_pdks +14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv new file mode 100644 index 0000000..143a995 --- /dev/null +++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,flow_completed,0h2m44s,-1,34496.0,0.0625,17248.0,22.32,548.17,1078,0,0,0,0,0,0,0,1,0,-1,-1,56118,10305,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,34379429.0,0.0,23.92,17.17,1.87,1.98,-1,1093,1786,640,1301,0,0,0,740,0,0,0,0,0,0,0,4,339,281,11,166,765,0,931,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/mbist1/OPENLANE_VERSION b/signoff/mbist1/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/mbist1/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/mbist1/PDK_SOURCES b/signoff/mbist1/PDK_SOURCES new file mode 100644 index 0000000..ca3684a --- /dev/null +++ b/signoff/mbist1/PDK_SOURCES
@@ -0,0 +1,6 @@ +-ne openlane +8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b +-ne skywater-pdk +c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +-ne open_pdks +14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist1/final_summary_report.csv b/signoff/mbist1/final_summary_report.csv new file mode 100644 index 0000000..8a28c87 --- /dev/null +++ b/signoff/mbist1/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m50s,-1,49880.0,0.05,24940.0,30.9,584.83,1247,0,0,0,0,0,0,-1,11,0,0,-1,94813,15439,-2.97,-3.45,-1,-3.3,-1,-96.9,-108.64,-1,-139.61,-1,48342142.0,33.68,41.51,41.32,8.23,4.68,-1,1173,2529,315,1639,0,0,0,1157,0,0,0,0,0,0,0,4,232,261,16,166,595,0,761,111.11111111111111,9,8,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/mbist2/OPENLANE_VERSION b/signoff/mbist2/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/mbist2/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/mbist2/PDK_SOURCES b/signoff/mbist2/PDK_SOURCES new file mode 100644 index 0000000..ca3684a --- /dev/null +++ b/signoff/mbist2/PDK_SOURCES
@@ -0,0 +1,6 @@ +-ne openlane +8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b +-ne skywater-pdk +c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +-ne open_pdks +14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist2/final_summary_report.csv b/signoff/mbist2/final_summary_report.csv new file mode 100644 index 0000000..e28708f --- /dev/null +++ b/signoff/mbist2/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/mbist2,mbist_top2,mbist2,flow_completed,0h3m46s,-1,47080.0,0.05,23540.0,29.07,558.92,1177,0,0,0,0,0,0,-1,0,0,0,-1,73830,13504,-2.55,-3.03,-1,-3.22,-1,-86.73,-97.34,-1,-127.26,-1,44786491.0,24.11,36.18,28.45,9.41,0.26,-1,1120,2443,315,1606,0,0,0,1090,0,0,0,0,0,0,0,4,219,245,16,166,595,0,761,111.11111111111111,9,8,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 715b1c8..8892364 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h6m12s,-1,0.5837484433374844,10.2784,0.2918742216687422,-1,500.51,3,0,0,0,0,0,0,-1,0,0,-1,-1,605051,2144,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.93,1.45,0.12,0.06,-1,60,843,60,843,0,0,0,3,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h18m16s,-1,2.1404109589041096,10.2784,1.0702054794520548,-1,512.0,11,0,0,0,0,0,0,-1,0,0,-1,-1,996902,6096,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,2.28,2.21,0.08,0.13,-1,148,1674,148,1674,0,0,0,11,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index d977764..f682046 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m51s,-1,50283.33333333334,0.12,25141.66666666667,28.0,605.29,3017,0,0,0,0,0,0,0,3,0,0,-1,163509,26410,0.0,-0.32,-1,0.0,-1,0.0,-9.1,-1,0.0,-1,104829193.0,4.06,36.24,25.62,6.37,1.56,-1,1353,3716,627,2954,0,0,0,1466,0,0,0,0,0,0,0,4,710,926,12,204,1560,0,1764,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h5m32s,-1,45300.0,0.12,22650.0,26.77,606.54,2718,0,0,0,0,0,0,0,3,0,0,-1,167703,26005,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,123482009.0,4.87,36.56,26.85,6.78,0.27,-1,1165,3352,658,2843,0,0,0,1301,0,0,0,0,0,0,0,4,709,844,13,204,1560,0,1764,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES new file mode 100644 index 0000000..ca3684a --- /dev/null +++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -0,0 +1,6 @@ +-ne openlane +8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b +-ne skywater-pdk +c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +-ne open_pdks +14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv new file mode 100644 index 0000000..21d6546 --- /dev/null +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h5m39s,-1,5824.242424242424,0.33,2912.121212121212,2.63,613.77,961,0,-1,-1,-1,-1,0,0,1,0,-1,-1,352615,12599,-1.97,0.0,-1,-0.83,-1,-1.97,0.0,-1,-0.83,-1,306869576.0,20.31,9.0,35.51,0.38,10.03,-1,475,2106,155,1786,0,0,0,703,0,0,0,0,0,0,0,4,239,323,8,1600,4010,0,5610,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4