| commit | 4376ed5acbfc0fe80e2d2f998e091af18fc2bb1a | [log] [tgz] |
|---|---|---|
| author | dineshannayya <dinesh.annayya@gmail.com> | Tue Nov 23 14:02:30 2021 +0530 |
| committer | dineshannayya <dinesh.annayya@gmail.com> | Tue Nov 23 14:02:30 2021 +0530 |
| tree | f2df07cc2431c5e4d9ebce78d49197c922d99d59 | |
| parent | 59a04a6e6cb7af4a528b180a2d19ec4dbafa3d3d [diff] [blame] |
Timing clean up
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 00441ab..57c4e51 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -96,5 +96,5 @@ set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"