| 0-prep 3.542 |
| 1-yosys 1.732 |
| 2-opensta 2.317 |
| 3-verilog2def_openroad 1.434 |
| 4-ioPlacer 1.126 |
| 5-tapcell 1.123 |
| 7-pdn 2.118 |
| 8-replace 3.061 |
| 8-resizer 1.796 |
| 9-write_verilog 1.186 |
| 10-opensta_post_resizer 2.3810000000000002 |
| 11-opendp 1.209 |
| 12-resizer_timing 1.579 |
| 13-write_verilog 1.199 |
| 14-resizer_timing 1.674 |
| 14-opensta_post_resizer_timing 2.358 |
| 15-write_verilog 1.18 |
| 16-opensta_post_resizer_routing_timing 2.413 |
| 18-opendp 1.238 |
| 19-write_verilog 1.152 |
| 19-diodes 1.165 |
| 20-addspacers 1.437 |
| 21-fastroute 3.396 |
| 22-write_verilog 1.376 |
| 23-tritonRoute 48.832 |
| 24-spef_extraction 1.759 |
| 25-opensta_spef 2.91 |
| 27-write_verilog 1.429 |
| 31-magic_gen 15.942 |
| 32-klayout 1.6400000000000001 |
| 34-klayout_xor 38.191 |
| 35-magic_ext_spice 14.515 |
| 36-lvs 17.769 |
| 37-magic_drc 64.58 |
| 39-or_antenna 1.324 |
| 40-prep 2.112 |
| 40-cvc 0.605 |
