| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: ./designs/axmul/src/axmul.v |
| Parsing SystemVerilog input from `./designs/axmul/src/axmul.v' to AST representation. |
| Generating RTLIL representation for module `\axmul'. |
| Generating RTLIL representation for module `\acc_incrementor_3bit_cin'. |
| Generating RTLIL representation for module `\prop_mult2_sdk'. |
| Generating RTLIL representation for module `\fulladd'. |
| Generating RTLIL representation for module `\recurse_config_8'. |
| Generating RTLIL representation for module `\kgp'. |
| Generating RTLIL representation for module `\recursive_stage1'. |
| Successfully finished Verilog frontend. |
| |
| 2. Generating Graphviz representation of design. |
| Writing dot description to `/openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/hierarchy.dot'. |
| Dumping module axmul to page 1. |
| |
| 3. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 3.1. Analyzing design hierarchy.. |
| Top module: \axmul |
| Used module: \acc_incrementor_3bit_cin |
| Used module: \recurse_config_8 |
| Used module: \recursive_stage1 |
| Used module: \kgp |
| Used module: \fulladd |
| Used module: \prop_mult2_sdk |
| |
| 3.2. Analyzing design hierarchy.. |
| Top module: \axmul |
| Used module: \acc_incrementor_3bit_cin |
| Used module: \recurse_config_8 |
| Used module: \recursive_stage1 |
| Used module: \kgp |
| Used module: \fulladd |
| Used module: \prop_mult2_sdk |
| Removed 0 unused modules. |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[2].genblk1[16].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[2].genblk1[14].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[2].genblk1[12].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[2].genblk1[10].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[2].genblk1[8].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[16].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[14].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[12].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[10].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[8].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[6].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[1].genblk1[4].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[16].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[14].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[12].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[10].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[8].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[6].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[4].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.recursiveStg.genblk1[0].genblk1[2].s (recursive_stage1). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[7].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[6].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[5].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[4].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[3].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[2].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[1].t (kgp). |
| Mapping positional arguments of cell recurse_config_8.kgp_gen.genblk1[0].t (kgp). |
| Mapping positional arguments of cell axmul.u2 (acc_incrementor_3bit_cin). |
| Mapping positional arguments of cell axmul.ad1 (recurse_config_8). |
| Mapping positional arguments of cell axmul.f8 (fulladd). |
| Mapping positional arguments of cell axmul.f7 (fulladd). |
| Mapping positional arguments of cell axmul.f6 (fulladd). |
| Mapping positional arguments of cell axmul.f5 (fulladd). |
| Mapping positional arguments of cell axmul.f4 (fulladd). |
| Mapping positional arguments of cell axmul.f3 (fulladd). |
| Mapping positional arguments of cell axmul.f2 (fulladd). |
| Mapping positional arguments of cell axmul.f1 (fulladd). |
| Mapping positional arguments of cell axmul.z4 (prop_mult2_sdk). |
| Mapping positional arguments of cell axmul.z3 (prop_mult2_sdk). |
| Mapping positional arguments of cell axmul.z2 (prop_mult2_sdk). |
| Mapping positional arguments of cell axmul.z1 (prop_mult2_sdk). |
| |
| 4. Executing TRIBUF pass. |
| |
| 5. Executing SYNTH pass. |
| |
| 5.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 5.1.1. Analyzing design hierarchy.. |
| Top module: \axmul |
| Used module: \acc_incrementor_3bit_cin |
| Used module: \recurse_config_8 |
| Used module: \recursive_stage1 |
| Used module: \kgp |
| Used module: \fulladd |
| Used module: \prop_mult2_sdk |
| |
| 5.1.2. Analyzing design hierarchy.. |
| Top module: \axmul |
| Used module: \acc_incrementor_3bit_cin |
| Used module: \recurse_config_8 |
| Used module: \recursive_stage1 |
| Used module: \kgp |
| Used module: \fulladd |
| Used module: \prop_mult2_sdk |
| Removed 0 unused modules. |
| |
| 5.2. Executing PROC pass (convert processes to netlists). |
| |
| 5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed a total of 0 dead cases. |
| |
| 5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). |
| Removed 0 redundant assignments. |
| Promoted 84 assignments to connections. |
| |
| 5.2.4. Executing PROC_INIT pass (extract init attributes). |
| |
| 5.2.5. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$284'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$280'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$276'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$272'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$268'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$264'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$260'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$256'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$254'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$252'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$250'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$248'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$246'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$244'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$242'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$240'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$238'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$236'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$234'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$232'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$230'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$228'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$226'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$224'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$222'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$220'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$218'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$216'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$214'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$212'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$210'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$208'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$206'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$204'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$202'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$200'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$198'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$196'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$194'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$192'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$190'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$188'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$186'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$184'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$182'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$180'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$178'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$176'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$174'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$172'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$170'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$168'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$166'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$164'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$162'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$160'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$158'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$156'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$154'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$152'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$150'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$148'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$146'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$144'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$142'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$140'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$138'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$136'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$134'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$132'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$130'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$128'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$126'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$124'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$122'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$120'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$118'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$116'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$114'. |
| Creating decoders for process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$112'. |
| |
| 5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). |
| No latch inferred for signal `\recurse_config_8.\x[0] [1:0]' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| No latch inferred for signal `\recurse_config_8.\x[1] [1:0]' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| No latch inferred for signal `\recurse_config_8.\x[2] [3:0]' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| No latch inferred for signal `\recurse_config_8.\x[3] [7:0]' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$111' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$284'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$110' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$280'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$109' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$276'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$108' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$272'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$107' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$268'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$106' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$264'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$105' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$260'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:134$104' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$256'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$103' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$254'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$102' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$252'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$101' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$250'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$100' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$248'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$99' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$246'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$98' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$244'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$97' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$242'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$96' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$240'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$95' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$238'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$94' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$236'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$93' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$234'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$92' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$232'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$91' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$230'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$90' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$228'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$89' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$226'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:125$88' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$224'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$87' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$222'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$86' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$220'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$85' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$218'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$84' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$216'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$83' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$214'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$82' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$212'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$81' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$210'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$80' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$208'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$79' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$206'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$78' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$204'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$77' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$202'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$76' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$200'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$75' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$198'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$74' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$196'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$73' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$194'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$72' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$192'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$71' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$190'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$70' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$188'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$69' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$186'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$68' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$184'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$67' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$182'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:125$66' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$180'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$65' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$178'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$64' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$176'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$63' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$174'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$62' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$172'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$61' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$170'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$60' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$168'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$59' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$166'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$58' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$164'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$57' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$162'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$56' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$160'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$55' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$158'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$54' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$156'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$53' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$154'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$52' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$152'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$51' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$150'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$50' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$148'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$49' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$146'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$48' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$144'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$47' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$142'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$46' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$140'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$45' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$138'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$44' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$136'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$43' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$134'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:128$42' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$132'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:125$41' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$130'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$40' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$128'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$39' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$126'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$38' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$124'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$37' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$122'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$36' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$120'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$35' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$118'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$34' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$116'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:120$33' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$114'. |
| No latch inferred for signal `\recurse_config_8.$mem2bits$\x$./designs/axmul/src/axmul.v:114$32' from process `\recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$112'. |
| |
| 5.2.8. Executing PROC_DFF pass (convert process syncs to FFs). |
| |
| 5.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). |
| |
| 5.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$288'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$284'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$280'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$276'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$272'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$268'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$264'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$260'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$256'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$254'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$252'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$250'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$248'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$246'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$244'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$242'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$240'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$238'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$236'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$234'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$232'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$230'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$228'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$226'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$224'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$222'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$220'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$218'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$216'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$214'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$212'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$210'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$208'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$206'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$204'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$202'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$200'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$198'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$196'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$194'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$192'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$190'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$188'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$186'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$184'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$182'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$180'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$178'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$176'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$174'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$172'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$170'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$168'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$166'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$164'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$162'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$160'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$158'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$156'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$154'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$152'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$150'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$148'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$146'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$144'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$142'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$140'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$138'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$136'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$134'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$132'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$130'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$128'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$126'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$124'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$122'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$120'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$118'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$116'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$114'. |
| Removing empty process `recurse_config_8.$proc$./designs/axmul/src/axmul.v:0$112'. |
| Cleaned up 0 empty switches. |
| |
| 5.3. Executing FLATTEN pass (flatten design). |
| Deleting now unused module recursive_stage1. |
| Deleting now unused module kgp. |
| Deleting now unused module recurse_config_8. |
| Deleting now unused module fulladd. |
| Deleting now unused module prop_mult2_sdk. |
| Deleting now unused module acc_incrementor_3bit_cin. |
| <suppressed ~42 debug messages> |
| |
| 5.4. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| <suppressed ~13 debug messages> |
| |
| 5.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 28 unused cells and 399 unused wires. |
| <suppressed ~37 debug messages> |
| |
| 5.6. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Found and reported 0 problems. |
| |
| 5.7. Executing OPT pass (performing simple optimizations). |
| |
| 5.7.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.7.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| <suppressed ~39 debug messages> |
| Removed a total of 13 cells. |
| |
| 5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 5.7.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.7.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 13 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 5.7.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.7.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 5.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 5.7.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.7.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.7.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.7.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 5.8. Executing FSM pass (extract and optimize FSM). |
| |
| 5.8.1. Executing FSM_DETECT pass (finding FSMs in design). |
| |
| 5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| |
| 5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| |
| 5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| 5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| |
| 5.9. Executing OPT pass (performing simple optimizations). |
| |
| 5.9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 5.9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.9.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 5.10. Executing WREDUCE pass (reducing word size of cells). |
| Removed top 3 bits (of 4) from port Y of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:78$16 ($and). |
| Removed top 3 bits (of 4) from port A of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:78$16 ($and). |
| Removed top 3 bits (of 4) from port B of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:78$16 ($and). |
| Removed top 2 bits (of 4) from port Y of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:77$15 ($and). |
| Removed top 2 bits (of 4) from port A of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:77$15 ($and). |
| Removed top 2 bits (of 4) from port B of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:77$15 ($and). |
| Removed top 1 bits (of 4) from port Y of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:76$14 ($and). |
| Removed top 1 bits (of 4) from port A of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:76$14 ($and). |
| Removed top 1 bits (of 4) from port B of cell axmul.$flatten\z2.$and$./designs/axmul/src/axmul.v:76$14 ($and). |
| Removed top 12 bits (of 16) from wire axmul.q1. |
| |
| 5.11. Executing PEEPOPT pass (run peephole optimizers). |
| |
| 5.12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 5.13. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module axmul: |
| created 0 $alu and 0 $macc cells. |
| |
| 5.14. Executing SHARE pass (SAT-based resource sharing). |
| |
| 5.15. Executing OPT pass (performing simple optimizations). |
| |
| 5.15.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 5.15.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.15.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.15.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.15.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 5.16. Executing MEMORY pass. |
| |
| 5.16.1. Executing OPT_MEM pass (optimize memories). |
| Performed a total of 0 transformations. |
| |
| 5.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd). |
| |
| 5.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| |
| 5.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 5.17. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.18. Executing OPT pass (performing simple optimizations). |
| |
| 5.18.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| <suppressed ~38 debug messages> |
| |
| 5.18.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.18.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.18.5. Finished fast OPT passes. |
| |
| 5.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). |
| |
| 5.20. Executing OPT pass (performing simple optimizations). |
| |
| 5.20.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.20.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 5.20.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.20.6. Executing OPT_SHARE pass. |
| |
| 5.20.7. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.20.9. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.20.10. Finished OPT passes. (There is nothing left to do.) |
| |
| 5.21. Executing TECHMAP pass (map to technology primitives). |
| |
| 5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v |
| Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod_trunc'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\$__div_mod_floor'. |
| Generating RTLIL representation for module `\_90_divfloor'. |
| Generating RTLIL representation for module `\_90_modfloor'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| |
| 5.21.2. Continuing TECHMAP pass. |
| Using extmapper simplemap for cells of type $and. |
| Using extmapper simplemap for cells of type $xor. |
| Using extmapper simplemap for cells of type $or. |
| Using extmapper simplemap for cells of type $not. |
| No more expansions possible. |
| <suppressed ~313 debug messages> |
| |
| 5.22. Executing OPT pass (performing simple optimizations). |
| |
| 5.22.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.22.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 5.22.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 5.22.5. Finished fast OPT passes. |
| |
| 5.23. Executing ABC pass (technology mapping using ABC). |
| |
| 5.23.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 288 gates and 304 wires to a netlist network with 16 inputs and 16 outputs. |
| |
| 5.23.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_library <abc-temp-dir>/stdcells.genlib |
| ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". |
| ABC: + strash |
| ABC: + dretime |
| ABC: + map |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 5.23.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 49 |
| ABC RESULTS: ANDNOT cells: 90 |
| ABC RESULTS: MUX cells: 2 |
| ABC RESULTS: NAND cells: 23 |
| ABC RESULTS: NOR cells: 4 |
| ABC RESULTS: NOT cells: 3 |
| ABC RESULTS: OR cells: 32 |
| ABC RESULTS: ORNOT cells: 22 |
| ABC RESULTS: XNOR cells: 4 |
| ABC RESULTS: XOR cells: 38 |
| ABC RESULTS: internal signals: 272 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 16 |
| Removing temp directory. |
| |
| 5.24. Executing OPT pass (performing simple optimizations). |
| |
| 5.24.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 5.24.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| <suppressed ~9 debug messages> |
| Removed a total of 3 cells. |
| |
| 5.24.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 305 unused wires. |
| <suppressed ~211 debug messages> |
| |
| 5.24.5. Finished fast OPT passes. |
| |
| 5.25. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 5.25.1. Analyzing design hierarchy.. |
| Top module: \axmul |
| |
| 5.25.2. Analyzing design hierarchy.. |
| Top module: \axmul |
| Removed 0 unused modules. |
| |
| 5.26. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 293 |
| Number of wire bits: 504 |
| Number of public wires: 45 |
| Number of public wire bits: 256 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 264 |
| $_ANDNOT_ 89 |
| $_AND_ 49 |
| $_MUX_ 2 |
| $_NAND_ 23 |
| $_NOR_ 4 |
| $_NOT_ 3 |
| $_ORNOT_ 22 |
| $_OR_ 31 |
| $_XNOR_ 4 |
| $_XOR_ 37 |
| |
| 5.27. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Found and reported 0 problems. |
| |
| 6. Generating Graphviz representation of design. |
| Writing dot description to `/openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/post_techmap.dot'. |
| Dumping module axmul to page 1. |
| |
| 7. Executing SHARE pass (SAT-based resource sharing). |
| |
| 8. Executing OPT pass (performing simple optimizations). |
| |
| 8.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 8.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \axmul.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \axmul. |
| Performed a total of 0 changes. |
| |
| 8.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\axmul'. |
| Removed a total of 0 cells. |
| |
| 8.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| |
| 8.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module axmul. |
| |
| 8.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 9. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 41 unused wires. |
| <suppressed ~41 debug messages> |
| |
| 10. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 252 |
| Number of wire bits: 281 |
| Number of public wires: 4 |
| Number of public wire bits: 33 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 264 |
| $_ANDNOT_ 89 |
| $_AND_ 49 |
| $_MUX_ 2 |
| $_NAND_ 23 |
| $_NOR_ 4 |
| $_NOT_ 3 |
| $_ORNOT_ 22 |
| $_OR_ 31 |
| $_XNOR_ 4 |
| $_XOR_ 37 |
| |
| mapping tbuf |
| |
| 11. Executing TECHMAP pass (map to technology primitives). |
| |
| 11.1. Executing Verilog-2005 frontend: /soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v |
| Parsing Verilog input from `/soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_TBUF_'. |
| Successfully finished Verilog frontend. |
| |
| 11.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~3 debug messages> |
| |
| 12. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 13. Executing MUXCOVER pass (mapping to wider MUXes). |
| Covering MUX trees in module axmul.. |
| Treeifying 2 MUXes: |
| Found tree with 1 MUXes at root \c [14]. |
| Found tree with 1 MUXes at root \c [15]. |
| Finished treeification: Found 2 trees. |
| Covering trees: |
| Replaced tree at \c [14]: 1 MUX2, 0 MUX4, 0 MUX8, 0 MUX16 |
| Replaced tree at \c [15]: 1 MUX2, 0 MUX4, 0 MUX8, 0 MUX16 |
| Added a total of 0 decoder MUXes. |
| <suppressed ~35 debug messages> |
| |
| 14. Executing TECHMAP pass (map to technology primitives). |
| |
| 14.1. Executing Verilog-2005 frontend: /soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v |
| Parsing Verilog input from `/soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_MUX4_'. |
| Successfully finished Verilog frontend. |
| |
| 14.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~3 debug messages> |
| |
| 15. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 16. Executing TECHMAP pass (map to technology primitives). |
| |
| 16.1. Executing Verilog-2005 frontend: /soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v |
| Parsing Verilog input from `/soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_MUX_'. |
| Successfully finished Verilog frontend. |
| |
| 16.2. Continuing TECHMAP pass. |
| Using template \$_MUX_ for cells of type $_MUX_. |
| No more expansions possible. |
| <suppressed ~5 debug messages> |
| |
| 17. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 18. Executing TECHMAP pass (map to technology primitives). |
| |
| 18.1. Executing Verilog-2005 frontend: /soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v |
| Parsing Verilog input from `/soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_DLATCH_P_'. |
| Generating RTLIL representation for module `\$_DLATCH_N_'. |
| Successfully finished Verilog frontend. |
| |
| 18.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~4 debug messages> |
| |
| 19. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 20. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_. |
| cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_. |
| cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_. |
| cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. |
| final dff cell mappings: |
| unmapped dff cell: $_DFF_N_ |
| \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| unmapped dff cell: $_DFF_NN0_ |
| unmapped dff cell: $_DFF_NN1_ |
| unmapped dff cell: $_DFF_NP0_ |
| unmapped dff cell: $_DFF_NP1_ |
| \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); |
| \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); |
| unmapped dff cell: $_DFF_PP0_ |
| unmapped dff cell: $_DFF_PP1_ |
| \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); |
| unmapped dff cell: $_DFFSR_NNP_ |
| unmapped dff cell: $_DFFSR_NPN_ |
| unmapped dff cell: $_DFFSR_NPP_ |
| unmapped dff cell: $_DFFSR_PNN_ |
| unmapped dff cell: $_DFFSR_PNP_ |
| unmapped dff cell: $_DFFSR_PPN_ |
| unmapped dff cell: $_DFFSR_PPP_ |
| |
| 20.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). |
| Mapping DFF cells in module `\axmul': |
| |
| 21. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 260 |
| Number of wire bits: 289 |
| Number of public wires: 4 |
| Number of public wire bits: 33 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 264 |
| $_ANDNOT_ 89 |
| $_AND_ 49 |
| $_NAND_ 23 |
| $_NOR_ 4 |
| $_NOT_ 3 |
| $_ORNOT_ 22 |
| $_OR_ 31 |
| $_XNOR_ 4 |
| $_XOR_ 37 |
| sky130_fd_sc_hd__mux2_1 2 |
| |
| [INFO]: ABC: WireLoad : S_0 |
| |
| 22. Executing ABC pass (technology mapping using ABC). |
| |
| 22.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 22.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 6 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + map -p -B 0.2 -A 0.9 -M 0 |
| ABC: The cell areas are multiplied by the factor: <num_fanins> ^ (0.90). |
| ABC: The cell delays are multiplied by the factor: <num_fanins> ^ (0.20). |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (1866.96 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 250 ( 16.8 %) Cap = 10.4 ff ( 3.5 %) Area = 2024.44 ( 83.2 %) Delay = 1780.49 ps ( 30.4 %) |
| ABC: Path 0 -- 9 : 0 2 pi A = 0.00 Df = 5.8 -4.0 ps S = 17.5 ps Cin = 0.0 ff Cout = 4.4 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 88 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 200.8 -66.0 ps S = 224.8 ps Cin = 2.1 ff Cout = 18.5 ff Cmax = 130.0 ff G = 841 |
| ABC: Path 2 -- 105 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 482.3 -151.2 ps S = 282.7 ps Cin = 2.1 ff Cout = 23.5 ff Cmax = 130.0 ff G = 1079 |
| ABC: Path 3 -- 107 : 3 1 sky130_fd_sc_hd__nand3_2 A = 10.01 Df = 595.1 -158.5 ps S = 78.3 ps Cin = 4.4 ff Cout = 4.6 ff Cmax = 260.0 ff G = 99 |
| ABC: Path 4 -- 108 : 2 3 sky130_fd_sc_hd__nand2_2 A = 6.26 Df = 698.5 -192.3 ps S = 80.8 ps Cin = 4.4 ff Cout = 11.7 ff Cmax = 295.7 ff G = 251 |
| ABC: Path 5 -- 113 : 3 5 sky130_fd_sc_hd__nand3_2 A = 10.01 Df = 824.0 -201.2 ps S = 133.2 ps Cin = 4.4 ff Cout = 20.7 ff Cmax = 260.0 ff G = 448 |
| ABC: Path 6 -- 195 : 3 3 sky130_fd_sc_hd__nor3b_2 A = 12.51 Df =1044.1 -7.9 ps S = 285.6 ps Cin = 3.4 ff Cout = 14.1 ff Cmax = 93.4 ff G = 388 |
| ABC: Path 7 -- 242 : 4 2 sky130_fd_sc_hd__o211ai_2 A = 12.51 Df =1217.9 -16.0 ps S = 179.9 ps Cin = 4.4 ff Cout = 9.3 ff Cmax = 133.7 ff G = 204 |
| ABC: Path 8 -- 243 : 3 1 sky130_fd_sc_hd__nand3_2 A = 10.01 Df =1300.1 -14.4 ps S = 52.7 ps Cin = 4.4 ff Cout = 2.6 ff Cmax = 260.0 ff G = 53 |
| ABC: Path 9 -- 244 : 3 2 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =1496.1 -62.1 ps S = 49.2 ps Cin = 2.4 ff Cout = 6.9 ff Cmax = 309.5 ff G = 284 |
| ABC: Path 10 -- 250 : 3 1 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =1683.0 -134.3 ps S = 39.0 ps Cin = 2.4 ff Cout = 4.6 ff Cmax = 309.5 ff G = 188 |
| ABC: Path 11 -- 252 : 2 1 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1780.5 -140.3 ps S = 108.7 ps Cin = 4.4 ff Cout = 17.6 ff Cmax = 295.7 ff G = 398 |
| ABC: Start-point = pi8 (\a [4]). End-point = po8 (\c [11]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 250 edge = 595 area =947.93 delay =1270.95 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 22.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a211o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 8 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 17 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a221oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__a41oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 29 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 67 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 31 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__nor3b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__o21ba_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2ai_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 9 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 23. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 24. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 25. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 26. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 27. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 28. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 29. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 239 |
| Number of wire bits: 268 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 252 |
| sky130_fd_sc_hd__a211o_2 1 |
| sky130_fd_sc_hd__a211oi_2 1 |
| sky130_fd_sc_hd__a21boi_2 5 |
| sky130_fd_sc_hd__a21o_2 8 |
| sky130_fd_sc_hd__a21oi_2 17 |
| sky130_fd_sc_hd__a221o_2 2 |
| sky130_fd_sc_hd__a221oi_2 1 |
| sky130_fd_sc_hd__a22o_2 5 |
| sky130_fd_sc_hd__a22oi_2 6 |
| sky130_fd_sc_hd__a41oi_2 1 |
| sky130_fd_sc_hd__and2_2 10 |
| sky130_fd_sc_hd__buf_1 29 |
| sky130_fd_sc_hd__inv_2 13 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__mux2_2 1 |
| sky130_fd_sc_hd__nand2_2 67 |
| sky130_fd_sc_hd__nand3_2 31 |
| sky130_fd_sc_hd__nand3b_2 3 |
| sky130_fd_sc_hd__nor2_2 11 |
| sky130_fd_sc_hd__nor3_2 2 |
| sky130_fd_sc_hd__nor3b_2 1 |
| sky130_fd_sc_hd__o211a_2 1 |
| sky130_fd_sc_hd__o211ai_2 3 |
| sky130_fd_sc_hd__o21a_2 2 |
| sky130_fd_sc_hd__o21ai_2 9 |
| sky130_fd_sc_hd__o21ba_2 1 |
| sky130_fd_sc_hd__o21bai_2 4 |
| sky130_fd_sc_hd__o221ai_2 1 |
| sky130_fd_sc_hd__o2bb2ai_2 2 |
| sky130_fd_sc_hd__xnor2_2 3 |
| sky130_fd_sc_hd__xor2_2 9 |
| |
| Chip area for module '\axmul': 2046.963200 |
| |
| 30. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_1 |
| |
| 31. Executing ABC pass (technology mapping using ABC). |
| |
| 31.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 31.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 6 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + map -p -B 0.2 -A 0.9 -M 0 |
| ABC: The cell areas are multiplied by the factor: <num_fanins> ^ (0.90). |
| ABC: The cell delays are multiplied by the factor: <num_fanins> ^ (0.20). |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + map |
| ABC: + |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (1909.16 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 282 ( 18.1 %) Cap = 10.1 ff ( 3.5 %) Area = 2190.85 ( 81.9 %) Delay = 1905.66 ps ( 18.8 %) |
| ABC: Path 0 -- 11 : 0 2 pi A = 0.00 Df = 4.9 -3.4 ps S = 16.5 ps Cin = 0.0 ff Cout = 3.7 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 85 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 195.5 -62.1 ps S = 218.9 ps Cin = 2.1 ff Cout = 18.0 ff Cmax = 130.0 ff G = 823 |
| ABC: Path 2 -- 104 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 470.2 -146.4 ps S = 274.1 ps Cin = 2.1 ff Cout = 22.8 ff Cmax = 130.0 ff G = 1030 |
| ABC: Path 3 -- 129 : 4 2 sky130_fd_sc_hd__a22oi_2 A = 12.51 Df = 614.5 -67.4 ps S = 190.4 ps Cin = 4.3 ff Cout = 9.2 ff Cmax = 170.3 ff G = 206 |
| ABC: Path 4 -- 130 : 2 5 sky130_fd_sc_hd__nor2_2 A = 6.26 Df = 881.2 -207.7 ps S = 272.0 ps Cin = 4.4 ff Cout = 23.2 ff Cmax = 141.9 ff G = 500 |
| ABC: Path 5 -- 131 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df = 972.0 -73.2 ps S = 62.7 ps Cin = 4.4 ff Cout = 6.1 ff Cmax = 295.7 ff G = 133 |
| ABC: Path 6 -- 135 : 2 2 sky130_fd_sc_hd__and2_2 A = 7.51 Df =1155.4 -109.7 ps S = 57.2 ps Cin = 1.5 ff Cout = 7.0 ff Cmax = 303.0 ff G = 463 |
| ABC: Path 7 -- 253 : 2 5 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1266.9 -133.1 ps S = 123.9 ps Cin = 4.4 ff Cout = 20.8 ff Cmax = 295.7 ff G = 453 |
| ABC: Path 8 -- 275 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1332.4 -112.1 ps S = 60.4 ps Cin = 4.4 ff Cout = 6.2 ff Cmax = 295.7 ff G = 135 |
| ABC: Path 9 -- 276 : 3 1 sky130_fd_sc_hd__or3_2 A = 7.51 Df =1788.5 -182.8 ps S = 83.7 ps Cin = 1.5 ff Cout = 4.6 ff Cmax = 310.4 ff G = 291 |
| ABC: Path 10 -- 278 : 2 1 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1905.7 -222.3 ps S = 108.7 ps Cin = 4.4 ff Cout = 17.6 ff Cmax = 295.7 ff G = 398 |
| ABC: Start-point = pi10 (\b [6]). End-point = po9 (\c [10]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 282 edge = 681 area =1012.94 delay =1377.74 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 31.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a211o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 14 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 12 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__a31oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a32oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__and4_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 29 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 22 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 83 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 33 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 15 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o2111a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o2111ai_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o311ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o31a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 3 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 32. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 33. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 34. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 35. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 36. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 37. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 38. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 271 |
| Number of wire bits: 300 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 284 |
| sky130_fd_sc_hd__a211o_2 1 |
| sky130_fd_sc_hd__a211oi_2 1 |
| sky130_fd_sc_hd__a21o_2 3 |
| sky130_fd_sc_hd__a21oi_2 14 |
| sky130_fd_sc_hd__a221o_2 2 |
| sky130_fd_sc_hd__a22o_2 1 |
| sky130_fd_sc_hd__a22oi_2 12 |
| sky130_fd_sc_hd__a31o_2 3 |
| sky130_fd_sc_hd__a31oi_2 1 |
| sky130_fd_sc_hd__a32oi_2 2 |
| sky130_fd_sc_hd__and2_2 11 |
| sky130_fd_sc_hd__and3_2 6 |
| sky130_fd_sc_hd__and4_2 1 |
| sky130_fd_sc_hd__buf_1 29 |
| sky130_fd_sc_hd__inv_2 22 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__nand2_2 83 |
| sky130_fd_sc_hd__nand3_2 33 |
| sky130_fd_sc_hd__nand3b_2 2 |
| sky130_fd_sc_hd__nor2_2 15 |
| sky130_fd_sc_hd__nor3_2 2 |
| sky130_fd_sc_hd__o2111a_2 1 |
| sky130_fd_sc_hd__o2111ai_2 2 |
| sky130_fd_sc_hd__o211a_2 3 |
| sky130_fd_sc_hd__o211ai_2 7 |
| sky130_fd_sc_hd__o21a_2 3 |
| sky130_fd_sc_hd__o21ai_2 6 |
| sky130_fd_sc_hd__o21bai_2 1 |
| sky130_fd_sc_hd__o221ai_2 1 |
| sky130_fd_sc_hd__o22ai_2 3 |
| sky130_fd_sc_hd__o2bb2ai_2 1 |
| sky130_fd_sc_hd__o311ai_2 1 |
| sky130_fd_sc_hd__o31a_2 1 |
| sky130_fd_sc_hd__or2b_2 2 |
| sky130_fd_sc_hd__or3_2 1 |
| sky130_fd_sc_hd__xnor2_2 2 |
| sky130_fd_sc_hd__xor2_2 3 |
| |
| Chip area for module '\axmul': 2213.372800 |
| |
| 39. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_2 |
| |
| 40. Executing ABC pass (technology mapping using ABC). |
| |
| 40.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 40.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 6 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + map -p -B 0.2 -A 0.9 -M 0 |
| ABC: The cell areas are multiplied by the factor: <num_fanins> ^ (0.90). |
| ABC: The cell delays are multiplied by the factor: <num_fanins> ^ (0.20). |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + map |
| ABC: + |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (1705.60 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 283 ( 17.0 %) Cap = 10.3 ff ( 3.2 %) Area = 2215.88 ( 83.0 %) Delay = 1856.86 ps ( 7.1 %) |
| ABC: Path 0 -- 11 : 0 3 pi A = 0.00 Df = 11.2 -7.6 ps S = 24.1 ps Cin = 0.0 ff Cout = 9.0 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 76 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 244.2 -88.5 ps S = 276.9 ps Cin = 2.1 ff Cout = 23.0 ff Cmax = 130.0 ff G = 1050 |
| ABC: Path 2 -- 77 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df = 327.8 -78.6 ps S = 74.0 ps Cin = 4.4 ff Cout = 6.1 ff Cmax = 295.7 ff G = 132 |
| ABC: Path 3 -- 79 : 2 2 sky130_fd_sc_hd__nor2_2 A = 6.26 Df = 461.8 -167.7 ps S = 103.4 ps Cin = 4.4 ff Cout = 6.8 ff Cmax = 141.9 ff G = 148 |
| ABC: Path 4 -- 80 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 810.0 -307.3 ps S = 409.1 ps Cin = 2.1 ff Cout = 34.4 ff Cmax = 130.0 ff G = 1598 |
| ABC: Path 5 -- 98 : 2 5 sky130_fd_sc_hd__nor2_2 A = 6.26 Df = 960.4 -156.8 ps S = 271.0 ps Cin = 4.4 ff Cout = 23.2 ff Cmax = 141.9 ff G = 500 |
| ABC: Path 6 -- 316 : 4 1 sky130_fd_sc_hd__a211oi_2 A = 12.51 Df =1758.4 -285.4 ps S = 172.1 ps Cin = 4.4 ff Cout = 4.6 ff Cmax = 88.8 ff G = 101 |
| ABC: Path 7 -- 318 : 2 1 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =1856.9 -25.3 ps S = 213.8 ps Cin = 4.4 ff Cout = 17.6 ff Cmax = 141.9 ff G = 399 |
| ABC: Start-point = pi10 (\b [6]). End-point = po18 (\c [13]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 283 edge = 672 area =1038.13 delay =1337.43 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 40.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 8 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 16 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a31oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a32oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 25 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 23 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 85 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 31 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 20 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 5 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 41. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 42. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 43. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 44. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 45. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 46. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 47. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 272 |
| Number of wire bits: 301 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 285 |
| sky130_fd_sc_hd__a211oi_2 1 |
| sky130_fd_sc_hd__a21boi_2 3 |
| sky130_fd_sc_hd__a21o_2 8 |
| sky130_fd_sc_hd__a21oi_2 16 |
| sky130_fd_sc_hd__a221o_2 2 |
| sky130_fd_sc_hd__a22o_2 2 |
| sky130_fd_sc_hd__a22oi_2 11 |
| sky130_fd_sc_hd__a31o_2 1 |
| sky130_fd_sc_hd__a31oi_2 1 |
| sky130_fd_sc_hd__a32oi_2 1 |
| sky130_fd_sc_hd__and2_2 7 |
| sky130_fd_sc_hd__and3_2 4 |
| sky130_fd_sc_hd__buf_1 25 |
| sky130_fd_sc_hd__inv_2 23 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__mux2_2 1 |
| sky130_fd_sc_hd__nand2_2 85 |
| sky130_fd_sc_hd__nand3_2 31 |
| sky130_fd_sc_hd__nand3b_2 5 |
| sky130_fd_sc_hd__nor2_2 20 |
| sky130_fd_sc_hd__nor3_2 1 |
| sky130_fd_sc_hd__o211a_2 2 |
| sky130_fd_sc_hd__o211ai_2 7 |
| sky130_fd_sc_hd__o21a_2 4 |
| sky130_fd_sc_hd__o21ai_2 5 |
| sky130_fd_sc_hd__o21bai_2 1 |
| sky130_fd_sc_hd__o221a_2 1 |
| sky130_fd_sc_hd__o221ai_2 3 |
| sky130_fd_sc_hd__o22ai_2 1 |
| sky130_fd_sc_hd__o2bb2ai_2 1 |
| sky130_fd_sc_hd__or2_2 1 |
| sky130_fd_sc_hd__xnor2_2 4 |
| sky130_fd_sc_hd__xor2_2 5 |
| |
| Chip area for module '\axmul': 2238.396800 |
| |
| 48. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_3 |
| |
| 49. Executing ABC pass (technology mapping using ABC). |
| |
| 49.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 49.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + map -p -B 0.2 -A 0.9 -M 0 |
| ABC: The cell areas are multiplied by the factor: <num_fanins> ^ (0.90). |
| ABC: The cell delays are multiplied by the factor: <num_fanins> ^ (0.20). |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (1813.02 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 254 ( 18.1 %) Cap = 10.1 ff ( 3.8 %) Area = 1976.90 ( 81.5 %) Delay = 1890.11 ps ( 5.9 %) |
| ABC: Path 0 -- 14 : 0 2 pi A = 0.00 Df = 8.8 -6.1 ps S = 21.0 ps Cin = 0.0 ff Cout = 6.8 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 92 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 221.4 -76.6 ps S = 248.9 ps Cin = 2.1 ff Cout = 20.6 ff Cmax = 130.0 ff G = 938 |
| ABC: Path 2 -- 125 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 503.2 -160.9 ps S = 278.0 ps Cin = 2.1 ff Cout = 23.1 ff Cmax = 130.0 ff G = 1049 |
| ABC: Path 3 -- 202 : 2 1 sky130_fd_sc_hd__nand2_2 A = 6.26 Df = 569.1 -140.9 ps S = 50.7 ps Cin = 4.4 ff Cout = 1.6 ff Cmax = 295.7 ff G = 34 |
| ABC: Path 4 -- 203 : 3 5 sky130_fd_sc_hd__and3_2 A = 7.51 Df = 815.4 -157.4 ps S = 110.0 ps Cin = 1.5 ff Cout = 17.4 ff Cmax = 309.5 ff G = 1123 |
| ABC: Path 5 -- 218 : 3 2 sky130_fd_sc_hd__nand3b_2 A = 11.26 Df =1045.7 -235.4 ps S = 91.4 ps Cin = 3.5 ff Cout = 9.2 ff Cmax = 263.7 ff G = 256 |
| ABC: Path 6 -- 223 : 3 4 sky130_fd_sc_hd__a21oi_2 A = 8.76 Df =1262.5 -274.2 ps S = 199.3 ps Cin = 4.6 ff Cout = 14.0 ff Cmax = 128.2 ff G = 292 |
| ABC: Path 7 -- 247 : 3 3 sky130_fd_sc_hd__o21a_2 A = 8.76 Df =1451.4 -168.8 ps S = 87.7 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 294.8 ff G = 575 |
| ABC: Path 8 -- 275 : 3 3 sky130_fd_sc_hd__nand3_2 A = 10.01 Df =1565.0 -168.7 ps S = 96.0 ps Cin = 4.4 ff Cout = 13.7 ff Cmax = 260.0 ff G = 298 |
| ABC: Path 9 -- 286 : 2 1 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1640.3 -190.2 ps S = 45.8 ps Cin = 4.4 ff Cout = 4.6 ff Cmax = 295.7 ff G = 100 |
| ABC: Path 10 -- 287 : 3 1 sky130_fd_sc_hd__a21oi_2 A = 8.76 Df =1686.4 -116.3 ps S = 100.1 ps Cin = 4.6 ff Cout = 4.6 ff Cmax = 128.2 ff G = 96 |
| ABC: Path 11 -- 289 : 2 1 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =1890.1 -26.9 ps S = 213.6 ps Cin = 4.4 ff Cout = 17.6 ff Cmax = 141.9 ff G = 399 |
| ABC: Start-point = pi13 (\a [5]). End-point = po18 (\c [13]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 254 edge = 581 area =958.82 delay =1258.17 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 49.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__and2b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__and4_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 27 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 19 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 82 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 30 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__nor2b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o2111ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 10 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 50. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 51. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 52. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 53. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 54. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 55. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 56. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 243 |
| Number of wire bits: 272 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 256 |
| sky130_fd_sc_hd__a211oi_2 1 |
| sky130_fd_sc_hd__a21boi_2 1 |
| sky130_fd_sc_hd__a21o_2 5 |
| sky130_fd_sc_hd__a21oi_2 13 |
| sky130_fd_sc_hd__a221o_2 2 |
| sky130_fd_sc_hd__a22o_2 1 |
| sky130_fd_sc_hd__a22oi_2 7 |
| sky130_fd_sc_hd__and2_2 7 |
| sky130_fd_sc_hd__and2b_2 1 |
| sky130_fd_sc_hd__and3_2 2 |
| sky130_fd_sc_hd__and4_2 1 |
| sky130_fd_sc_hd__buf_1 27 |
| sky130_fd_sc_hd__inv_2 19 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__mux2_2 1 |
| sky130_fd_sc_hd__nand2_2 82 |
| sky130_fd_sc_hd__nand3_2 30 |
| sky130_fd_sc_hd__nand3b_2 5 |
| sky130_fd_sc_hd__nor2_2 9 |
| sky130_fd_sc_hd__nor2b_2 1 |
| sky130_fd_sc_hd__nor3_2 1 |
| sky130_fd_sc_hd__o2111ai_2 1 |
| sky130_fd_sc_hd__o211a_2 2 |
| sky130_fd_sc_hd__o211ai_2 3 |
| sky130_fd_sc_hd__o21a_2 4 |
| sky130_fd_sc_hd__o21ai_2 10 |
| sky130_fd_sc_hd__o21bai_2 3 |
| sky130_fd_sc_hd__o221ai_2 1 |
| sky130_fd_sc_hd__o22ai_2 1 |
| sky130_fd_sc_hd__or2b_2 1 |
| sky130_fd_sc_hd__xnor2_2 2 |
| sky130_fd_sc_hd__xor2_2 10 |
| |
| Chip area for module '\axmul': 1999.417600 |
| |
| 57. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_4 |
| |
| 58. Executing ABC pass (technology mapping using ABC). |
| |
| 58.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 58.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 73 has dup fanin 71. |
| ABC: Node 73 has dup fanin 72. |
| ABC: Node 73 has dup fanin 71. |
| ABC: Node 73 has dup fanin 72. |
| ABC: Node 88 has dup fanin 86. |
| ABC: Node 88 has dup fanin 87. |
| ABC: Node 88 has dup fanin 86. |
| ABC: Node 88 has dup fanin 87. |
| ABC: Node 89 has dup fanin 85. |
| ABC: Node 89 has dup fanin 88. |
| ABC: Node 89 has dup fanin 85. |
| ABC: Node 89 has dup fanin 88. |
| ABC: Node 90 has dup fanin 83. |
| ABC: Node 90 has dup fanin 89. |
| ABC: Node 90 has dup fanin 83. |
| ABC: Node 90 has dup fanin 89. |
| ABC: Node 94 has dup fanin 91. |
| ABC: Node 94 has dup fanin 93. |
| ABC: Node 94 has dup fanin 91. |
| ABC: Node 94 has dup fanin 93. |
| ABC: Node 97 has dup fanin 76. |
| ABC: Node 97 has dup fanin 94. |
| ABC: Node 97 has dup fanin 76. |
| ABC: Node 97 has dup fanin 94. |
| ABC: Node 101 has dup fanin 99. |
| ABC: Node 101 has dup fanin 100. |
| ABC: Node 101 has dup fanin 99. |
| ABC: Node 101 has dup fanin 100. |
| ABC: Node 114 has dup fanin 111. |
| ABC: Node 114 has dup fanin 113. |
| ABC: Node 114 has dup fanin 111. |
| ABC: Node 114 has dup fanin 113. |
| ABC: Node 118 has dup fanin 101. |
| ABC: Node 118 has dup fanin 103. |
| ABC: Node 118 has dup fanin 101. |
| ABC: Node 118 has dup fanin 103. |
| ABC: Node 125 has dup fanin 123. |
| ABC: Node 125 has dup fanin 124. |
| ABC: Node 125 has dup fanin 123. |
| ABC: Node 125 has dup fanin 124. |
| ABC: Node 126 has dup fanin 122. |
| ABC: Node 126 has dup fanin 125. |
| ABC: Node 126 has dup fanin 122. |
| ABC: Node 126 has dup fanin 125. |
| ABC: Node 129 has dup fanin 127. |
| ABC: Node 129 has dup fanin 128. |
| ABC: Node 129 has dup fanin 127. |
| ABC: Node 129 has dup fanin 128. |
| ABC: Node 130 has dup fanin 126. |
| ABC: Node 130 has dup fanin 129. |
| ABC: Node 130 has dup fanin 126. |
| ABC: Node 130 has dup fanin 129. |
| ABC: Node 133 has dup fanin 114. |
| ABC: Node 133 has dup fanin 116. |
| ABC: Node 133 has dup fanin 114. |
| ABC: Node 133 has dup fanin 116. |
| ABC: Node 147 has dup fanin 144. |
| ABC: Node 147 has dup fanin 146. |
| ABC: Node 147 has dup fanin 144. |
| ABC: Node 147 has dup fanin 146. |
| ABC: Node 149 has dup fanin 68. |
| ABC: Node 149 has dup fanin 73. |
| ABC: Node 149 has dup fanin 68. |
| ABC: Node 149 has dup fanin 73. |
| ABC: Node 153 has dup fanin 66. |
| ABC: Node 153 has dup fanin 147. |
| ABC: Node 153 has dup fanin 66. |
| ABC: Node 153 has dup fanin 147. |
| ABC: Node 160 has dup fanin 80. |
| ABC: Node 160 has dup fanin 159. |
| ABC: Node 160 has dup fanin 80. |
| ABC: Node 160 has dup fanin 159. |
| ABC: Node 169 has dup fanin 161. |
| ABC: Node 169 has dup fanin 168. |
| ABC: Node 169 has dup fanin 161. |
| ABC: Node 169 has dup fanin 168. |
| ABC: Node 171 has dup fanin 143. |
| ABC: Node 171 has dup fanin 170. |
| ABC: Node 171 has dup fanin 143. |
| ABC: Node 171 has dup fanin 170. |
| ABC: Node 177 has dup fanin 175. |
| ABC: Node 177 has dup fanin 176. |
| ABC: Node 177 has dup fanin 175. |
| ABC: Node 177 has dup fanin 176. |
| ABC: Node 179 has dup fanin 141. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 179 has dup fanin 141. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 181 has dup fanin 163. |
| ABC: Node 181 has dup fanin 180. |
| ABC: Node 181 has dup fanin 163. |
| ABC: Node 181 has dup fanin 180. |
| ABC: Node 190 has dup fanin 83. |
| ABC: Node 190 has dup fanin 187. |
| ABC: Node 190 has dup fanin 83. |
| ABC: Node 190 has dup fanin 187. |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (3182.16 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 176 ( 27.8 %) Cap = 7.6 ff ( 5.0 %) Area = 1320.02 ( 72.2 %) Delay = 2899.06 ps ( 9.1 %) |
| ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 6.1 -4.2 ps S = 17.8 ps Cin = 0.0 ff Cout = 4.6 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 38 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 29.1 -3.2 ps S = 24.5 ps Cin = 4.5 ff Cout = 3.7 ff Cmax = 331.4 ff G = 79 |
| ABC: Path 2 -- 128 : 4 4 sky130_fd_sc_hd__or4_2 A = 8.76 Df = 701.6 -543.8 ps S = 119.0 ps Cin = 1.5 ff Cout = 7.7 ff Cmax = 310.4 ff G = 485 |
| ABC: Path 3 -- 151 : 2 3 sky130_fd_sc_hd__or2b_2 A = 8.76 Df = 898.3 -244.9 ps S = 61.4 ps Cin = 1.6 ff Cout = 6.0 ff Cmax = 312.2 ff G = 366 |
| ABC: Path 4 -- 155 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1171.0 -116.6 ps S = 52.5 ps Cin = 1.7 ff Cout = 6.0 ff Cmax = 300.3 ff G = 335 |
| ABC: Path 5 -- 162 : 4 2 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1437.3 -19.0 ps S = 52.7 ps Cin = 1.7 ff Cout = 6.1 ff Cmax = 300.3 ff G = 338 |
| ABC: Path 6 -- 163 : 2 4 sky130_fd_sc_hd__or2_2 A = 6.26 Df =1736.9 -193.5 ps S = 75.0 ps Cin = 1.5 ff Cout = 10.2 ff Cmax = 299.4 ff G = 668 |
| ABC: Path 7 -- 166 : 2 1 sky130_fd_sc_hd__or2_2 A = 6.26 Df =2030.8 -385.9 ps S = 52.5 ps Cin = 1.5 ff Cout = 2.5 ff Cmax = 299.4 ff G = 163 |
| ABC: Path 8 -- 168 : 4 3 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =2288.4 -479.8 ps S = 66.2 ps Cin = 2.4 ff Cout = 8.2 ff Cmax = 271.9 ff G = 333 |
| ABC: Path 9 -- 169 : 1 1 sky130_fd_sc_hd__inv_2 A = 3.75 Df =2329.4 -493.1 ps S = 23.3 ps Cin = 4.5 ff Cout = 2.5 ff Cmax = 331.4 ff G = 52 |
| ABC: Path 10 -- 171 : 5 3 sky130_fd_sc_hd__o221a_2 A = 11.26 Df =2519.5 -257.3 ps S = 72.1 ps Cin = 2.3 ff Cout = 8.6 ff Cmax = 281.1 ff G = 351 |
| ABC: Path 11 -- 175 : 5 2 sky130_fd_sc_hd__o221ai_2 A = 15.01 Df =2614.7 -201.5 ps S = 145.3 ps Cin = 4.5 ff Cout = 3.7 ff Cmax = 128.2 ff G = 77 |
| ABC: Path 12 -- 176 : 4 1 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =2899.1 -6.6 ps S = 106.5 ps Cin = 1.7 ff Cout = 17.6 ff Cmax = 300.3 ff G = 1025 |
| ABC: Start-point = pi1 (\a [3]). End-point = po7 (\c [12]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 176 edge = 456 area =1320.02 delay =14.00 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 58.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 28 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 17 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2a_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 29 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 3 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 59. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 60. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 61. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 62. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 63. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 64. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 65. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 165 |
| Number of wire bits: 194 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 178 |
| sky130_fd_sc_hd__a21oi_2 1 |
| sky130_fd_sc_hd__a2bb2o_2 21 |
| sky130_fd_sc_hd__a2bb2oi_2 2 |
| sky130_fd_sc_hd__a31o_2 5 |
| sky130_fd_sc_hd__and2_2 4 |
| sky130_fd_sc_hd__buf_1 21 |
| sky130_fd_sc_hd__inv_2 28 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__nand2_2 6 |
| sky130_fd_sc_hd__nor2_2 10 |
| sky130_fd_sc_hd__o211a_2 1 |
| sky130_fd_sc_hd__o21a_2 3 |
| sky130_fd_sc_hd__o21ai_2 3 |
| sky130_fd_sc_hd__o221a_2 10 |
| sky130_fd_sc_hd__o221ai_2 3 |
| sky130_fd_sc_hd__o22a_2 17 |
| sky130_fd_sc_hd__o2bb2a_2 3 |
| sky130_fd_sc_hd__o32a_2 1 |
| sky130_fd_sc_hd__or2_2 29 |
| sky130_fd_sc_hd__or2b_2 5 |
| sky130_fd_sc_hd__or4_2 3 |
| |
| Chip area for module '\axmul': 1342.537600 |
| |
| 66. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_5 |
| |
| 67. Executing ABC pass (technology mapping using ABC). |
| |
| 67.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 67.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 10000.0 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 73 has dup fanin 71. |
| ABC: Node 73 has dup fanin 72. |
| ABC: Node 73 has dup fanin 71. |
| ABC: Node 73 has dup fanin 72. |
| ABC: Node 85 has dup fanin 82. |
| ABC: Node 85 has dup fanin 84. |
| ABC: Node 85 has dup fanin 82. |
| ABC: Node 85 has dup fanin 84. |
| ABC: Node 87 has dup fanin 68. |
| ABC: Node 87 has dup fanin 73. |
| ABC: Node 87 has dup fanin 68. |
| ABC: Node 87 has dup fanin 73. |
| ABC: Node 96 has dup fanin 94. |
| ABC: Node 96 has dup fanin 95. |
| ABC: Node 96 has dup fanin 94. |
| ABC: Node 96 has dup fanin 95. |
| ABC: Node 97 has dup fanin 93. |
| ABC: Node 97 has dup fanin 96. |
| ABC: Node 97 has dup fanin 93. |
| ABC: Node 97 has dup fanin 96. |
| ABC: Node 98 has dup fanin 91. |
| ABC: Node 98 has dup fanin 97. |
| ABC: Node 98 has dup fanin 91. |
| ABC: Node 98 has dup fanin 97. |
| ABC: Node 102 has dup fanin 99. |
| ABC: Node 102 has dup fanin 101. |
| ABC: Node 102 has dup fanin 99. |
| ABC: Node 102 has dup fanin 101. |
| ABC: Node 108 has dup fanin 105. |
| ABC: Node 108 has dup fanin 107. |
| ABC: Node 108 has dup fanin 105. |
| ABC: Node 108 has dup fanin 107. |
| ABC: Node 115 has dup fanin 113. |
| ABC: Node 115 has dup fanin 114. |
| ABC: Node 115 has dup fanin 113. |
| ABC: Node 115 has dup fanin 114. |
| ABC: Node 118 has dup fanin 115. |
| ABC: Node 118 has dup fanin 117. |
| ABC: Node 118 has dup fanin 115. |
| ABC: Node 118 has dup fanin 117. |
| ABC: Node 128 has dup fanin 126. |
| ABC: Node 128 has dup fanin 127. |
| ABC: Node 128 has dup fanin 126. |
| ABC: Node 128 has dup fanin 127. |
| ABC: Node 129 has dup fanin 125. |
| ABC: Node 129 has dup fanin 128. |
| ABC: Node 129 has dup fanin 125. |
| ABC: Node 129 has dup fanin 128. |
| ABC: Node 132 has dup fanin 130. |
| ABC: Node 132 has dup fanin 131. |
| ABC: Node 132 has dup fanin 130. |
| ABC: Node 132 has dup fanin 131. |
| ABC: Node 133 has dup fanin 129. |
| ABC: Node 133 has dup fanin 132. |
| ABC: Node 133 has dup fanin 129. |
| ABC: Node 133 has dup fanin 132. |
| ABC: Node 136 has dup fanin 108. |
| ABC: Node 136 has dup fanin 110. |
| ABC: Node 136 has dup fanin 108. |
| ABC: Node 136 has dup fanin 110. |
| ABC: Node 146 has dup fanin 76. |
| ABC: Node 146 has dup fanin 102. |
| ABC: Node 146 has dup fanin 76. |
| ABC: Node 146 has dup fanin 102. |
| ABC: Node 157 has dup fanin 66. |
| ABC: Node 157 has dup fanin 85. |
| ABC: Node 157 has dup fanin 66. |
| ABC: Node 157 has dup fanin 85. |
| ABC: Node 162 has dup fanin 81. |
| ABC: Node 162 has dup fanin 161. |
| ABC: Node 162 has dup fanin 81. |
| ABC: Node 162 has dup fanin 161. |
| ABC: Node 171 has dup fanin 163. |
| ABC: Node 171 has dup fanin 170. |
| ABC: Node 171 has dup fanin 163. |
| ABC: Node 171 has dup fanin 170. |
| ABC: Node 173 has dup fanin 153. |
| ABC: Node 173 has dup fanin 172. |
| ABC: Node 173 has dup fanin 153. |
| ABC: Node 173 has dup fanin 172. |
| ABC: Node 179 has dup fanin 177. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 179 has dup fanin 177. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 181 has dup fanin 143. |
| ABC: Node 181 has dup fanin 180. |
| ABC: Node 181 has dup fanin 143. |
| ABC: Node 181 has dup fanin 180. |
| ABC: Node 183 has dup fanin 142. |
| ABC: Node 183 has dup fanin 182. |
| ABC: Node 183 has dup fanin 142. |
| ABC: Node 183 has dup fanin 182. |
| ABC: Node 191 has dup fanin 91. |
| ABC: Node 191 has dup fanin 188. |
| ABC: Node 191 has dup fanin 91. |
| ABC: Node 191 has dup fanin 188. |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (2999.11 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 178 ( 29.8 %) Cap = 7.8 ff ( 5.3 %) Area = 1318.76 ( 70.2 %) Delay = 2784.84 ps ( 18.5 %) |
| ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 6.1 -4.2 ps S = 17.8 ps Cin = 0.0 ff Cout = 4.6 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 43 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 29.1 -3.2 ps S = 24.5 ps Cin = 4.5 ff Cout = 3.7 ff Cmax = 331.4 ff G = 79 |
| ABC: Path 2 -- 44 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 161.4 -32.2 ps S = 130.1 ps Cin = 2.1 ff Cout = 10.2 ff Cmax = 130.0 ff G = 464 |
| ABC: Path 3 -- 45 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 342.0 -79.3 ps S = 156.8 ps Cin = 2.1 ff Cout = 12.5 ff Cmax = 130.0 ff G = 567 |
| ABC: Path 4 -- 93 : 4 4 sky130_fd_sc_hd__or4_2 A = 8.76 Df = 953.4 -397.3 ps S = 118.8 ps Cin = 1.5 ff Cout = 7.7 ff Cmax = 310.4 ff G = 485 |
| ABC: Path 5 -- 144 : 2 3 sky130_fd_sc_hd__or2b_2 A = 8.76 Df =1150.0 -293.8 ps S = 61.4 ps Cin = 1.6 ff Cout = 6.0 ff Cmax = 312.2 ff G = 366 |
| ABC: Path 6 -- 148 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1422.7 -115.9 ps S = 52.8 ps Cin = 1.7 ff Cout = 6.1 ff Cmax = 300.3 ff G = 339 |
| ABC: Path 7 -- 149 : 4 2 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1675.8 -10.2 ps S = 66.7 ps Cin = 1.7 ff Cout = 9.2 ff Cmax = 300.3 ff G = 512 |
| ABC: Path 8 -- 155 : 2 4 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =1814.6 -99.2 ps S = 117.1 ps Cin = 4.4 ff Cout = 8.2 ff Cmax = 141.9 ff G = 177 |
| ABC: Path 9 -- 160 : 2 1 sky130_fd_sc_hd__or2_2 A = 6.26 Df =1993.7 -58.0 ps S = 52.2 ps Cin = 1.5 ff Cout = 2.5 ff Cmax = 299.4 ff G = 164 |
| ABC: Path 10 -- 163 : 5 3 sky130_fd_sc_hd__o221a_2 A = 11.26 Df =2276.8 -12.9 ps S = 71.9 ps Cin = 2.3 ff Cout = 8.5 ff Cmax = 281.1 ff G = 347 |
| ABC: Path 11 -- 178 : 5 2 sky130_fd_sc_hd__o221ai_2 A = 15.01 Df =2454.9 -88.1 ps S = 145.3 ps Cin = 4.5 ff Cout = 3.7 ff Cmax = 128.2 ff G = 77 |
| ABC: Path 12 -- 179 : 4 1 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =2784.8 -96.0 ps S = 106.5 ps Cin = 1.7 ff Cout = 17.6 ff Cmax = 300.3 ff G = 1025 |
| ABC: Start-point = pi1 (\a [3]). End-point = po7 (\c [12]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 178 edge = 454 area =1318.75 delay =14.00 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 67.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 22 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 31 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 16 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2a_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 29 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 3 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 68. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 69. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 70. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 71. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 72. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 73. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 74. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 167 |
| Number of wire bits: 196 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 180 |
| sky130_fd_sc_hd__a21oi_2 1 |
| sky130_fd_sc_hd__a2bb2o_2 21 |
| sky130_fd_sc_hd__a2bb2oi_2 2 |
| sky130_fd_sc_hd__a31o_2 3 |
| sky130_fd_sc_hd__and2_2 2 |
| sky130_fd_sc_hd__buf_1 22 |
| sky130_fd_sc_hd__inv_2 31 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__nand2_2 9 |
| sky130_fd_sc_hd__nor2_2 10 |
| sky130_fd_sc_hd__o21a_2 1 |
| sky130_fd_sc_hd__o21ai_2 5 |
| sky130_fd_sc_hd__o221a_2 11 |
| sky130_fd_sc_hd__o221ai_2 4 |
| sky130_fd_sc_hd__o22a_2 16 |
| sky130_fd_sc_hd__o2bb2a_2 3 |
| sky130_fd_sc_hd__o32a_2 1 |
| sky130_fd_sc_hd__or2_2 29 |
| sky130_fd_sc_hd__or2b_2 4 |
| sky130_fd_sc_hd__or4_2 3 |
| |
| Chip area for module '\axmul': 1341.286400 |
| |
| 75. Executing Verilog backend. |
| Dumping module `\axmul'. |
| [INFO]: ABC: WireLoad : S_6 |
| |
| 76. Executing ABC pass (technology mapping using ABC). |
| |
| 76.1. Extracting gate netlist of module `\axmul' to `<abc-temp-dir>/input.blif'.. |
| Extracted 262 gates and 278 wires to a netlist network with 16 inputs and 19 outputs. |
| |
| 76.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_lib -w /openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.06 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openLANE_flow/designs/axmul/runs/run1/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.09 sec |
| ABC: Memory = 7.77 MB. Time = 0.09 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /openLANE_flow/designs/axmul/runs/run1/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + retime -D -D 10000.0 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: Warning: The choice nodes in the original AIG are removed by strashing. |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 10000.0 |
| ABC: + buffer -N 5 -S 1000.0 |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 64 has dup fanin 61. |
| ABC: Node 64 has dup fanin 63. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 65 has dup fanin 60. |
| ABC: Node 65 has dup fanin 64. |
| ABC: Node 76 has dup fanin 72. |
| ABC: Node 76 has dup fanin 75. |
| ABC: Node 76 has dup fanin 72. |
| ABC: Node 76 has dup fanin 75. |
| ABC: Node 84 has dup fanin 74. |
| ABC: Node 84 has dup fanin 83. |
| ABC: Node 84 has dup fanin 74. |
| ABC: Node 84 has dup fanin 83. |
| ABC: Node 86 has dup fanin 69. |
| ABC: Node 86 has dup fanin 76. |
| ABC: Node 86 has dup fanin 69. |
| ABC: Node 86 has dup fanin 76. |
| ABC: Node 95 has dup fanin 89. |
| ABC: Node 95 has dup fanin 91. |
| ABC: Node 95 has dup fanin 89. |
| ABC: Node 95 has dup fanin 91. |
| ABC: Node 97 has dup fanin 66. |
| ABC: Node 97 has dup fanin 84. |
| ABC: Node 97 has dup fanin 66. |
| ABC: Node 97 has dup fanin 84. |
| ABC: Node 107 has dup fanin 104. |
| ABC: Node 107 has dup fanin 106. |
| ABC: Node 107 has dup fanin 104. |
| ABC: Node 107 has dup fanin 106. |
| ABC: Node 114 has dup fanin 112. |
| ABC: Node 114 has dup fanin 113. |
| ABC: Node 114 has dup fanin 112. |
| ABC: Node 114 has dup fanin 113. |
| ABC: Node 117 has dup fanin 114. |
| ABC: Node 117 has dup fanin 116. |
| ABC: Node 117 has dup fanin 114. |
| ABC: Node 117 has dup fanin 116. |
| ABC: Node 120 has dup fanin 107. |
| ABC: Node 120 has dup fanin 109. |
| ABC: Node 120 has dup fanin 107. |
| ABC: Node 120 has dup fanin 109. |
| ABC: Node 125 has dup fanin 122. |
| ABC: Node 125 has dup fanin 124. |
| ABC: Node 125 has dup fanin 122. |
| ABC: Node 125 has dup fanin 124. |
| ABC: Node 134 has dup fanin 125. |
| ABC: Node 134 has dup fanin 127. |
| ABC: Node 134 has dup fanin 125. |
| ABC: Node 134 has dup fanin 127. |
| ABC: Node 141 has dup fanin 93. |
| ABC: Node 141 has dup fanin 95. |
| ABC: Node 141 has dup fanin 93. |
| ABC: Node 141 has dup fanin 95. |
| ABC: Node 144 has dup fanin 142. |
| ABC: Node 144 has dup fanin 143. |
| ABC: Node 144 has dup fanin 142. |
| ABC: Node 144 has dup fanin 143. |
| ABC: Node 148 has dup fanin 78. |
| ABC: Node 148 has dup fanin 144. |
| ABC: Node 148 has dup fanin 78. |
| ABC: Node 148 has dup fanin 144. |
| ABC: Node 161 has dup fanin 81. |
| ABC: Node 161 has dup fanin 160. |
| ABC: Node 161 has dup fanin 81. |
| ABC: Node 161 has dup fanin 160. |
| ABC: Node 167 has dup fanin 103. |
| ABC: Node 167 has dup fanin 166. |
| ABC: Node 167 has dup fanin 103. |
| ABC: Node 167 has dup fanin 166. |
| ABC: Node 169 has dup fanin 100. |
| ABC: Node 169 has dup fanin 168. |
| ABC: Node 169 has dup fanin 100. |
| ABC: Node 169 has dup fanin 168. |
| ABC: Node 175 has dup fanin 173. |
| ABC: Node 175 has dup fanin 174. |
| ABC: Node 175 has dup fanin 173. |
| ABC: Node 175 has dup fanin 174. |
| ABC: Node 177 has dup fanin 139. |
| ABC: Node 177 has dup fanin 176. |
| ABC: Node 177 has dup fanin 139. |
| ABC: Node 177 has dup fanin 176. |
| ABC: Node 179 has dup fanin 137. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 179 has dup fanin 137. |
| ABC: Node 179 has dup fanin 178. |
| ABC: Node 185 has dup fanin 79. |
| ABC: Node 185 has dup fanin 79. |
| ABC: + upsize -D 10000.0 |
| ABC: Current delay (3354.85 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 10000.0 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 170 ( 27.1 %) Cap = 7.9 ff ( 4.6 %) Area = 1293.74 ( 72.9 %) Delay = 2856.95 ps ( 21.2 %) |
| ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 6.1 -4.2 ps S = 17.8 ps Cin = 0.0 ff Cout = 4.6 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 42 : 1 4 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 42.5 -10.2 ps S = 42.9 ps Cin = 4.5 ff Cout = 7.8 ff Cmax = 331.4 ff G = 167 |
| ABC: Path 2 -- 125 : 2 4 sky130_fd_sc_hd__or2_2 A = 6.26 Df = 329.9 -163.6 ps S = 67.8 ps Cin = 1.5 ff Cout = 7.4 ff Cmax = 299.4 ff G = 490 |
| ABC: Path 3 -- 126 : 3 4 sky130_fd_sc_hd__or3_2 A = 7.51 Df = 764.4 -480.3 ps S = 92.7 ps Cin = 1.5 ff Cout = 7.7 ff Cmax = 310.4 ff G = 479 |
| ABC: Path 4 -- 149 : 2 3 sky130_fd_sc_hd__or2b_2 A = 8.76 Df = 949.3 -365.7 ps S = 61.4 ps Cin = 1.6 ff Cout = 6.0 ff Cmax = 312.2 ff G = 366 |
| ABC: Path 5 -- 152 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1222.0 -116.6 ps S = 52.5 ps Cin = 1.7 ff Cout = 6.0 ff Cmax = 300.3 ff G = 335 |
| ABC: Path 6 -- 159 : 4 2 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1488.4 -19.0 ps S = 52.7 ps Cin = 1.7 ff Cout = 6.1 ff Cmax = 300.3 ff G = 338 |
| ABC: Path 7 -- 184 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =1549.1 -34.7 ps S = 37.6 ps Cin = 4.4 ff Cout = 3.0 ff Cmax = 295.7 ff G = 65 |
| ABC: Path 8 -- 185 : 2 1 sky130_fd_sc_hd__or2_2 A = 6.26 Df =1875.5 -104.2 ps S = 52.3 ps Cin = 1.5 ff Cout = 2.4 ff Cmax = 299.4 ff G = 161 |
| ABC: Path 9 -- 186 : 4 2 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =2016.1 -14.6 ps S = 45.5 ps Cin = 2.4 ff Cout = 4.1 ff Cmax = 271.9 ff G = 164 |
| ABC: Path 10 -- 198 : 3 1 sky130_fd_sc_hd__o21a_2 A = 8.76 Df =2182.2 -64.4 ps S = 32.0 ps Cin = 2.4 ff Cout = 2.4 ff Cmax = 294.8 ff G = 96 |
| ABC: Path 11 -- 200 : 5 2 sky130_fd_sc_hd__o32a_2 A = 11.26 Df =2550.3 -282.9 ps S = 65.0 ps Cin = 2.3 ff Cout = 7.2 ff Cmax = 300.3 ff G = 296 |
| ABC: Path 12 -- 205 : 4 1 sky130_fd_sc_hd__a22o_2 A = 10.01 Df =2857.0 -7.5 ps S = 105.5 ps Cin = 2.3 ff Cout = 17.6 ff Cmax = 301.2 ff G = 751 |
| ABC: Start-point = pi1 (\a [3]). End-point = po18 (\c [13]). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 16/ 19 lat = 0 nd = 170 edge = 451 area =1293.74 delay =14.00 lev = 14 |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 76.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a31oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a32o_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a41o_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 16 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 30 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 19 |
| ABC RESULTS: sky130_fd_sc_hd__o31a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o41a_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 29 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 1 |
| ABC RESULTS: internal signals: 243 |
| ABC RESULTS: input signals: 16 |
| ABC RESULTS: output signals: 19 |
| Removing temp directory. |
| |
| 77. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 78. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 79. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 80. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \axmul.. |
| Removed 0 unused cells and 287 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 81. Executing INSBUF pass (insert buffer cells for connected wires). |
| |
| 82. Executing CHECK pass (checking for obvious problems). |
| Checking module axmul... |
| Warning: Wire axmul.\c [15] is used but has no driver. |
| Warning: Wire axmul.\c [14] is used but has no driver. |
| Warning: Wire axmul.\c [13] is used but has no driver. |
| Warning: Wire axmul.\c [12] is used but has no driver. |
| Warning: Wire axmul.\c [11] is used but has no driver. |
| Warning: Wire axmul.\c [10] is used but has no driver. |
| Warning: Wire axmul.\c [9] is used but has no driver. |
| Warning: Wire axmul.\c [8] is used but has no driver. |
| Warning: Wire axmul.\c [7] is used but has no driver. |
| Warning: Wire axmul.\c [6] is used but has no driver. |
| Warning: Wire axmul.\c [5] is used but has no driver. |
| Warning: Wire axmul.\c [4] is used but has no driver. |
| Warning: Wire axmul.\c [3] is used but has no driver. |
| Warning: Wire axmul.\c [2] is used but has no driver. |
| Warning: Wire axmul.\c [1] is used but has no driver. |
| Warning: Wire axmul.\c [0] is used but has no driver. |
| Found and reported 16 problems. |
| |
| 83. Printing statistics. |
| |
| === axmul === |
| |
| Number of wires: 159 |
| Number of wire bits: 188 |
| Number of public wires: 3 |
| Number of public wire bits: 32 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 172 |
| sky130_fd_sc_hd__a21o_2 1 |
| sky130_fd_sc_hd__a21oi_2 1 |
| sky130_fd_sc_hd__a22o_2 1 |
| sky130_fd_sc_hd__a2bb2o_2 21 |
| sky130_fd_sc_hd__a2bb2oi_2 1 |
| sky130_fd_sc_hd__a31o_2 2 |
| sky130_fd_sc_hd__a31oi_2 1 |
| sky130_fd_sc_hd__a32o_2 2 |
| sky130_fd_sc_hd__a41o_2 3 |
| sky130_fd_sc_hd__and2_2 5 |
| sky130_fd_sc_hd__buf_1 16 |
| sky130_fd_sc_hd__inv_2 30 |
| sky130_fd_sc_hd__mux2_1 2 |
| sky130_fd_sc_hd__nand2_2 5 |
| sky130_fd_sc_hd__nor2_2 6 |
| sky130_fd_sc_hd__o21a_2 2 |
| sky130_fd_sc_hd__o21ai_2 6 |
| sky130_fd_sc_hd__o221a_2 9 |
| sky130_fd_sc_hd__o221ai_2 2 |
| sky130_fd_sc_hd__o22a_2 19 |
| sky130_fd_sc_hd__o31a_2 1 |
| sky130_fd_sc_hd__o32a_2 1 |
| sky130_fd_sc_hd__o41a_2 1 |
| sky130_fd_sc_hd__or2_2 29 |
| sky130_fd_sc_hd__or2b_2 4 |
| sky130_fd_sc_hd__or3_2 1 |
| |
| Chip area for module '\axmul': 1316.262400 |
| |
| 84. Executing Verilog backend. |
| Dumping module `\axmul'. |
| |
| Warnings: 16 unique messages, 112 total |
| End of script. Logfile hash: 5fba6fd1a0, CPU: user 3.71s system 0.07s, MEM: 45.31 MB peak |
| Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) |
| Time spent: 54% 8x abc (4 sec), 34% 10x stat (2 sec), ... |
