sx_openlane_runs/logs/placement/8-resizer.log

OpenROAD 1 fb8ae93b6c7a5eb0e6fac83360a8a48d76c41885
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef at line 68110.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-replace.def
[INFO ODB-0128] Design: axmul
[INFO ODB-0130]     Created 34 pins.
[INFO ODB-0131]     Created 7878 components and 17600 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 16960 connections.
[INFO ODB-0133]     Created 194 nets and 640 connections.
[INFO ODB-0134] Finished DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-replace.def
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO RSZ-0027] Inserted 16 input buffers.
[INFO RSZ-0028] Inserted 16 output buffers.
[INFO RSZ-0058] Using max wire length 4269um.
[INFO RSZ-0039] Resized 162 instances.
Placement Analysis
---------------------------------
total displacement       2105.1 u
average displacement        0.3 u
max displacement           31.9 u
original HPWL           19041.1 u
legalized HPWL          21512.4 u
delta HPWL                   13 %

[INFO DPL-0020] Mirrored 111 instances
[INFO DPL-0021] HPWL before           21512.4 u
[INFO DPL-0022] HPWL after            21300.9 u
[INFO DPL-0023] HPWL delta               -1.0 %