| OpenROAD 1 fb8ae93b6c7a5eb0e6fac83360a8a48d76c41885 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef |
| [WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later. |
| The LEF parser will ignore this statement. |
| To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef at line 68110. |
| |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 441 library cells |
| [INFO ODB-0226] Finished LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef |
| [INFO ODB-0127] Reading DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def |
| [INFO ODB-0128] Design: axmul |
| [INFO ODB-0130] Created 34 pins. |
| [INFO ODB-0131] Created 7910 components and 17792 component-terminals. |
| [INFO ODB-0132] Created 2 special nets and 17088 connections. |
| [INFO ODB-0133] Created 226 nets and 704 connections. |
| [INFO ODB-0134] Finished DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def |
| INFO: CTS was skipped, reading base sdc file. |
| create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) |
| set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| puts "\[INFO\]: Setting output delay to: $output_delay_value" |
| [INFO]: Setting output delay to: 2.0 |
| puts "\[INFO\]: Setting input delay to: $input_delay_value" |
| [INFO]: Setting input delay to: 2.0 |
| set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] |
| set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] |
| #set rst_indx [lsearch [all_inputs] [get_port resetn]] |
| set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] |
| #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] |
| set all_inputs_wo_clk_rst $all_inputs_wo_clk |
| # correct resetn |
| set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst |
| #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} |
| set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] |
| # TODO set this as parameter |
| set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] |
| set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] |
| puts "\[INFO\]: Setting load to: $cap_load" |
| [INFO]: Setting load to: 0.01765 |
| set_load $cap_load [all_outputs] |
| [INFO GRT-0020] Min routing layer: li1 |
| [INFO GRT-0021] Max routing layer: met5 |
| [INFO GRT-0022] Global adjustment: 0% |
| [INFO GRT-0023] Grid origin: (0, 0) |
| [WARNING GRT-0043] No OR_DEFAULT vias defined. |
| [INFO GRT-0224] Chose via L1M1_PR as default. |
| [INFO GRT-0224] Chose via M1M2_PR as default. |
| [INFO GRT-0224] Chose via M2M3_PR as default. |
| [INFO GRT-0224] Chose via M3M4_PR as default. |
| [INFO GRT-0224] Chose via M4M5_PR as default. |
| [INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400 |
| [INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400 |
| [INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500 |
| [INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150 |
| [INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400 |
| [INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100 |
| [INFO GRT-0003] Macros: 0 |
| [INFO GRT-0004] Blockages: 34972 |
| [INFO GRT-0019] Found 0 clock nets. |
| [INFO GRT-0001] Minimum degree: 2 |
| [INFO GRT-0002] Maximum degree: 6 |
| [INFO GRT-0017] Processing 36468 blockages on layer li1. |
| [INFO GRT-0017] Processing 16078 blockages on layer met1. |
| [INFO GRT-0017] Processing 12 blockages on layer met4. |
| [INFO GRT-0017] Processing 8 blockages on layer met5. |
| |
| [INFO GRT-0053] Routing resources analysis: |
| Routing Original Derated Resource |
| Layer Direction Resources Resources Reduction (%) |
| --------------------------------------------------------------- |
| li1 Vertical 167700 165339 1.41% |
| met1 Horizontal 223600 195947 12.37% |
| met2 Vertical 167700 166175 0.91% |
| met3 Horizontal 111800 111972 -0.15% |
| met4 Vertical 67080 65632 2.16% |
| met5 Horizontal 22360 22188 0.77% |
| --------------------------------------------------------------- |
| |
| [INFO GRT-0111] Final number of vias: 591 |
| [INFO GRT-0112] Final usage 3D: 4909 |
| |
| [INFO GRT-0096] Final congestion report: |
| Layer Resource Demand Usage (%) Max H / Max V / Total Overflow |
| --------------------------------------------------------------------------------------- |
| li1 165339 1316 0.80% 0 / 0 / 0 |
| met1 195947 1697 0.87% 0 / 0 / 0 |
| met2 166175 123 0.07% 0 / 0 / 0 |
| met3 111972 0 0.00% 0 / 0 / 0 |
| met4 65632 0 0.00% 0 / 0 / 0 |
| met5 22188 0 0.00% 0 / 0 / 0 |
| --------------------------------------------------------------------------------------- |
| Total 727253 3136 0.43% 0 / 0 / 0 |
| |
| [INFO GRT-0018] Total wirelength: 26703 um |
| [WARNING RSZ-0021] no estimated parasitics. Using wire load models. |
| [INFO RSZ-0033] No hold violations found. |
| Placement Analysis |
| --------------------------------- |
| total displacement 0.0 u |
| average displacement 0.0 u |
| max displacement 0.0 u |
| original HPWL 21300.9 u |
| legalized HPWL 21512.4 u |
| delta HPWL 1 % |
| |
| [INFO DPL-0020] Mirrored 111 instances |
| [INFO DPL-0021] HPWL before 21512.4 u |
| [INFO DPL-0022] HPWL after 21300.9 u |
| [INFO DPL-0023] HPWL delta -1.0 % |
