| [INFO]: Current run directory is /openLANE_flow/designs/axmul/runs/run1 |
| [INFO]: Preparing LEF Files |
| [INFO]: Extracting the number of available metal layers from /soft/ProgramFiles/caravel_user_project/openlane_caravel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef |
| [INFO]: The number of available metal layers is 6 |
| [INFO]: The available metal layers are li1 met1 met2 met3 met4 met5 |
| [INFO]: Merging LEF Files... |
| [INFO]: Trimming Liberty... |
| [INFO]: Generating Exclude List... |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparation complete |
| [INFO]: Running Synthesis... |
| [INFO]: current step index: 1 |
| [INFO]: Changing netlist from 0 to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 2 |
| [INFO]: Synthesis was successful |
| [INFO]: Running Floorplanning... |
| [INFO]: Running Initial Floorplanning... |
| [INFO]: current step index: 3 |
| [INFO]: Core area width: 888.96 |
| [INFO]: Core area height: 578.24 |
| [INFO]: Final Vertical PDN Offset: 16.32 |
| [INFO]: Final Horizontal PDN Offset: 16.65 |
| [INFO]: Final Vertical PDN Pitch: 153.6 |
| [INFO]: Final Horizontal PDN Pitch: 153.18 |
| [INFO]: Changing layout from 0 to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/3-verilog2def_openroad.def |
| [INFO]: Running IO Placement... |
| [INFO]: current step index: 4 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/3-verilog2def_openroad.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/4-ioPlacer.def |
| [INFO]: Running Tap/Decap Insertion... |
| [INFO]: current step index: 5 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/4-ioPlacer.def to /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def |
| [INFO]: Power planning the following nets |
| [INFO]: Power: VPWR |
| [INFO]: Ground: VGND |
| [INFO]: Generating PDN... |
| [INFO]: current step index: 6 |
| [INFO]: current step index: 7 |
| [INFO]: PDN generation was successful. |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/6-pdn.def |
| [INFO]: Running Placement... |
| [INFO]: Running Global Placement... |
| [INFO]: current step index: 8 |
| [INFO]: Global placement was successful |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/6-pdn.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-replace.def |
| [INFO]: Running Resizer Design Optimizations... |
| [INFO]: Generating Exclude List... |
| [INFO]: Creating ::env(DONT_USE_CELLS)... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-replace.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-resizer.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 9 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 10 |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 11 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/8-resizer.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: current step index: 12 |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 13 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 14 |
| [INFO]: Routing... |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/14-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 15 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 16 |
| [INFO]: Running Diode Insertion... |
| [INFO]: current step index: 17 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/14-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/17-diodes.def |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 18 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/17-diodes.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 19 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v |
| [INFO]: Running Fill Insertion... |
| [INFO]: current step index: 20 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/20-addspacers.def |
| [INFO]: Obstructions will be added over the whole die area: met5 0 0 900 600 |
| [INFO]: Adding routing obstructions... |
| [WARNING]: Specifying a routing obstruction is now done using the coordinates |
| [WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y). |
| [INFO]: Obstructions added over met5 0 0 900 600 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/20-addspacers.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/20-addspacers.obs.def |
| [INFO]: Running Global Routing... |
| [INFO]: current step index: 21 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/20-addspacers.obs.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.def |
| [INFO]: Changing layout from 0 to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.guide |
| [INFO]: Current Def is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.def |
| [INFO]: Current Guide is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.guide |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 22 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v |
| [INFO]: Running Detailed Routing... |
| [INFO]: current step index: 23 |
| [INFO]: No DRC violations after detailed routing. |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.def to /openLANE_flow/designs/axmul/runs/run1/results/routing/22-axmul.def |
| [INFO]: Running SPEF Extraction... |
| [INFO]: current step index: 24 |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 25 |
| [INFO]: Calculating Runtime From the Start... |
| [INFO]: Routing completed for axmul/29-10_08-35 in 0h1m39s |
| [INFO]: Writing Powered Verilog... |
| [INFO]: current step index: 26 |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 27 |
| [INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is. |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v to /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs.powered.v |
| [INFO]: Running Magic to generate various views... |
| [INFO]: Streaming out GDS II... |
| [INFO]: current step index: 28 |
| [INFO]: current step index: 29 |
| [INFO]: current step index: 30 |
| [INFO]: current step index: 31 |
| [INFO]: Running Klayout to re-generate GDS-II... |
| [INFO]: Streaming out GDS II... |
| [INFO]: current step index: 32 |
| [INFO]: Back-up GDS-II streamed out. |
| [INFO]: Running XOR on the layouts using Klayout... |
| [INFO]: current step index: 33 |
| [INFO]: current step index: 34 |
| [INFO]: Klayout XOR Complete |
| [INFO]: Running Magic Spice Export from LEF... |
| [INFO]: current step index: 35 |
| [INFO]: No Illegal overlaps detected during extraction. |
| [INFO]: Running LEF LVS... |
| [INFO]: /openLANE_flow/designs/axmul/runs/run1/results/magic/axmul.spice against /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs.powered.v |
| [INFO]: current step index: 36 |
| [INFO]: No LVS mismatches. |
| [INFO]: Running Magic DRC... |
| [INFO]: current step index: 37 |
| [INFO]: Converting Magic DRC Violations to Magic Readable Format... |
| [INFO]: Converting Magic DRC Violations to Klayout XML Database... |
| [INFO]: Converting DRC Violations to RDB Format... |
| [INFO]: Converted DRC Violations to RDB Format |
| [INFO]: No DRC violations after GDS streaming out. |
| [INFO]: Running Antenna Checks... |
| [INFO]: Running OpenROAD Antenna Rule Checker... |
| [INFO]: current step index: 38 |
| [INFO]: current step index: 39 |
| [INFO]: Running CVC |
| [INFO]: current step index: 40 |
| [INFO]: Calculating Runtime From the Start... |
| [INFO]: flow completed for axmul/29-10_08-35 in 0h4m17s |
| [INFO]: Saving Runtime Environment |
| [INFO]: Generating Final Summary Report... |
| [INFO]: Design Name: axmul |
| Run Directory: /openLANE_flow/designs/axmul/runs/run1 |
| ---------------------------------------- |
| |
| Magic DRC Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/reports/magic/37-magic.drc |
| Total Magic DRC violations is 0 |
| ---------------------------------------- |
| |
| LVS Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs_parsed.lef.log |
| LVS reports no net, device, pin, or property mismatches. |
| Total errors = 0 |
| ---------------------------------------- |
| |
| Antenna Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/reports/routing/39-antenna.rpt |
| Number of pins violated: 0 |
| Number of nets violated: 0 |
| [INFO]: check full report here: /openLANE_flow/designs/axmul/runs/run1/reports/final_summary_report.csv |
| [SUCCESS]: Flow Completed Without Fatal Errors. |
| [WARNING]: A run for axmul with tag 'run1' already exists. Pass -overwrite option to overwrite it |
| [INFO]: Now you can run commands that pick up where 'run1' left off |
| [INFO]: Current run directory is /openLANE_flow/designs/axmul/runs/run1 |
| [INFO]: Sourcing /openLANE_flow/designs/axmul/runs/run1/config.tcl |
| Any changes to the DESIGN config file will NOT be applied |
| [INFO]: Current DEF: /openLANE_flow/designs/axmul/runs/run1/results/routing/22-axmul.def. |
| [INFO]: Use 'set_def file_name.def' if you'd like to change it. |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparation complete |
| [INFO]: Calculating Runtime From the Start... |
| [INFO]: flow completed for axmul/29-10_08-35 in 0h8m29s |
| [INFO]: Saving Runtime Environment |
| [INFO]: Generating Final Summary Report... |
| [INFO]: Design Name: axmul |
| Run Directory: /openLANE_flow/designs/axmul/runs/run1 |
| ---------------------------------------- |
| |
| Magic DRC Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/reports/magic/37-magic.drc |
| Total Magic DRC violations is 0 |
| ---------------------------------------- |
| |
| LVS Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs_parsed.lef.log |
| LVS reports no net, device, pin, or property mismatches. |
| Total errors = 0 |
| ---------------------------------------- |
| |
| Antenna Summary: |
| Source: /openLANE_flow/designs/axmul/runs/run1/reports/routing/39-antenna.rpt |
| Number of pins violated: 0 |
| Number of nets violated: 0 |
| [INFO]: check full report here: /openLANE_flow/designs/axmul/runs/run1/reports/final_summary_report.csv |
| [SUCCESS]: Flow Completed Without Fatal Errors. |
| [WARNING]: A run for axmul with tag 'run1' already exists. Pass -overwrite option to overwrite it |
| [INFO]: Now you can run commands that pick up where 'run1' left off |
| [INFO]: Current run directory is /openLANE_flow/designs/axmul/runs/run1 |
| [INFO]: Sourcing /openLANE_flow/designs/axmul/runs/run1/config.tcl |
| Any changes to the DESIGN config file will NOT be applied |
| [INFO]: Current DEF: /openLANE_flow/designs/axmul/runs/run1/results/routing/22-axmul.def. |
| [INFO]: Use 'set_def file_name.def' if you'd like to change it. |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparation complete |
| [INFO]: Running Synthesis... |
| [WARNING]: A netlist at /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v already exists... |
| [WARNING]: Skipping synthesis |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs.powered.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 41 |
| [INFO]: Synthesis was successful |
| [INFO]: Running Floorplanning... |
| [INFO]: Running Initial Floorplanning... |
| [INFO]: current step index: 42 |
| [INFO]: Core area width: 888.96 |
| [INFO]: Core area height: 578.24 |
| [INFO]: Final Vertical PDN Offset: 19.62 |
| [INFO]: Final Horizontal PDN Offset: 19.95 |
| [INFO]: Final Vertical PDN Pitch: 153.6 |
| [INFO]: Final Horizontal PDN Pitch: 153.18 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/routing/22-axmul.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/42-verilog2def_openroad.def |
| [INFO]: Running IO Placement... |
| [INFO]: current step index: 43 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/42-verilog2def_openroad.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/43-ioPlacer.def |
| [INFO]: Running Tap/Decap Insertion... |
| [INFO]: current step index: 44 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/43-ioPlacer.def to /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def |
| [INFO]: Power planning the following nets |
| [INFO]: Power: VPWR |
| [INFO]: Ground: VGND |
| [WARNING]: All internal macros will not be connected to power. |
| [INFO]: Generating PDN... |
| [INFO]: current step index: 45 |
| [INFO]: current step index: 46 |
| [INFO]: PDN generation was successful. |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/45-pdn.def |
| [INFO]: Running Placement... |
| [INFO]: Running Global Placement... |
| [INFO]: current step index: 47 |
| [INFO]: Global placement was successful |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/6-pdn.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/47-replace.def |
| [INFO]: Running Resizer Design Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/47-replace.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/47-resizer.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 48 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 49 |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 50 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/47-resizer.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: current step index: 51 |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/51-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 52 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 53 |
| [INFO]: Routing... |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/53-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 54 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 55 |
| [INFO]: Running Diode Insertion... |
| [INFO]: current step index: 56 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/53-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/56-diodes.def |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 57 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/56-diodes.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 58 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v |
| [INFO]: Running Fill Insertion... |
| [INFO]: current step index: 59 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.def |
| [INFO]: Adding routing obstructions... |
| [WARNING]: Specifying a routing obstruction is now done using the coordinates |
| [WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y). |
| [INFO]: Obstructions added over met5 0 0 900 600 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.obs.def |
| [INFO]: Obstructions will be added over the whole die area: met5 0 0 900 600 |
| [INFO]: Adding routing obstructions... |
| [WARNING]: Specifying a routing obstruction is now done using the coordinates |
| [WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y). |
| [INFO]: Obstructions added over met5 0 0 900 600 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.obs.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.obs.obs.def |
| [INFO]: Running Global Routing... |
| [INFO]: current step index: 60 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/59-addspacers.obs.obs.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/21-fastroute.guide to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.guide |
| [INFO]: Current Def is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.def |
| [INFO]: Current Guide is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.guide |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 61 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v |
| [INFO]: Running Detailed Routing... |
| [INFO]: current step index: 62 |
| [INFO]: No DRC violations after detailed routing. |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.def to /openLANE_flow/designs/axmul/runs/run1/results/routing/61-axmul.def |
| [INFO]: Running SPEF Extraction... |
| [INFO]: current step index: 63 |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 64 |
| [INFO]: Calculating Runtime From the Start... |
| [INFO]: Routing completed for axmul/29-10_08-35 in 0h10m59s |
| [INFO]: Writing Powered Verilog... |
| [INFO]: current step index: 65 |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 66 |
| [INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is. |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v to /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs.powered.v |
| [INFO]: Running Magic to generate various views... |
| [INFO]: Streaming out GDS II... |
| [INFO]: current step index: 67 |
| [INFO]: current step index: 68 |
| [INFO]: current step index: 69 |
| [INFO]: current step index: 70 |
| [INFO]: Running Klayout to re-generate GDS-II... |
| [INFO]: Streaming out GDS II... |
| [INFO]: current step index: 71 |
| [INFO]: Back-up GDS-II streamed out. |
| [INFO]: Running XOR on the layouts using Klayout... |
| [INFO]: current step index: 72 |
| [INFO]: current step index: 73 |
| [WARNING]: A run for axmul with tag 'run1' already exists. Pass -overwrite option to overwrite it |
| [INFO]: Now you can run commands that pick up where 'run1' left off |
| [INFO]: Current run directory is /openLANE_flow/designs/axmul/runs/run1 |
| [INFO]: Sourcing /openLANE_flow/designs/axmul/runs/run1/config.tcl |
| Any changes to the DESIGN config file will NOT be applied |
| [INFO]: Current DEF: /openLANE_flow/designs/axmul/runs/run1/results/routing/61-axmul.def. |
| [INFO]: Use 'set_def file_name.def' if you'd like to change it. |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparation complete |
| [INFO]: Running Synthesis... |
| [WARNING]: A netlist at /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v already exists... |
| [WARNING]: Skipping synthesis |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/lvs/axmul.lvs.powered.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 74 |
| [INFO]: Synthesis was successful |
| [INFO]: Running Floorplanning... |
| [INFO]: Running Initial Floorplanning... |
| [INFO]: current step index: 75 |
| [INFO]: Core area width: 888.96 |
| [INFO]: Core area height: 578.24 |
| [INFO]: Final Vertical PDN Offset: 19.62 |
| [INFO]: Final Horizontal PDN Offset: 19.95 |
| [INFO]: Final Vertical PDN Pitch: 153.6 |
| [INFO]: Final Horizontal PDN Pitch: 153.18 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/routing/61-axmul.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/75-verilog2def_openroad.def |
| [INFO]: Running IO Placement... |
| [INFO]: current step index: 76 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/75-verilog2def_openroad.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/76-ioPlacer.def |
| [INFO]: Running Tap/Decap Insertion... |
| [INFO]: current step index: 77 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/76-ioPlacer.def to /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def |
| [INFO]: Power planning the following nets |
| [INFO]: Power: VPWR |
| [INFO]: Ground: VGND |
| [WARNING]: All internal macros will not be connected to power. |
| [INFO]: Generating PDN... |
| [INFO]: current step index: 78 |
| [INFO]: current step index: 79 |
| [INFO]: PDN generation was successful. |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/floorplan/axmul.floorplan.def to /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/78-pdn.def |
| [INFO]: Running Placement... |
| [INFO]: Running Global Placement... |
| [INFO]: current step index: 80 |
| [INFO]: Global placement was successful |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/6-pdn.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/80-replace.def |
| [INFO]: Running Resizer Design Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/80-replace.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/80-resizer.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 81 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 82 |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 83 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/80-resizer.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: current step index: 84 |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/84-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 85 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 86 |
| [INFO]: Routing... |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/12-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/86-resizer_timing.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 87 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: current step index: 88 |
| [INFO]: Running Diode Insertion... |
| [INFO]: current step index: 89 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/86-resizer_timing.def to /openLANE_flow/designs/axmul/runs/run1/tmp/placement/89-diodes.def |
| [INFO]: Running Detailed Placement... |
| [INFO]: current step index: 90 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/placement/89-diodes.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 91 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_optimized.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v |
| [INFO]: Running Fill Insertion... |
| [INFO]: current step index: 92 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/results/placement/axmul.placement.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.def |
| [INFO]: Adding routing obstructions... |
| [WARNING]: Specifying a routing obstruction is now done using the coordinates |
| [WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y). |
| [INFO]: Obstructions added over met5 0 0 900 600 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.def |
| [INFO]: Obstructions will be added over the whole die area: met5 0 0 900 600 |
| [INFO]: Adding routing obstructions... |
| [WARNING]: Specifying a routing obstruction is now done using the coordinates |
| [WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y). |
| [INFO]: Obstructions added over met5 0 0 900 600 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.obs.def |
| [INFO]: Running Global Routing... |
| [INFO]: current step index: 93 |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.obs.def to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/93-fastroute.def |
| [INFO]: Changing layout from /openLANE_flow/designs/axmul/runs/run1/tmp/routing/60-fastroute.guide to /openLANE_flow/designs/axmul/runs/run1/tmp/routing/93-fastroute.guide |
| [INFO]: Current Def is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/93-fastroute.def |
| [INFO]: Current Guide is /openLANE_flow/designs/axmul/runs/run1/tmp/routing/93-fastroute.guide |
| [INFO]: Writing Verilog... |
| [INFO]: current step index: 94 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_diodes.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v |
| [INFO]: Running Detailed Routing... |
| [INFO]: current step index: 95 |
| [WARNING]: A run for axmul with tag 'run1' already exists. Pass -overwrite option to overwrite it |
| [INFO]: Now you can run commands that pick up where 'run1' left off |
| [INFO]: Current run directory is /openLANE_flow/designs/axmul/runs/run1 |
| [INFO]: Sourcing /openLANE_flow/designs/axmul/runs/run1/config.tcl |
| Any changes to the DESIGN config file will NOT be applied |
| [INFO]: Current DEF: /openLANE_flow/designs/axmul/runs/run1/tmp/routing/93-fastroute.def. |
| [INFO]: Use 'set_def file_name.def' if you'd like to change it. |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparation complete |
| [INFO]: Running Synthesis Exploration... |
| [INFO]: current step index: 96 |
| [INFO]: Changing netlist from /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis_preroute.v to /openLANE_flow/designs/axmul/runs/run1/results/synthesis/axmul.synthesis.v |
| [INFO]: This is a Synthesis Exploration and so no need to remove the defparam lines. |
