| OpenROAD 1 fb8ae93b6c7a5eb0e6fac83360a8a48d76c41885 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged.lef |
| [WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later. |
| The LEF parser will ignore this statement. |
| To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /openLANE_flow/designs/axmul/runs/run1/tmp/merged.lef at line 68110. |
| |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 441 library cells |
| [INFO ODB-0226] Finished LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged.lef |
| [INFO ODB-0127] Reading DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/75-verilog2def_openroad.def |
| [INFO ODB-0128] Design: axmul |
| [INFO ODB-0130] Created 32 pins. |
| [INFO ODB-0131] Created 178 components and 1352 component-terminals. |
| [INFO ODB-0133] Created 194 nets and 640 connections. |
| [INFO ODB-0134] Finished DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/floorplan/75-verilog2def_openroad.def |
| Found 0 macro blocks. |
| Using 1u default distance from corners. |
| Using 2 tracks default min distance between IO pins. |
| [INFO PPL-0007] Random pin placement. |