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foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-008 / 9a624e3d5d5b522b023229bb4c1191a4a9b4df1d / verilog / dv / Makefile
  1. 340cc4a Update full chip simulation to run from root by manarabdelaty · 4 years ago
  2. b41301c Added top level makefile by manarabdelaty · 4 years ago
  3. 8dbabc1 Update DV Makefiles by manarabdelaty · 4 years ago
  4. 69bd326 Updated DV tests by manarabdelaty · 4 years ago[Renamed from verilog/dv/user_proj_example/Makefile]
  5. d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 4 years ago