Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-008 / d6a3030cec106b6a609f9eac58db7ee0ea6d7133
commitd6a3030cec106b6a609f9eac58db7ee0ea6d7133[log] [tgz]
authorBYCakar <51989341+BYCakar@users.noreply.github.com>Fri Nov 12 20:25:20 2021 +0300
committerGitHub <noreply@github.com>Fri Nov 12 20:25:20 2021 +0300
treec0c0e983a151c1ad8305db15cd23a86fb3bf17ca
parent9b9d943f135425845aad6da3f78e90561b86c7b1 [diff]
Update README.md
1 file changed
tree: c0c0e983a151c1ad8305db15cd23a86fb3bf17ca
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Overview

YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.

Setup

export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
cd $UPRJ_ROOT
export CARAVEL_ROOT=$(pwd)/caravel
make install

Running Simulation

GPIO Test

  • This test is meant to verify that we can send and receive data from YONGA-100M Ethernet through the WISHBONE port. The firmware sends a UDP frame to YONGA-100M Ethernet, then receives a response from YONGA-100M Ethernet.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-ethernet_100m

Hardening the User Project Macro using OpenLANE

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>__
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>__
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck <https://github.com/efabless/mpw_precheck>

List of Contributors

In alphabetical order:

  • Abdullah Yildiz
  • Burak Yakup Cakar