Update DV for PWM
diff --git a/verilog/dv/randsack_netlists.v b/verilog/dv/randsack_netlists.v
index e61d22a..6585946 100644
--- a/verilog/dv/randsack_netlists.v
+++ b/verilog/dv/randsack_netlists.v
@@ -33,7 +33,8 @@
`include "collapsering_macro.v"
`include "ringosc_macro.v"
`include "ring_control.v"
+ `include "pwm_wb.v"
`include "picorv32_wb/gpio32_wb.v"
`include "picorv32_wb/simpleuart_div16_wb.v"
- `include "verilog-wishbone/rtl/wb_mux_4.v"
+ `include "verilog-wishbone/rtl/wb_mux_8.v"
`endif
diff --git a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
index ace6adf..a820b17 100644
--- a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
+++ b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
@@ -23,15 +23,23 @@
#define RANDSACK_GPIO0_BASE 0x30800000
#define RANDSACK_PWM0_BASE 0x30810000
+#define RANDSACK_PWM1_BASE 0x30810100
+#define RANDSACK_PWM2_BASE 0x30810200
+#define RANDSACK_PWM3_BASE 0x30810300
#define RANDSACK_UART0_BASE 0x30820000
#define RANDSACK_RING0_BASE 0x30830000
-#define RANDSACK_RING1_BASE 0x30840000
+#define RANDSACK_RING1_BASE 0x30830100
#define RANDSACK_GPIO_DATA 0x00
#define RANDSACK_GPIO_ENA 0x04
#define RANDSACK_GPIO_PU 0x08
#define RANDSACK_GPIO_PD 0x0c
+#define RANDSACK_PWM_DIV 0x00
+#define RANDSACK_PWM_CNTMAX 0x04
+#define RANDSACK_PWM_CNT 0x08
+#define RANDSACK_PWM_CMP 0x0c
+
#define RANDSACK_RING_COUNT_ADDR 0x00
#define RANDSACK_RING_CONTROL_ADDR 0x04
#define RANDSACK_RING_TRIMA_ADDR 0x08
@@ -95,10 +103,24 @@
while (reg_mprj_xfer == 1)
;
- // Enable GPIOs and write pattern.
- REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_ENA) = 0x0000ffff;
+ // Enable GPIOs and PWM IOs and write pattern.
+ REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_ENA) = 0x0000ffff | (1 << 23) | (1 << 21) | (1 << 19) | (1 << 17);
REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x00005555;
+ // Configure PWMs.
+ REG(RANDSACK_PWM0_BASE + RANDSACK_PWM_DIV) = 1;
+ REG(RANDSACK_PWM0_BASE + RANDSACK_PWM_CNTMAX) = 255;
+ REG(RANDSACK_PWM0_BASE + RANDSACK_PWM_CMP) = 128;
+ REG(RANDSACK_PWM1_BASE + RANDSACK_PWM_DIV) = 2;
+ REG(RANDSACK_PWM1_BASE + RANDSACK_PWM_CNTMAX) = 255;
+ REG(RANDSACK_PWM1_BASE + RANDSACK_PWM_CMP) = 64;
+ REG(RANDSACK_PWM2_BASE + RANDSACK_PWM_DIV) = 3;
+ REG(RANDSACK_PWM2_BASE + RANDSACK_PWM_CNTMAX) = 64;
+ REG(RANDSACK_PWM2_BASE + RANDSACK_PWM_CMP) = 32;
+ REG(RANDSACK_PWM3_BASE + RANDSACK_PWM_DIV) = 4;
+ REG(RANDSACK_PWM3_BASE + RANDSACK_PWM_CNTMAX) = 127;
+ REG(RANDSACK_PWM3_BASE + RANDSACK_PWM_CMP) = 64;
+
// Reset ring1 osc.
REG(RANDSACK_RING1_BASE + RANDSACK_RING_TRIMA_ADDR) = 50;
REG(RANDSACK_RING1_BASE + RANDSACK_RING_CONTROL_ADDR) = RANDSACK_RING_CONTROL_START_MASK + RANDSACK_RING_CONTROL_TEST_EN_MASK;
