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foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-005 / 89894c4eb816112a3688b130ec577c12b3e32a98
commit89894c4eb816112a3688b130ec577c12b3e32a98[log] [tgz]
authorAnish <anish@anishsinghani.com>Fri Nov 12 15:05:23 2021 -0500
committerAnish <anish@anishsinghani.com>Fri Nov 12 15:05:23 2021 -0500
tree411c576eb79c9ec1fcdeb061621b4aff388b59af
parent320265506f6be8ec43dc0ac14fd21d3ea343a90a [diff]
Add additional experimental cores, update licensing
42 files changed
tree: 411c576eb79c9ec1fcdeb061621b4aff388b59af
  1. def/
  2. gds/
  3. lef/
  4. mag/
  5. maglef/
  6. openlane/
  7. signoff/
  8. spi/
  9. verilog/
  10. caravel
  11. .gitignore
  12. .gitmodules
  13. info.yaml
  14. LICENSE
  15. Makefile
  16. README.md
README.md

Cryptography Accelerator v2

This is a cryptography accelerator chip for the Skywater MPW-THREE tapeout. It includes an AES256 core (with some key-entropy restrictions to reduce the number of bits in the key), a SHA256 core, a VGA game demo, and some other experimental structures. This includes improved versions of the unsuccessful cores from MPW-ONE.

For documentation on the AES and SHA cores (including the original Chisel source code), see asinghani/crypto-accelerator

Overview

This chip contains 4 major components:

  1. AES128/256 Accelerator

    • Optimized for balance between speed and area, can encrypt or decrypt a 16-byte block in ~20 cycles for AES128 or ~28 cycles for AES256
    • Supports both ECB and CBC modes (CBC is recommended because it is much more secure against certain types of attacks) with no performance penalty for using CBC
    • Has some internal key-entropy limitations since it is meant for experimental use

  2. SHA256 Accelerator

    • Can hash a single 512-bit block in ~66 cycles (and is able to process multiple blocks immediately back-to-back, i.e. when hashing a large file)

  3. VGA Game Demo

    • Contributed by Ethan Polcyn (and then ported to run on the ASIC environment)
    • Consists of a small infinite side-scrolling jumping game (based on the Chromium Browser‘s “No internet”-game), playable using button input from one of the chip’s I/O pins
    • Renders VGA video output at 640x480 through the chip's output pins
  1. Caravel harness/padframe
    • Contains a picorv32 CPU (which is used to interface with the rest of the cores through the Wishbone bus) and the padframe
    • See efabless/caravel for details.