Removed unused dv tests. Added wb_openram test to dv.
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index d87238f..7acbc5d 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus +PATTERNS = wb_openram all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile deleted file mode 100644 index 5237a05..0000000 --- a/verilog/dv/io_ports/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf - -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM -SIM?=RTL - -.SUFFIXES: - -PATTERN = io_ports - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c deleted file mode 100644 index 0b23571..0000000 --- a/verilog/dv/io_ports/io_ports.c +++ /dev/null
@@ -1,72 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" - -/* - IO Test: - - Configures MPRJ lower 8-IO pins as outputs - - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) -*/ - -void main() -{ - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - // Configure lower 8-IOs as user output - // Observe counter value in the testbench - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - -} -
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v deleted file mode 100644 index f7628bc..0000000 --- a/verilog/dv/io_ports/io_ports_tb.v +++ /dev/null
@@ -1,169 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - -module io_ports_tb; - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - - assign mprj_io_0 = mprj_io[7:0]; - // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]}; - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - // assign mprj_io[3] = 1'b1; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("io_ports.vcd"); - $dumpvars(0, io_ports_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (25) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - // Observe Output pins [7:0] - wait(mprj_io_0 == 8'h01); - wait(mprj_io_0 == 8'h02); - wait(mprj_io_0 == 8'h03); - wait(mprj_io_0 == 8'h04); - wait(mprj_io_0 == 8'h05); - wait(mprj_io_0 == 8'h06); - wait(mprj_io_0 == 8'h07); - wait(mprj_io_0 == 8'h08); - wait(mprj_io_0 == 8'h09); - wait(mprj_io_0 == 8'h0A); - wait(mprj_io_0 == 8'hFF); - wait(mprj_io_0 == 8'h00); - - `ifdef GL - $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); - `else - $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); - `endif - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #100; - power1 <= 1'b1; - #100; - power2 <= 1'b1; - #100; - power3 <= 1'b1; - #100; - power4 <= 1'b1; - end - - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire USER_VDD3V3 = power3; - wire USER_VDD1V8 = power4; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("io_ports.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile deleted file mode 100644 index ba979f7..0000000 --- a/verilog/dv/la_test1/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf - -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM -SIM?=RTL - -.SUFFIXES: - -PATTERN = la_test1 - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c deleted file mode 100644 index 220bdfe..0000000 --- a/verilog/dv/la_test1/la_test1.c +++ /dev/null
@@ -1,124 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" - -// -------------------------------------------------------- - -/* - MPRJ Logic Analyzer Test: - - Observes counter value through LA probes [31:0] - - Sets counter initial value through LA probes [63:32] - - Flags when counter value exceeds 500 through the management SoC gpio - - Outputs message to the UART when the test concludes successfuly -*/ - -void main() -{ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flad the start/end of a test - // The lower GPIO pins are configured to be output - // and accessible to the user project. They show - // the project count value, although this test is - // designed to read the project count through the - // logic analyzer probes. - // I/O 6 is configured for the UART Tx line - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Set UART clock to 64 kbaud (enable before I/O configuration) - reg_uart_clkdiv = 625; - reg_uart_enable = 1; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - // Configure LA probes [31:0], [127:64] as inputs to the cpu - // Configure LA probes [63:32] as outputs from the cpu - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB400000; - - // Set Counter value to zero through LA probes [63:32] - reg_la1_data = 0x00000000; - - // Configure LA probes from [63:32] as inputs to disable counter write - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; - - while (1) { - if (reg_la0_data > 0x1F4) { - reg_mprj_datal = 0xAB410000; - break; - } - } - print("\n"); - print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long! - reg_mprj_datal = 0xAB510000; -} -
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v deleted file mode 100644 index 626e390..0000000 --- a/verilog/dv/la_test1/la_test1_tb.v +++ /dev/null
@@ -1,149 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart.v" - -module la_test1_tb; - reg clock; - reg RSTB; - reg CSB; - - reg power1, power2; - - wire gpio; - wire uart_tx; - wire [37:0] mprj_io; - wire [15:0] checkbits; - - assign checkbits = mprj_io[31:16]; - assign uart_tx = mprj_io[6]; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - initial begin - // $dumpfile("la_test1.vcd"); - // $dumpvars(0, la_test1_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (200) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test LA (GL) Failed"); - `else - $display ("Monitor: Timeout, Test LA (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB40); - $display("LA Test 1 started"); - wait(checkbits == 16'hAB41); - wait(checkbits == 16'hAB51); - #10000; - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; - - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("la_test1.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - - // Testbench UART - tbuart tbuart ( - .ser_rx(uart_tx) - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile deleted file mode 100644 index 0435500..0000000 --- a/verilog/dv/la_test2/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf - -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM -SIM?=RTL - -.SUFFIXES: - -PATTERN = la_test2 - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c deleted file mode 100644 index 5875432..0000000 --- a/verilog/dv/la_test2/la_test2.c +++ /dev/null
@@ -1,114 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" - -/* - MPRJ LA Test: - - Sets counter clk through LA[64] - - Sets counter rst through LA[65] - - Observes count value for five clk cycle through LA[31:0] -*/ - -int clk = 0; -int i; - -void main() -{ - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - - // All GPIO pins are configured to be output - // Used to flad the start/end of a test - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - // Configure All LA probes as inputs to the cpu - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - // Configure LA[64] LA[65] as outputs from the cpu - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; - - // Set clk & reset to one - reg_la2_data = 0x00000003; - - // DELAY - for (i=0; i<5; i=i+1) {} - - // Toggle clk & de-assert reset - for (i=0; i<11; i=i+1) { - clk = !clk; - reg_la2_data = 0x00000000 | clk; - } - - if (reg_la0_data >= 0x05) { - reg_mprj_datal = 0xAB610000; - } - -} -
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v deleted file mode 100644 index e09905e..0000000 --- a/verilog/dv/la_test2/la_test2_tb.v +++ /dev/null
@@ -1,139 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - -module la_test2_tb; - reg clock; - reg RSTB; - reg CSB; - - reg power1, power2; - - wire gpio; - wire [37:0] mprj_io; - wire [15:0] checkbits; - - assign checkbits = mprj_io[31:16]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("la_test2.vcd"); - $dumpvars(0, la_test2_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'h AB60); - $display("Monitor: Test 2 MPRJ-Logic Analyzer Started"); - wait(checkbits == 16'h AB61); - $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed"); - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; - - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("la_test2.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), - .io3() - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c deleted file mode 100644 index e4d0a2d..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus.c +++ /dev/null
@@ -1,134 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" - -// -------------------------------------------------------- - -void main() -{ - // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flag the start/end of a test - // The lower GPIO pins are configured to be output - // and accessible to the user project. They show - // the project count value, although this test is - // designed to read the project count through the - // logic analyzer probes. - // I/O 6 is configured for the UART Tx line - uint32_t testval; - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2 - - reg_mprj_datal = 0x00000000; - reg_mprj_datah = 0x00000000; - - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; - - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Set UART clock to 64 kbaud (enable before I/O configuration) - reg_uart_clkdiv = 625; - reg_uart_enable = 1; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - /* TEST: Recast channels 35 to 32 to allow input to user project */ - /* This is done locally only: Do not run reg_mprj_xfer! */ - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Configure LA probes [31:0], [127:64] as inputs to the cpu - // Configure LA probes [63:32] as outputs from the cpu - reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] - reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB400000; - - // Set Counter value to zero through LA probes [63:32] - reg_la1_data = 0x00000000; - - // Configure LA probes from [63:32] as inputs to disable counter write - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; - - reg_mprj_datal = 0xAB410000; - reg_mprj_datah = 0x00000000; - - // Test ability to force data on channel 37 - // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful - reg_mprj_datah = 0xffffffca; - reg_mprj_datah = 0x00000000; - reg_mprj_datah = 0x0f0f0fc5; - reg_mprj_datah = 0x00000000; - - // Test ability to read back data generated by the user project - // on the "monitored" outputs. Read from the lower 16 bits and - // copy the value to the upper 16 bits. - - testval = reg_mprj_datal; - reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000; - - // Flag end of the test - reg_mprj_datal = 0xAB510000; -} -
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v deleted file mode 100644 index 1409015..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v +++ /dev/null
@@ -1,157 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype wire - -`timescale 1 ns / 1 ps - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart.v" - -module mprj_stimulus_tb; - // Signals declaration - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire HIGH; - wire LOW; - wire TRI; - assign HIGH = 1'b1; - assign LOW = 1'b0; - assign TRI = 1'bz; - - wire gpio; - wire uart_tx; - wire [37:0] mprj_io; - wire [15:0] checkbits; - wire [3:0] status; - - // Signals Assignment - assign checkbits = mprj_io[31:16]; - assign status = mprj_io[35:32]; - assign uart_tx = mprj_io[6]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("mprj_stimulus.vcd"); - $dumpvars(0, mprj_stimulus_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (150) begin - repeat (1000) @(posedge clock); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed"); - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB40); - $display("Monitor: mprj_stimulus test started"); - wait(status == 4'ha); - wait(status == 4'h5); - // Value 0009 reflects copying user-controlled outputs to memory and back - // to management-controlled outputs. - wait(checkbits == 16'h0009); - wait(checkbits == 16'hAB51); - $display("Monitor: mprj_stimulus test Passed"); - #10000; - $finish; - end - - // Reset Operation - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - - spiflash #( - .FILENAME("mprj_stimulus.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - - // Testbench UART - tbuart tbuart ( - .ser_rx(uart_tx) - ); - -endmodule -`default_nettype wire
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/wb_openram/Makefile similarity index 74% rename from verilog/dv/mprj_stimulus/Makefile rename to verilog/dv/wb_openram/Makefile index 3a73b99..f700888 100644 --- a/verilog/dv/mprj_stimulus/Makefile +++ b/verilog/dv/wb_openram/Makefile
@@ -14,9 +14,6 @@ # # SPDX-License-Identifier: Apache-2.0 -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - ## Caravel Pointers CARAVEL_ROOT ?= ../../../caravel CARAVEL_PATH ?= $(CARAVEL_ROOT) @@ -33,14 +30,14 @@ ## RISCV GCC GCC_PATH?=/ef/apps/bin GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL .SUFFIXES: -PATTERN = mprj_stimulus +PATTERN = wb_openram all: ${PATTERN:=.vcd} @@ -48,12 +45,12 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ + iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ @@ -62,7 +59,7 @@ %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env +%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< %.hex: %.elf @@ -73,21 +70,6 @@ %.bin: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - # ---- Clean ---- clean:
diff --git a/verilog/dv/wb_openram/wb_openram.c b/verilog/dv/wb_openram/wb_openram.c new file mode 100644 index 0000000..1d04320 --- /dev/null +++ b/verilog/dv/wb_openram/wb_openram.c
@@ -0,0 +1,118 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include "verilog/dv/caravel/defs.h" +#include "verilog/dv/caravel/stub.c" + +// Caravel allows user project to use 0x30xx_xxxx address space on Wishbone bus +// 0x3000_0000 till 3000_03ff -> 256 Words of OpenRAM (1024 Bytes) +#define OPENRAM_BASE_ADDRESS 0x30000000 +#define OPENRAM_SIZE_DWORDS 256ul +#define OPENRAM_SIZE_BYTES (4ul * OPENRAM_SIZE_DWORDS) +#define OPENRAM_ADDRESS_MASK (OPENRAM_SIZE_BYTES - 1) +#define OPENRAM_MEM(offset) (*(volatile uint32_t*)(OPENRAM_BASE_ADDRESS + (offset & OPENRAM_ADDRESS_MASK))) + +// Generates 32bits wide value out of address, not random +unsigned long generate_value(unsigned long address) +{ + return ((address & OPENRAM_ADDRESS_MASK) << 19) | + ((~address & OPENRAM_ADDRESS_MASK) << 1); +} + +void main() +{ + unsigned int address, err_cnt = 0; + + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + + // All GPIO pins are configured to be output + // Used to flad the start/end of a test + + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // Flag start of the test + reg_mprj_datal = 0xAB600000; + + // Fill memory + for (address = 0; address < OPENRAM_SIZE_DWORDS; address += 32) + { + // generate some dword based on address + OPENRAM_MEM(address) = generate_value(address); + } + + // Check memory + err_cnt = 0; + for (address = 0; address < OPENRAM_SIZE_DWORDS; address += 32) + { + // check dword based on address + if (OPENRAM_MEM(address) != generate_value(address)) + { + err_cnt++; + } + } + + if (err_cnt == 0) + { + reg_mprj_datal = 0xAB610000; + } +} +
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_openram/wb_openram_tb.v similarity index 73% rename from verilog/dv/wb_port/wb_port_tb.v rename to verilog/dv/wb_openram/wb_openram_tb.v index b32f900..c189538 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_openram/wb_openram_tb.v
@@ -21,21 +21,19 @@ `include "caravel_netlists.v" `include "spiflash.v" -module wb_port_tb; +module wb_openram_tb; reg clock; reg RSTB; reg CSB; reg power1, power2; reg power3, power4; - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; + wire gpio; + wire [37:0] mprj_io; wire [15:0] checkbits; assign checkbits = mprj_io[31:16]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -48,32 +46,36 @@ end initial begin - $dumpfile("wb_port.vcd"); - $dumpvars(0, wb_port_tb); + $dumpfile("wb_openram.vcd"); + $dumpvars(0, wb_openram_tb); - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); + // Repeat cycles of 10000 clock edges as needed to complete testbench + repeat (25) begin + repeat (10000) @(posedge clock); + $display("+10000 cycles"); end $display("%c[1;31m",27); `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed"); + $display ("Monitor: Timeout, Test OpenRAM Project IO Ports (GL) Failed"); `else - $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed"); + $display ("Monitor: Timeout, Test OpenRAM Project IO Ports (RTL) Failed"); `endif $display("%c[0m",27); $finish; end initial begin - wait(checkbits == 16'h AB60); - $display("Monitor: MPRJ-Logic WB Started"); + wait(checkbits == 16'h AB60); + `ifdef GL + $display("Monitor: Test OpenRAM Project IO (GL) Started"); + `else + $display("Monitor: Test OpenRAM Project IO (RTL) Started"); + `endif wait(checkbits == 16'h AB61); `ifdef GL - $display("Monitor: Mega-Project WB (GL) Passed"); + $display("Monitor: Test OpenRAM Project IO (GL) Passed"); `else - $display("Monitor: Mega-Project WB (RTL) Passed"); + $display("Monitor: Test OpenRAM Project IO (RTL) Passed"); `endif $finish; end @@ -82,9 +84,9 @@ RSTB <= 1'b0; CSB <= 1'b1; // Force CSB high #2000; - RSTB <= 1'b1; // Release reset - #170000; - CSB = 1'b0; // CSB can be released + RSTB <= 1'b1; // Release reset + #1700000; + CSB = 1'b0; // CSB can be released end initial begin // Power-up sequence @@ -101,11 +103,11 @@ #100; power4 <= 1'b1; end - +/* always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + #1 $display("MPRJ-IO state = %b ", mprj_io[20:0]); end - +*/ wire flash_csb; wire flash_clk; wire flash_io0; @@ -143,7 +145,7 @@ ); spiflash #( - .FILENAME("wb_port.hex") + .FILENAME("wb_openram.hex") ) spiflash ( .csb(flash_csb), .clk(flash_clk), @@ -154,4 +156,4 @@ ); endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile deleted file mode 100644 index 1c784c6..0000000 --- a/verilog/dv/wb_port/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf - -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM -SIM?=RTL - -.SUFFIXES: - -PATTERN = wb_port - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c deleted file mode 100644 index 425c115..0000000 --- a/verilog/dv/wb_port/wb_port.c +++ /dev/null
@@ -1,89 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" - -/* - Wishbone Test: - - Configures MPRJ lower 8-IO pins as outputs - - Checks counter value through the wishbone port -*/ -int i = 0; -int clk = 0; - -void main() -{ - - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - reg_mprj_slave = 0x00002710; - if (reg_mprj_slave == 0x2752) { - reg_mprj_datal = 0xAB610000; - } else { - reg_mprj_datal = 0xAB600000; - } -}
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 3537de8..fc0f7a9 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,10 @@ // Assume default net type to be wire because GL netlists don't have the wire definitions `default_nettype wire `include "gl/user_project_wrapper.v" - `include "gl/user_proj_example.v" + `include "../wb_openram_wrapper/src/wb_openram_wrapper.v" + `include "../openram_testchip/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v" `else `include "user_project_wrapper.v" - `include "user_proj_example.v" + `include "../../wb_openram_wrapper/src/wb_openram_wrapper.v" + `include "../../openram_testchip/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v" `endif \ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v deleted file mode 100644 index 26081e9..0000000 --- a/verilog/rtl/user_proj_example.v +++ /dev/null
@@ -1,165 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ - -module user_proj_example #( - parameter BITS = 32 -)( -`ifdef USE_POWER_PINS - inout vccd1, // User area 1 1.8V supply - inout vssd1, // User area 1 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq -); - wire clk; - wire rst; - - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; - - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5ee1cee..0154db3 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -82,40 +82,64 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_proj_example mprj ( +wire openram_clk0; +wire openram_csb0; +wire openram_web0; +wire [3:0] openram_wmask0; +wire [7:0] openram_addr0; +wire [31:0] openram_din0; +wire [31:0] openram_dout0; + +sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB +( `ifdef USE_POWER_PINS - .vccd1(vccd1), // User area 1 1.8V power - .vssd1(vssd1), // User area 1 digital ground + .vccd1 (vccd1), + .vssd1 (vssd1), `endif - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), + .clk0 (openram_clk0), + .csb0 (openram_csb0), + .web0 (openram_web0), + .wmask0 (openram_wmask0), + .addr0 (openram_addr0), + .din0 (openram_din0), + .dout0 (openram_dout0) +); - // MGMT SoC Wishbone Slave +wb_openram_wrapper wb_openram_wrapper +( +`ifdef USE_POWER_PINS + .vdda1 (vdda1), // User area 1 3.3V supply + .vdda2 (vdda2), // User area 2 3.3V supply + .vssa1 (vssa1), // User area 1 analog ground + .vssa2 (vssa2), // User area 2 analog ground + .vccd1 (vccd1), // User area 1 1.8V supply + .vccd2 (vccd2), // User area 2 1.8v supply + .vssd1 (vssd1), // User area 1 digital ground + .vssd2 (vssd2), // User area 2 digital ground +`endif - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), + // Wishbone port A + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbs_stb_i (wbs_stb_i), + .wbs_cyc_i (wbs_cyc_i), + .wbs_we_i (wbs_we_i), + .wbs_sel_i (wbs_sel_i), + .wbs_dat_i (wbs_dat_i), + .wbs_adr_i (wbs_adr_i), + .wbs_ack_o (wbs_ack_o), + .wbs_dat_o (wbs_dat_o), - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), - - // IRQ - .irq(user_irq) + // OpenRAM interface + // Port 0: RW + .clk0 (openram_clk0), // clock + .csb0 (openram_csb0), // active low chip select + .web0 (openram_web0), // active low write control + .wmask0 (openram_wmask0), // write mask + .addr0 (openram_addr0), + .din0 (openram_din0), + .dout0 (openram_dout0) ); endmodule // user_project_wrapper