Changed interval and max time for completing dv.

verilog/dv/wb_openram/wb_openram_tb.v

diff --git a/verilog/dv/wb_openram/wb_openram_tb.v b/verilog/dv/wb_openram/wb_openram_tb.v
index d48d38a..cb72241 100644
--- a/verilog/dv/wb_openram/wb_openram_tb.v
+++ b/verilog/dv/wb_openram/wb_openram_tb.v
@@ -52,9 +52,9 @@
 		$dumpvars(0, wb_openram_tb);
 
 		// Repeat cycles of 10000 clock edges as needed to complete testbench
-		repeat (12) begin
-			repeat (5000) @(posedge clock);
-			$display("+5000 cycles");
+		repeat (8) begin
+			repeat (10000) @(posedge clock);
+			$display("+10000 cycles");
 		end
 		$display("%c[1;31m",27);
 		`ifdef GL