Using new version of wb_wrapper (avoiding generation of setup/hold violations for openram macro, fixed double-operation). Improved dv-test.
diff --git a/verilog/dv/wb_openram/wb_openram.c b/verilog/dv/wb_openram/wb_openram.c
index 57c7036..fd265c0 100644
--- a/verilog/dv/wb_openram/wb_openram.c
+++ b/verilog/dv/wb_openram/wb_openram.c
@@ -84,22 +84,6 @@
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
@@ -121,11 +105,11 @@
// check dword based on address
if (OPENRAM_MEM(address) != generate_value(address))
{
- reg_mprj_datal = 0xAB61dead;
+ reg_mprj_datal = 0xAB7E0000;
return; // instant fail
}
}
- reg_mprj_datal = 0xAB610000; // pass
+ reg_mprj_datal = 0xAB700000; // pass
}
diff --git a/verilog/dv/wb_openram/wb_openram_tb.v b/verilog/dv/wb_openram/wb_openram_tb.v
index c43f4ef..9bcf0d9 100644
--- a/verilog/dv/wb_openram/wb_openram_tb.v
+++ b/verilog/dv/wb_openram/wb_openram_tb.v
@@ -30,11 +30,11 @@
wire gpio;
wire [37:0] mprj_io;
- wire [15:0] checkpoint;
- wire [15:0] status;
+ wire [11:0] checkpoint;
+ wire [3:0] status;
- assign checkpoint = mprj_io[31:16];
- assign status = mprj_io[15:0];
+ assign checkpoint = mprj_io[31:20];
+ assign status = mprj_io[19:16];
// External clock is used by default. Make this artificially fast for the
@@ -67,14 +67,14 @@
end
initial begin
- wait(checkpoint == 16'h AB60);
+ wait(checkpoint == 12'h AB6);
`ifdef GL
$display("Monitor: Test OpenRAM Project IO (GL) Started");
`else
$display("Monitor: Test OpenRAM Project IO (RTL) Started");
`endif
- wait(checkpoint == 16'h AB61);
- if (status == 16'h 0000) begin
+ wait(checkpoint == 12'h AB7);
+ if (status == 4'h 0) begin
`ifdef GL
$display("Monitor: Test OpenRAM Project IO (GL) Passed");
`else
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index ecae883..977ea18 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -53,8 +53,210 @@
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
+ wire \openram_addr0[0] ;
+ wire \openram_addr0[1] ;
+ wire \openram_addr0[2] ;
+ wire \openram_addr0[3] ;
+ wire \openram_addr0[4] ;
+ wire \openram_addr0[5] ;
+ wire \openram_addr0[6] ;
+ wire \openram_addr0[7] ;
+ wire openram_clk0;
+ wire openram_csb0;
+ wire \openram_din0[0] ;
+ wire \openram_din0[10] ;
+ wire \openram_din0[11] ;
+ wire \openram_din0[12] ;
+ wire \openram_din0[13] ;
+ wire \openram_din0[14] ;
+ wire \openram_din0[15] ;
+ wire \openram_din0[16] ;
+ wire \openram_din0[17] ;
+ wire \openram_din0[18] ;
+ wire \openram_din0[19] ;
+ wire \openram_din0[1] ;
+ wire \openram_din0[20] ;
+ wire \openram_din0[21] ;
+ wire \openram_din0[22] ;
+ wire \openram_din0[23] ;
+ wire \openram_din0[24] ;
+ wire \openram_din0[25] ;
+ wire \openram_din0[26] ;
+ wire \openram_din0[27] ;
+ wire \openram_din0[28] ;
+ wire \openram_din0[29] ;
+ wire \openram_din0[2] ;
+ wire \openram_din0[30] ;
+ wire \openram_din0[31] ;
+ wire \openram_din0[3] ;
+ wire \openram_din0[4] ;
+ wire \openram_din0[5] ;
+ wire \openram_din0[6] ;
+ wire \openram_din0[7] ;
+ wire \openram_din0[8] ;
+ wire \openram_din0[9] ;
+ wire \openram_dout0[0] ;
+ wire \openram_dout0[10] ;
+ wire \openram_dout0[11] ;
+ wire \openram_dout0[12] ;
+ wire \openram_dout0[13] ;
+ wire \openram_dout0[14] ;
+ wire \openram_dout0[15] ;
+ wire \openram_dout0[16] ;
+ wire \openram_dout0[17] ;
+ wire \openram_dout0[18] ;
+ wire \openram_dout0[19] ;
+ wire \openram_dout0[1] ;
+ wire \openram_dout0[20] ;
+ wire \openram_dout0[21] ;
+ wire \openram_dout0[22] ;
+ wire \openram_dout0[23] ;
+ wire \openram_dout0[24] ;
+ wire \openram_dout0[25] ;
+ wire \openram_dout0[26] ;
+ wire \openram_dout0[27] ;
+ wire \openram_dout0[28] ;
+ wire \openram_dout0[29] ;
+ wire \openram_dout0[2] ;
+ wire \openram_dout0[30] ;
+ wire \openram_dout0[31] ;
+ wire \openram_dout0[3] ;
+ wire \openram_dout0[4] ;
+ wire \openram_dout0[5] ;
+ wire \openram_dout0[6] ;
+ wire \openram_dout0[7] ;
+ wire \openram_dout0[8] ;
+ wire \openram_dout0[9] ;
+ wire openram_web0;
+ wire \openram_wmask0[0] ;
+ wire \openram_wmask0[1] ;
+ wire \openram_wmask0[2] ;
+ wire \openram_wmask0[3] ;
- user_proj_example mprj (.vccd1(vccd1),
+ sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB (.csb0(openram_csb0),
+ .web0(openram_web0),
+ .clk0(openram_clk0),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .addr0({\openram_addr0[7] ,
+ \openram_addr0[6] ,
+ \openram_addr0[5] ,
+ \openram_addr0[4] ,
+ \openram_addr0[3] ,
+ \openram_addr0[2] ,
+ \openram_addr0[1] ,
+ \openram_addr0[0] }),
+ .addr1({_NC1,
+ _NC2,
+ _NC3,
+ _NC4,
+ _NC5,
+ _NC6,
+ _NC7,
+ _NC8}),
+ .din0({\openram_din0[31] ,
+ \openram_din0[30] ,
+ \openram_din0[29] ,
+ \openram_din0[28] ,
+ \openram_din0[27] ,
+ \openram_din0[26] ,
+ \openram_din0[25] ,
+ \openram_din0[24] ,
+ \openram_din0[23] ,
+ \openram_din0[22] ,
+ \openram_din0[21] ,
+ \openram_din0[20] ,
+ \openram_din0[19] ,
+ \openram_din0[18] ,
+ \openram_din0[17] ,
+ \openram_din0[16] ,
+ \openram_din0[15] ,
+ \openram_din0[14] ,
+ \openram_din0[13] ,
+ \openram_din0[12] ,
+ \openram_din0[11] ,
+ \openram_din0[10] ,
+ \openram_din0[9] ,
+ \openram_din0[8] ,
+ \openram_din0[7] ,
+ \openram_din0[6] ,
+ \openram_din0[5] ,
+ \openram_din0[4] ,
+ \openram_din0[3] ,
+ \openram_din0[2] ,
+ \openram_din0[1] ,
+ \openram_din0[0] }),
+ .dout0({\openram_dout0[31] ,
+ \openram_dout0[30] ,
+ \openram_dout0[29] ,
+ \openram_dout0[28] ,
+ \openram_dout0[27] ,
+ \openram_dout0[26] ,
+ \openram_dout0[25] ,
+ \openram_dout0[24] ,
+ \openram_dout0[23] ,
+ \openram_dout0[22] ,
+ \openram_dout0[21] ,
+ \openram_dout0[20] ,
+ \openram_dout0[19] ,
+ \openram_dout0[18] ,
+ \openram_dout0[17] ,
+ \openram_dout0[16] ,
+ \openram_dout0[15] ,
+ \openram_dout0[14] ,
+ \openram_dout0[13] ,
+ \openram_dout0[12] ,
+ \openram_dout0[11] ,
+ \openram_dout0[10] ,
+ \openram_dout0[9] ,
+ \openram_dout0[8] ,
+ \openram_dout0[7] ,
+ \openram_dout0[6] ,
+ \openram_dout0[5] ,
+ \openram_dout0[4] ,
+ \openram_dout0[3] ,
+ \openram_dout0[2] ,
+ \openram_dout0[1] ,
+ \openram_dout0[0] }),
+ .dout1({_NC9,
+ _NC10,
+ _NC11,
+ _NC12,
+ _NC13,
+ _NC14,
+ _NC15,
+ _NC16,
+ _NC17,
+ _NC18,
+ _NC19,
+ _NC20,
+ _NC21,
+ _NC22,
+ _NC23,
+ _NC24,
+ _NC25,
+ _NC26,
+ _NC27,
+ _NC28,
+ _NC29,
+ _NC30,
+ _NC31,
+ _NC32,
+ _NC33,
+ _NC34,
+ _NC35,
+ _NC36,
+ _NC37,
+ _NC38,
+ _NC39,
+ _NC40}),
+ .wmask0({\openram_wmask0[3] ,
+ \openram_wmask0[2] ,
+ \openram_wmask0[1] ,
+ \openram_wmask0[0] }));
+ wb_openram_wrapper wb_openram_wrapper (.clk0(openram_clk0),
+ .csb0(openram_csb0),
+ .vccd1(vccd1),
.vssd1(vssd1),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -62,507 +264,79 @@
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
- .io_in({io_in[37],
- io_in[36],
- io_in[35],
- io_in[34],
- io_in[33],
- io_in[32],
- io_in[31],
- io_in[30],
- io_in[29],
- io_in[28],
- io_in[27],
- io_in[26],
- io_in[25],
- io_in[24],
- io_in[23],
- io_in[22],
- io_in[21],
- io_in[20],
- io_in[19],
- io_in[18],
- io_in[17],
- io_in[16],
- io_in[15],
- io_in[14],
- io_in[13],
- io_in[12],
- io_in[11],
- io_in[10],
- io_in[9],
- io_in[8],
- io_in[7],
- io_in[6],
- io_in[5],
- io_in[4],
- io_in[3],
- io_in[2],
- io_in[1],
- io_in[0]}),
- .io_oeb({io_oeb[37],
- io_oeb[36],
- io_oeb[35],
- io_oeb[34],
- io_oeb[33],
- io_oeb[32],
- io_oeb[31],
- io_oeb[30],
- io_oeb[29],
- io_oeb[28],
- io_oeb[27],
- io_oeb[26],
- io_oeb[25],
- io_oeb[24],
- io_oeb[23],
- io_oeb[22],
- io_oeb[21],
- io_oeb[20],
- io_oeb[19],
- io_oeb[18],
- io_oeb[17],
- io_oeb[16],
- io_oeb[15],
- io_oeb[14],
- io_oeb[13],
- io_oeb[12],
- io_oeb[11],
- io_oeb[10],
- io_oeb[9],
- io_oeb[8],
- io_oeb[7],
- io_oeb[6],
- io_oeb[5],
- io_oeb[4],
- io_oeb[3],
- io_oeb[2],
- io_oeb[1],
- io_oeb[0]}),
- .io_out({io_out[37],
- io_out[36],
- io_out[35],
- io_out[34],
- io_out[33],
- io_out[32],
- io_out[31],
- io_out[30],
- io_out[29],
- io_out[28],
- io_out[27],
- io_out[26],
- io_out[25],
- io_out[24],
- io_out[23],
- io_out[22],
- io_out[21],
- io_out[20],
- io_out[19],
- io_out[18],
- io_out[17],
- io_out[16],
- io_out[15],
- io_out[14],
- io_out[13],
- io_out[12],
- io_out[11],
- io_out[10],
- io_out[9],
- io_out[8],
- io_out[7],
- io_out[6],
- io_out[5],
- io_out[4],
- io_out[3],
- io_out[2],
- io_out[1],
- io_out[0]}),
- .irq({user_irq[2],
- user_irq[1],
- user_irq[0]}),
- .la_data_in({la_data_in[127],
- la_data_in[126],
- la_data_in[125],
- la_data_in[124],
- la_data_in[123],
- la_data_in[122],
- la_data_in[121],
- la_data_in[120],
- la_data_in[119],
- la_data_in[118],
- la_data_in[117],
- la_data_in[116],
- la_data_in[115],
- la_data_in[114],
- la_data_in[113],
- la_data_in[112],
- la_data_in[111],
- la_data_in[110],
- la_data_in[109],
- la_data_in[108],
- la_data_in[107],
- la_data_in[106],
- la_data_in[105],
- la_data_in[104],
- la_data_in[103],
- la_data_in[102],
- la_data_in[101],
- la_data_in[100],
- la_data_in[99],
- la_data_in[98],
- la_data_in[97],
- la_data_in[96],
- la_data_in[95],
- la_data_in[94],
- la_data_in[93],
- la_data_in[92],
- la_data_in[91],
- la_data_in[90],
- la_data_in[89],
- la_data_in[88],
- la_data_in[87],
- la_data_in[86],
- la_data_in[85],
- la_data_in[84],
- la_data_in[83],
- la_data_in[82],
- la_data_in[81],
- la_data_in[80],
- la_data_in[79],
- la_data_in[78],
- la_data_in[77],
- la_data_in[76],
- la_data_in[75],
- la_data_in[74],
- la_data_in[73],
- la_data_in[72],
- la_data_in[71],
- la_data_in[70],
- la_data_in[69],
- la_data_in[68],
- la_data_in[67],
- la_data_in[66],
- la_data_in[65],
- la_data_in[64],
- la_data_in[63],
- la_data_in[62],
- la_data_in[61],
- la_data_in[60],
- la_data_in[59],
- la_data_in[58],
- la_data_in[57],
- la_data_in[56],
- la_data_in[55],
- la_data_in[54],
- la_data_in[53],
- la_data_in[52],
- la_data_in[51],
- la_data_in[50],
- la_data_in[49],
- la_data_in[48],
- la_data_in[47],
- la_data_in[46],
- la_data_in[45],
- la_data_in[44],
- la_data_in[43],
- la_data_in[42],
- la_data_in[41],
- la_data_in[40],
- la_data_in[39],
- la_data_in[38],
- la_data_in[37],
- la_data_in[36],
- la_data_in[35],
- la_data_in[34],
- la_data_in[33],
- la_data_in[32],
- la_data_in[31],
- la_data_in[30],
- la_data_in[29],
- la_data_in[28],
- la_data_in[27],
- la_data_in[26],
- la_data_in[25],
- la_data_in[24],
- la_data_in[23],
- la_data_in[22],
- la_data_in[21],
- la_data_in[20],
- la_data_in[19],
- la_data_in[18],
- la_data_in[17],
- la_data_in[16],
- la_data_in[15],
- la_data_in[14],
- la_data_in[13],
- la_data_in[12],
- la_data_in[11],
- la_data_in[10],
- la_data_in[9],
- la_data_in[8],
- la_data_in[7],
- la_data_in[6],
- la_data_in[5],
- la_data_in[4],
- la_data_in[3],
- la_data_in[2],
- la_data_in[1],
- la_data_in[0]}),
- .la_data_out({la_data_out[127],
- la_data_out[126],
- la_data_out[125],
- la_data_out[124],
- la_data_out[123],
- la_data_out[122],
- la_data_out[121],
- la_data_out[120],
- la_data_out[119],
- la_data_out[118],
- la_data_out[117],
- la_data_out[116],
- la_data_out[115],
- la_data_out[114],
- la_data_out[113],
- la_data_out[112],
- la_data_out[111],
- la_data_out[110],
- la_data_out[109],
- la_data_out[108],
- la_data_out[107],
- la_data_out[106],
- la_data_out[105],
- la_data_out[104],
- la_data_out[103],
- la_data_out[102],
- la_data_out[101],
- la_data_out[100],
- la_data_out[99],
- la_data_out[98],
- la_data_out[97],
- la_data_out[96],
- la_data_out[95],
- la_data_out[94],
- la_data_out[93],
- la_data_out[92],
- la_data_out[91],
- la_data_out[90],
- la_data_out[89],
- la_data_out[88],
- la_data_out[87],
- la_data_out[86],
- la_data_out[85],
- la_data_out[84],
- la_data_out[83],
- la_data_out[82],
- la_data_out[81],
- la_data_out[80],
- la_data_out[79],
- la_data_out[78],
- la_data_out[77],
- la_data_out[76],
- la_data_out[75],
- la_data_out[74],
- la_data_out[73],
- la_data_out[72],
- la_data_out[71],
- la_data_out[70],
- la_data_out[69],
- la_data_out[68],
- la_data_out[67],
- la_data_out[66],
- la_data_out[65],
- la_data_out[64],
- la_data_out[63],
- la_data_out[62],
- la_data_out[61],
- la_data_out[60],
- la_data_out[59],
- la_data_out[58],
- la_data_out[57],
- la_data_out[56],
- la_data_out[55],
- la_data_out[54],
- la_data_out[53],
- la_data_out[52],
- la_data_out[51],
- la_data_out[50],
- la_data_out[49],
- la_data_out[48],
- la_data_out[47],
- la_data_out[46],
- la_data_out[45],
- la_data_out[44],
- la_data_out[43],
- la_data_out[42],
- la_data_out[41],
- la_data_out[40],
- la_data_out[39],
- la_data_out[38],
- la_data_out[37],
- la_data_out[36],
- la_data_out[35],
- la_data_out[34],
- la_data_out[33],
- la_data_out[32],
- la_data_out[31],
- la_data_out[30],
- la_data_out[29],
- la_data_out[28],
- la_data_out[27],
- la_data_out[26],
- la_data_out[25],
- la_data_out[24],
- la_data_out[23],
- la_data_out[22],
- la_data_out[21],
- la_data_out[20],
- la_data_out[19],
- la_data_out[18],
- la_data_out[17],
- la_data_out[16],
- la_data_out[15],
- la_data_out[14],
- la_data_out[13],
- la_data_out[12],
- la_data_out[11],
- la_data_out[10],
- la_data_out[9],
- la_data_out[8],
- la_data_out[7],
- la_data_out[6],
- la_data_out[5],
- la_data_out[4],
- la_data_out[3],
- la_data_out[2],
- la_data_out[1],
- la_data_out[0]}),
- .la_oenb({la_oenb[127],
- la_oenb[126],
- la_oenb[125],
- la_oenb[124],
- la_oenb[123],
- la_oenb[122],
- la_oenb[121],
- la_oenb[120],
- la_oenb[119],
- la_oenb[118],
- la_oenb[117],
- la_oenb[116],
- la_oenb[115],
- la_oenb[114],
- la_oenb[113],
- la_oenb[112],
- la_oenb[111],
- la_oenb[110],
- la_oenb[109],
- la_oenb[108],
- la_oenb[107],
- la_oenb[106],
- la_oenb[105],
- la_oenb[104],
- la_oenb[103],
- la_oenb[102],
- la_oenb[101],
- la_oenb[100],
- la_oenb[99],
- la_oenb[98],
- la_oenb[97],
- la_oenb[96],
- la_oenb[95],
- la_oenb[94],
- la_oenb[93],
- la_oenb[92],
- la_oenb[91],
- la_oenb[90],
- la_oenb[89],
- la_oenb[88],
- la_oenb[87],
- la_oenb[86],
- la_oenb[85],
- la_oenb[84],
- la_oenb[83],
- la_oenb[82],
- la_oenb[81],
- la_oenb[80],
- la_oenb[79],
- la_oenb[78],
- la_oenb[77],
- la_oenb[76],
- la_oenb[75],
- la_oenb[74],
- la_oenb[73],
- la_oenb[72],
- la_oenb[71],
- la_oenb[70],
- la_oenb[69],
- la_oenb[68],
- la_oenb[67],
- la_oenb[66],
- la_oenb[65],
- la_oenb[64],
- la_oenb[63],
- la_oenb[62],
- la_oenb[61],
- la_oenb[60],
- la_oenb[59],
- la_oenb[58],
- la_oenb[57],
- la_oenb[56],
- la_oenb[55],
- la_oenb[54],
- la_oenb[53],
- la_oenb[52],
- la_oenb[51],
- la_oenb[50],
- la_oenb[49],
- la_oenb[48],
- la_oenb[47],
- la_oenb[46],
- la_oenb[45],
- la_oenb[44],
- la_oenb[43],
- la_oenb[42],
- la_oenb[41],
- la_oenb[40],
- la_oenb[39],
- la_oenb[38],
- la_oenb[37],
- la_oenb[36],
- la_oenb[35],
- la_oenb[34],
- la_oenb[33],
- la_oenb[32],
- la_oenb[31],
- la_oenb[30],
- la_oenb[29],
- la_oenb[28],
- la_oenb[27],
- la_oenb[26],
- la_oenb[25],
- la_oenb[24],
- la_oenb[23],
- la_oenb[22],
- la_oenb[21],
- la_oenb[20],
- la_oenb[19],
- la_oenb[18],
- la_oenb[17],
- la_oenb[16],
- la_oenb[15],
- la_oenb[14],
- la_oenb[13],
- la_oenb[12],
- la_oenb[11],
- la_oenb[10],
- la_oenb[9],
- la_oenb[8],
- la_oenb[7],
- la_oenb[6],
- la_oenb[5],
- la_oenb[4],
- la_oenb[3],
- la_oenb[2],
- la_oenb[1],
- la_oenb[0]}),
+ .web0(openram_web0),
+ .addr0({\openram_addr0[7] ,
+ \openram_addr0[6] ,
+ \openram_addr0[5] ,
+ \openram_addr0[4] ,
+ \openram_addr0[3] ,
+ \openram_addr0[2] ,
+ \openram_addr0[1] ,
+ \openram_addr0[0] }),
+ .din0({\openram_dout0[31] ,
+ \openram_dout0[30] ,
+ \openram_dout0[29] ,
+ \openram_dout0[28] ,
+ \openram_dout0[27] ,
+ \openram_dout0[26] ,
+ \openram_dout0[25] ,
+ \openram_dout0[24] ,
+ \openram_dout0[23] ,
+ \openram_dout0[22] ,
+ \openram_dout0[21] ,
+ \openram_dout0[20] ,
+ \openram_dout0[19] ,
+ \openram_dout0[18] ,
+ \openram_dout0[17] ,
+ \openram_dout0[16] ,
+ \openram_dout0[15] ,
+ \openram_dout0[14] ,
+ \openram_dout0[13] ,
+ \openram_dout0[12] ,
+ \openram_dout0[11] ,
+ \openram_dout0[10] ,
+ \openram_dout0[9] ,
+ \openram_dout0[8] ,
+ \openram_dout0[7] ,
+ \openram_dout0[6] ,
+ \openram_dout0[5] ,
+ \openram_dout0[4] ,
+ \openram_dout0[3] ,
+ \openram_dout0[2] ,
+ \openram_dout0[1] ,
+ \openram_dout0[0] }),
+ .dout0({\openram_din0[31] ,
+ \openram_din0[30] ,
+ \openram_din0[29] ,
+ \openram_din0[28] ,
+ \openram_din0[27] ,
+ \openram_din0[26] ,
+ \openram_din0[25] ,
+ \openram_din0[24] ,
+ \openram_din0[23] ,
+ \openram_din0[22] ,
+ \openram_din0[21] ,
+ \openram_din0[20] ,
+ \openram_din0[19] ,
+ \openram_din0[18] ,
+ \openram_din0[17] ,
+ \openram_din0[16] ,
+ \openram_din0[15] ,
+ \openram_din0[14] ,
+ \openram_din0[13] ,
+ \openram_din0[12] ,
+ \openram_din0[11] ,
+ \openram_din0[10] ,
+ \openram_din0[9] ,
+ \openram_din0[8] ,
+ \openram_din0[7] ,
+ \openram_din0[6] ,
+ \openram_din0[5] ,
+ \openram_din0[4] ,
+ \openram_din0[3] ,
+ \openram_din0[2] ,
+ \openram_din0[1] ,
+ \openram_din0[0] }),
.wbs_adr_i({wbs_adr_i[31],
wbs_adr_i[30],
wbs_adr_i[29],
@@ -662,5 +436,9 @@
.wbs_sel_i({wbs_sel_i[3],
wbs_sel_i[2],
wbs_sel_i[1],
- wbs_sel_i[0]}));
+ wbs_sel_i[0]}),
+ .wmask0({\openram_wmask0[3] ,
+ \openram_wmask0[2] ,
+ \openram_wmask0[1] ,
+ \openram_wmask0[0] }));
endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e37987f..7c2ad82 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -127,13 +127,13 @@
// OpenRAM interface
// Port 0: RW
- .clk0 (openram_clk0), // clock
- .csb0 (openram_csb0), // active low chip select
- .web0 (openram_web0), // active low write control
- .wmask0 (openram_wmask0), // write mask
- .addr0 (openram_addr0),
- .din0 (openram_dout0),
- .dout0 (openram_din0)
+ .ram_clk0 (openram_clk0), // clock
+ .ram_csb0 (openram_csb0), // active low chip select
+ .ram_web0 (openram_web0), // active low write control
+ .ram_wmask0 (openram_wmask0), // write mask
+ .ram_addr0 (openram_addr0),
+ .ram_din0 (openram_dout0),
+ .ram_dout0 (openram_din0)
);
endmodule // user_project_wrapper
diff --git a/wb_openram_wrapper b/wb_openram_wrapper
index 4cb1a24..1fbcc71 160000
--- a/wb_openram_wrapper
+++ b/wb_openram_wrapper
@@ -1 +1 @@
-Subproject commit 4cb1a246458691460893b9609bb8e470fc52a0a3
+Subproject commit 1fbcc714f22c76fa59a3ecc7fe1547b15da0e41e
