Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-003
/
slot-003
/
ee06e592339fba9d2e4f07c529b0ab18945badc3
commit
ee06e592339fba9d2e4f07c529b0ab18945badc3
[
log
]
[
tgz
]
author
embelon <78412338+embelon@users.noreply.github.com>
Mon Oct 18 21:32:44 2021 +0200
committer
embelon <78412338+embelon@users.noreply.github.com>
Mon Oct 18 21:32:44 2021 +0200
tree
464b6bb1e3c83ca1cc85c5cfbe70fefd79fb3a80
parent
23bf9e5a376ded1369aec98501f40ef47137f590
[
diff
]
Updated version of wb_openram_wrapper used.
verilog/rtl/user_project_wrapper.v
[
diff
]
wb_openram_wrapper
[
diff
]
2 files changed
tree: 464b6bb1e3c83ca1cc85c5cfbe70fefd79fb3a80
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
openram_testchip
wb_openram_wrapper
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.