Build results
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+<pre><font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls</font>
+<font color="#00AAAA">[INFO]: PDK: sky130A</font>
+<font color="#00AAAA">[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A</font>
+<font color="#00AAAA">[INFO]: Standard Cell Library: sky130_fd_sc_ls</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#AA5500">[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Preparing LEF Files</font>
+<font color="#00AAAA">[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef</font>
+<font color="#00AAAA">[INFO]: The number of available metal layers is 6</font>
+<font color="#00AAAA">[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5</font>
+<font color="#00AAAA">[INFO]: Merging LEF Files...</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: MACROs matched found: 399</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">NAND3X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND3X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX8.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX8.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX4.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX4.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">HAX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">HAX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">MUX2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">MUX2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">BUFX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">BUFX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NAND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">XNOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">XNOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INV.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INV.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#00AAAA">[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef</font>
+<font color="#00AAAA">[INFO]: Trimming Liberty...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Storing configs into config.tcl ...</font>
+<font color="#00AAAA">[INFO]: Preparation complete</font>
+<font color="#00AAAA">[INFO]: Running Synthesis...</font>
+<font color="#00AAAA">[INFO]: current step index: 1</font>
+
+<font color="#AAAAAA"> /----------------------------------------------------------------------------\</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | yosys -- Yosys Open SYnthesis Suite |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Permission to use, copy, modify, and/or distribute this software for any |</font>
+<font color="#AAAAAA"> | purpose with or without fee is hereby granted, provided that the above |</font>
+<font color="#AAAAAA"> | copyright notice and this permission notice appear in all copies. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |</font>
+<font color="#AAAAAA"> | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |</font>
+<font color="#AAAAAA"> | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |</font>
+<font color="#AAAAAA"> | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |</font>
+<font color="#AAAAAA"> | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |</font>
+<font color="#AAAAAA"> | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |</font>
+<font color="#AAAAAA"> | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> \----------------------------------------------------------------------------/</font>
+
+<font color="#AAAAAA"> Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox</font>
+
+<font color="#AAAAAA">1. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 386 cell types from liberty file.</font>
+
+<font color="#AAAAAA">2. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 19 cell types from liberty file.</font>
+
+<font color="#AAAAAA">3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-17.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:19.1-26.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:28.1-36.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:38.1-47.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:49.1-55.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX2'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX4'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\CLKBUF1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:73.1-81.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\HAX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:83.1-89.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INV'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:91.1-97.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-105.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:107.1-113.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX4'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:115.1-121.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX8'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:123.1-131.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\MUX2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:133.1-140.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:142.1-150.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:152.1-159.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:171.1-179.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:181.1-190.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:192.1-199.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:210.1-217.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XNOR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XOR2X1'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\user_proj_example'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">6. Generating Graphviz representation of design.</font>
+<font color="#AAAAAA">ERROR: Nothing there to show.</font>
+<font color="#AA0000">[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-yosys.log |& tee >&@stdout"</font>
+<font color="#AA0000">[ERROR]: Exit code: 1</font>
+<font color="#AA0000">[ERROR]: Last 10 lines:</font>
+<font color="#AA0000">child process exited abnormally</font>
+
+<font color="#AA0000">[ERROR]: Please check yosys log file</font>
+<font color="#AA0000">[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow failed for user_proj_example/13-06_17-48 in 0h0m17s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">No antenna report found.</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#AA0000">[ERROR]: Flow Failed.</font>
+
+<font color="#AAAAAA"> while executing</font>
+<font color="#AAAAAA">"try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l [index_file $::env(yosys_log_file_tag).log 0] |& tee $::env(TERMINAL_OUTPUT)"</font>
+<font color="#AAAAAA"> (procedure "run_yosys" line 34)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_yosys"</font>
+<font color="#AAAAAA"> (procedure "run_synthesis" line 9)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_synthesis"</font>
+<font color="#AAAAAA"> (procedure "run_non_interactive_mode" line 14)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_non_interactive_mode {*}$argv"</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {</font>
+ <font color="#AAAAAA">puts_info "Running interactively"</font>
+ <font color="#AAAAAA">if { [info exists arg_values(-file)..."</font>
+<font color="#AAAAAA"> (file "/openLANE_flow/flow.tcl" line 223)</font>
+<font color="#AAAAAA">make[1]: *** [Makefile:43: user_proj_example] Fehler 1</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen</font>
+<font color="#AAAAAA">make: *** [Makefile:71: user_proj_example] Fehler 2</font>
+<font color="#AAAAAA">Deployment done.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ vi user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ cd ..</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ ls</font>
+<font color="#AAAAAA">caravel cells</font> <font color="#AAAAAA">def docs env.sh gds</font> <font color="#AAAAAA">info.yaml lef</font> <font color="#AAAAAA">LICENSE mag maglef Makefile</font> <font color="#AAAAAA">openlane README.md scripts signoff spi verilog</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ vi openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ vi openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ vi openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-yosys.log</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ ls</font>
+<font color="#AAAAAA">caravel cells</font> <font color="#AAAAAA">def docs env.sh gds</font> <font color="#AAAAAA">info.yaml lef</font> <font color="#AAAAAA">LICENSE mag maglef Makefile</font> <font color="#AAAAAA">openlane README.md scripts signoff spi verilog</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ cd verilog/</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog$ ls</font>
+<font color="#AAAAAA">dv gl</font> <font color="#AAAAAA">rtl</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog$ cd rtl/</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ ls</font>
+<font color="#AAAAAA">uprj_netlists.v user_proj_cells.v user_project_wrapper.v user_proj_example.v</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi *</font>
+<font color="#AAAAAA">4 Dateien zum Editieren</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ l</font>
+<font color="#AAAAAA">l: Befehl nicht gefunden.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/generator.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/</font>
+<font color="#AAAAAA">cells.pl deploy2caravel.sh drcexpander.pl generator.pl magic.layers.out placement.pl removeDRCcells.pl testgen.pl viewer.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/testgen.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/cells.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/cells.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ grep ifdef *</font>
+<font color="#AAAAAA">uprj_netlists.v:`ifdef GL</font>
+<font color="#AAAAAA">user_project_wrapper.v:`ifdef USE_POWER_PINS</font>
+<font color="#AAAAAA">user_project_wrapper.v: `ifdef USE_POWER_PINS</font>
+<font color="#AAAAAA">user_proj_example.v:`ifdef USE_POWER_PINS</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi user_project_wrapper.v </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi ../../scripts/cells.pl </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ ls -al</font>
+<font color="#AAAAAA">insgesamt 24</font>
+<font color="#AAAAAA">drwxrwxr-x 2 philipp philipp 4096 Jun 13 20:11 .</font>
+<font color="#AAAAAA">drwxrwxr-x 5 philipp philipp 4096 Mai 13 21:22 ..</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 1069 Mai 13 21:22 uprj_netlists.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3955 Jun 13 19:48 user_proj_cells.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3635 Mai 13 21:22 user_project_wrapper.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 1191 Jun 13 19:48 user_proj_example.v</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi *</font>
+<font color="#AAAAAA">4 Dateien zum Editieren</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ ls -al</font>
+<font color="#AAAAAA">insgesamt 24</font>
+<font color="#AAAAAA">drwxrwxr-x 2 philipp philipp 4096 Jun 13 20:15 .</font>
+<font color="#AAAAAA">drwxrwxr-x 5 philipp philipp 4096 Mai 13 21:22 ..</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 1069 Mai 13 21:22 uprj_netlists.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3955 Jun 13 19:48 user_proj_cells.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3635 Mai 13 21:22 user_project_wrapper.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 1191 Jun 13 19:48 user_proj_example.v</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ echo $CARAVEL</font>
+<font color="#AAAAAA">/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ perl $CARAVEL/scripts/generator.pl >$CARAVEL/verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ perl $CARAVEL/scripts/generator.pl >$CARAVEL/verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/AND2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/AND2X2.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/AOI21X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/AOI22X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/BUFX2.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/BUFX4.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/CLKBUF1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/HAX1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/INV.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/INVX1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/INVX2.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/INVX4.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/INVX8.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/MUX2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/NAND2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/NAND3X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/NOR2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/NOR3X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/OAI21X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/OAI22X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/OR2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/OR2X2.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/XNOR2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 71.</font>
+<font color="#AAAAAA">Checking for /cells/mag/XOR2X1.mag</font>
+<font color="#AAAAAA">Use of uninitialized value in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/generator.pl line 72.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ echo $CARAVEL</font>
+<font color="#AAAAAA">/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi *^C</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ perl $CARAVEL/scripts/generator.pl >$CARAVEL/verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ vi user_proj_example.v </font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ ls -la</font>
+<font color="#AAAAAA">insgesamt 28</font>
+<font color="#AAAAAA">drwxrwxr-x 2 philipp philipp 4096 Jun 13 20:17 .</font>
+<font color="#AAAAAA">drwxrwxr-x 5 philipp philipp 4096 Mai 13 21:22 ..</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 1069 Mai 13 21:22 uprj_netlists.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3955 Jun 13 19:48 user_proj_cells.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 3635 Mai 13 21:22 user_project_wrapper.v</font>
+<font color="#AAAAAA">-rw-rw-r-- 1 philipp philipp 4794 Jun 13 20:17 user_proj_example.v</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog/rtl$ cd ..</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/verilog$ cd ..</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ ls</font>
+<font color="#AAAAAA">caravel cells</font> <font color="#AAAAAA">def docs env.sh gds</font> <font color="#AAAAAA">info.yaml lef</font> <font color="#AAAAAA">LICENSE mag maglef Makefile</font> <font color="#AAAAAA">openlane README.md scripts signoff spi verilog</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project$ cd scripts/</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ ls</font>
+<font color="#AAAAAA">cells.pl deploy2caravel.sh drcexpander.pl generator.pl magic.layers.out placement.pl removeDRCcells.pl testgen.pl viewer.pl</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ bash deploy2caravel.sh </font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lib“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef/orig“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/gds“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/mag“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">Cleaning up old files</font>
+<font color="#AAAAAA">Copying files that were created by StdCellLib</font>
+<font color="#AAAAAA">Removing cells with DRC issues left</font>
+<font color="#AAAAAA">Checking AND2X1</font>
+<font color="#AAAAAA">Checking AND2X2</font>
+<font color="#AAAAAA">Checking AOI21X1</font>
+<font color="#AAAAAA">Checking AOI22X1</font>
+<font color="#AAAAAA">Checking BUFX2</font>
+<font color="#AAAAAA">Checking BUFX4</font>
+<font color="#AAAAAA">Removing cell with 2 DRC issues:</font>
+<font color="#AAAAAA">Checking CLKBUF1</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking corr_XOR2X1</font>
+<font color="#AAAAAA">Error: Could not find DRC: /home/philipp/libresilicon/StdCellLib/corr_XOR2X1.drc No such file or directory</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking HAX1</font>
+<font color="#AAAAAA">Checking INV</font>
+<font color="#AAAAAA">Checking INVX1</font>
+<font color="#AAAAAA">Checking INVX2</font>
+<font color="#AAAAAA">Checking INVX4</font>
+<font color="#AAAAAA">Checking INVX8</font>
+<font color="#AAAAAA">Checking LATCH</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking MUX2X1</font>
+<font color="#AAAAAA">Checking NAND2X1</font>
+<font color="#AAAAAA">Checking NAND3X1</font>
+<font color="#AAAAAA">Checking NOR2X1</font>
+<font color="#AAAAAA">Checking NOR3X1</font>
+<font color="#AAAAAA">Removing cell with 60 DRC issues:</font>
+<font color="#AAAAAA">Checking OAI21X1</font>
+<font color="#AAAAAA">Checking OAI22X1</font>
+<font color="#AAAAAA">Checking OR2X1</font>
+<font color="#AAAAAA">Checking OR2X2</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking XNOR2X1</font>
+<font color="#AAAAAA">Checking XOR2X1</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Now cleaning up the files for Sky130</font>
+<font color="#AAAAAA">AND2X1.lef</font>
+<font color="#AAAAAA">AND2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X1.lef for cell AND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AND2X2.lef</font>
+<font color="#AAAAAA">AND2X2.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X2.lef for cell AND2X2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI21X1.lef</font>
+<font color="#AAAAAA">AOI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI21X1.lef for cell AOI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI22X1.lef</font>
+<font color="#AAAAAA">AOI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI22X1.lef for cell AOI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">BUFX2.lef</font>
+<font color="#AAAAAA">BUFX2.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output BUFX2.lef for cell BUFX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">HAX1.lef</font>
+<font color="#AAAAAA">HAX1.lef -> 15.84 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output HAX1.lef for cell HAX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INV.lef</font>
+<font color="#AAAAAA">INV.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INV.lef for cell INV:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX1.lef</font>
+<font color="#AAAAAA">INVX1.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX1.lef for cell INVX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX2.lef</font>
+<font color="#AAAAAA">INVX2.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX2.lef for cell INVX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX4.lef</font>
+<font color="#AAAAAA">INVX4.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 69 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX4.lef for cell INVX4:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX8.lef</font>
+<font color="#AAAAAA">INVX8.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 83 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX8.lef for cell INVX8:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">MUX2X1.lef</font>
+<font color="#AAAAAA">MUX2X1.lef -> 8.64 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output MUX2X1.lef for cell MUX2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND2X1.lef</font>
+<font color="#AAAAAA">NAND2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND2X1.lef for cell NAND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND3X1.lef</font>
+<font color="#AAAAAA">NAND3X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND3X1.lef for cell NAND3X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NOR2X1.lef</font>
+<font color="#AAAAAA">NOR2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NOR2X1.lef for cell NOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI21X1.lef</font>
+<font color="#AAAAAA">OAI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI21X1.lef for cell OAI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI22X1.lef</font>
+<font color="#AAAAAA">OAI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI22X1.lef for cell OAI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OR2X1.lef</font>
+<font color="#AAAAAA">OR2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Generating LEF output OR2X1.lef for cell OR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">XNOR2X1.lef</font>
+<font color="#AAAAAA">XNOR2X1.lef -> 10.08 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 80 lines.</font>
+<font color="#AAAAAA">Generating LEF output XNOR2X1.lef for cell XNOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA"> INFO: Reading base liberty: /home/philipp/libresilicon/StdCellLib/Catalog/libresilicon.libtemplate</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: BUFX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: HAX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INV.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX4.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX8.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: MUX2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND3X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: XNOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(BUFX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(HAX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INV)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX4)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX8)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(MUX2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND3X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NOR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(XNOR2X1)</font>
+<font color="#AAAAAA"> INFO: Number of cells in base: 19, number of cells in output: 19</font>
+<font color="#AAAAAA"> INFO: Write liberty: libresilicon.lib</font>
+<font color="#AAAAAA">Now generating the demo wafer, the macro placement and the test-bench</font>
+<font color="#AAAAAA">Now building the Caravel user-project</font>
+<font color="#AAAAAA">cd openlane && make user_proj_example</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird betreten</font>
+<font color="#AAAAAA">###############################################</font>
+<font color="#00AAAA">[INFO]: </font>
+ <font color="#00AAAA">___ ____ ___ ____ _ ____ ____ ___</font>
+ <font color="#00AAAA">/ \ | \ / _]| \ | | / || \ / _]</font>
+ <font color="#00AAAA">| || o ) [_ | _ || | | o || _ | / [_</font>
+ <font color="#00AAAA">| O || _/ _]| | || |___ | || | || _]</font>
+ <font color="#00AAAA">| || | | [_ | | || || _ || | || [_</font>
+ <font color="#00AAAA">\___/ |__| |_____||__|__||_____||__|__||__|__||_____|</font>
+
+
+<font color="#00AAAA">[INFO]: Version: v0.15</font>
+<font color="#00AAAA">[INFO]: Running non-interactively</font>
+<font color="#00AAAA">[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls</font>
+<font color="#00AAAA">[INFO]: PDK: sky130A</font>
+<font color="#00AAAA">[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A</font>
+<font color="#00AAAA">[INFO]: Standard Cell Library: sky130_fd_sc_ls</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#AA5500">[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Preparing LEF Files</font>
+<font color="#00AAAA">[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef</font>
+<font color="#00AAAA">[INFO]: The number of available metal layers is 6</font>
+<font color="#00AAAA">[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5</font>
+<font color="#00AAAA">[INFO]: Merging LEF Files...</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: MACROs matched found: 399</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">NAND3X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND3X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX8.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX8.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX4.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX4.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">HAX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">HAX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">MUX2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">MUX2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">BUFX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">BUFX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NAND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">XNOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">XNOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INV.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INV.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#00AAAA">[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef</font>
+<font color="#00AAAA">[INFO]: Trimming Liberty...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Storing configs into config.tcl ...</font>
+<font color="#00AAAA">[INFO]: Preparation complete</font>
+<font color="#00AAAA">[INFO]: Running Synthesis...</font>
+<font color="#00AAAA">[INFO]: current step index: 1</font>
+
+<font color="#AAAAAA"> /----------------------------------------------------------------------------\</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | yosys -- Yosys Open SYnthesis Suite |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Permission to use, copy, modify, and/or distribute this software for any |</font>
+<font color="#AAAAAA"> | purpose with or without fee is hereby granted, provided that the above |</font>
+<font color="#AAAAAA"> | copyright notice and this permission notice appear in all copies. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |</font>
+<font color="#AAAAAA"> | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |</font>
+<font color="#AAAAAA"> | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |</font>
+<font color="#AAAAAA"> | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |</font>
+<font color="#AAAAAA"> | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |</font>
+<font color="#AAAAAA"> | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |</font>
+<font color="#AAAAAA"> | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> \----------------------------------------------------------------------------/</font>
+
+<font color="#AAAAAA"> Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox</font>
+
+<font color="#AAAAAA">1. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 386 cell types from liberty file.</font>
+
+<font color="#AAAAAA">2. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 19 cell types from liberty file.</font>
+
+<font color="#AAAAAA">3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v</font>
+<font color="#AAAAAA">/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:278: ERROR: syntax error, unexpected $end</font>
+<font color="#AA0000">[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-yosys.log |& tee >&@stdout"</font>
+<font color="#AA0000">[ERROR]: Exit code: 1</font>
+<font color="#AA0000">[ERROR]: Last 10 lines:</font>
+<font color="#AA0000">child process exited abnormally</font>
+
+<font color="#AA0000">[ERROR]: Please check yosys log file</font>
+<font color="#AA0000">[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow failed for user_proj_example/13-06_18-19 in 0h0m17s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">No antenna report found.</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#AA0000">[ERROR]: Flow Failed.</font>
+
+<font color="#AAAAAA"> while executing</font>
+<font color="#AAAAAA">"try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l [index_file $::env(yosys_log_file_tag).log 0] |& tee $::env(TERMINAL_OUTPUT)"</font>
+<font color="#AAAAAA"> (procedure "run_yosys" line 34)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_yosys"</font>
+<font color="#AAAAAA"> (procedure "run_synthesis" line 9)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_synthesis"</font>
+<font color="#AAAAAA"> (procedure "run_non_interactive_mode" line 14)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_non_interactive_mode {*}$argv"</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {</font>
+ <font color="#AAAAAA">puts_info "Running interactively"</font>
+ <font color="#AAAAAA">if { [info exists arg_values(-file)..."</font>
+<font color="#AAAAAA"> (file "/openLANE_flow/flow.tcl" line 223)</font>
+<font color="#AAAAAA">make[1]: *** [Makefile:43: user_proj_example] Fehler 1</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen</font>
+<font color="#AAAAAA">make: *** [Makefile:71: user_proj_example] Fehler 2</font>
+<font color="#AAAAAA">Deployment done.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ bash deploy2caravel.sh </font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lib“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef/orig“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/gds“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/mag“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">Cleaning up old files</font>
+<font color="#AAAAAA">Copying files that were created by StdCellLib</font>
+<font color="#AAAAAA">Removing cells with DRC issues left</font>
+<font color="#AAAAAA">Checking AND2X1</font>
+<font color="#AAAAAA">Checking AND2X2</font>
+<font color="#AAAAAA">Checking AOI21X1</font>
+<font color="#AAAAAA">Checking AOI22X1</font>
+<font color="#AAAAAA">Checking BUFX2</font>
+<font color="#AAAAAA">Checking BUFX4</font>
+<font color="#AAAAAA">Removing cell with 2 DRC issues:</font>
+<font color="#AAAAAA">Checking CLKBUF1</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking corr_XOR2X1</font>
+<font color="#AAAAAA">Error: Could not find DRC: /home/philipp/libresilicon/StdCellLib/corr_XOR2X1.drc No such file or directory</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking HAX1</font>
+<font color="#AAAAAA">Checking INV</font>
+<font color="#AAAAAA">Checking INVX1</font>
+<font color="#AAAAAA">Checking INVX2</font>
+<font color="#AAAAAA">Checking INVX4</font>
+<font color="#AAAAAA">Checking INVX8</font>
+<font color="#AAAAAA">Checking LATCH</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking MUX2X1</font>
+<font color="#AAAAAA">Checking NAND2X1</font>
+<font color="#AAAAAA">Checking NAND3X1</font>
+<font color="#AAAAAA">Checking NOR2X1</font>
+<font color="#AAAAAA">Checking NOR3X1</font>
+<font color="#AAAAAA">Removing cell with 60 DRC issues:</font>
+<font color="#AAAAAA">Checking OAI21X1</font>
+<font color="#AAAAAA">Checking OAI22X1</font>
+<font color="#AAAAAA">Checking OR2X1</font>
+<font color="#AAAAAA">Checking OR2X2</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking XNOR2X1</font>
+<font color="#AAAAAA">Checking XOR2X1</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Now cleaning up the files for Sky130</font>
+<font color="#AAAAAA">AND2X1.lef</font>
+<font color="#AAAAAA">AND2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X1.lef for cell AND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AND2X2.lef</font>
+<font color="#AAAAAA">AND2X2.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X2.lef for cell AND2X2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI21X1.lef</font>
+<font color="#AAAAAA">AOI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI21X1.lef for cell AOI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI22X1.lef</font>
+<font color="#AAAAAA">AOI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI22X1.lef for cell AOI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">BUFX2.lef</font>
+<font color="#AAAAAA">BUFX2.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output BUFX2.lef for cell BUFX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">HAX1.lef</font>
+<font color="#AAAAAA">HAX1.lef -> 15.84 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output HAX1.lef for cell HAX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INV.lef</font>
+<font color="#AAAAAA">INV.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INV.lef for cell INV:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX1.lef</font>
+<font color="#AAAAAA">INVX1.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX1.lef for cell INVX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX2.lef</font>
+<font color="#AAAAAA">INVX2.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX2.lef for cell INVX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX4.lef</font>
+<font color="#AAAAAA">INVX4.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 69 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX4.lef for cell INVX4:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX8.lef</font>
+<font color="#AAAAAA">INVX8.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 83 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX8.lef for cell INVX8:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">MUX2X1.lef</font>
+<font color="#AAAAAA">MUX2X1.lef -> 8.64 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output MUX2X1.lef for cell MUX2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND2X1.lef</font>
+<font color="#AAAAAA">NAND2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND2X1.lef for cell NAND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND3X1.lef</font>
+<font color="#AAAAAA">NAND3X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND3X1.lef for cell NAND3X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NOR2X1.lef</font>
+<font color="#AAAAAA">NOR2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NOR2X1.lef for cell NOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI21X1.lef</font>
+<font color="#AAAAAA">OAI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI21X1.lef for cell OAI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI22X1.lef</font>
+<font color="#AAAAAA">OAI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI22X1.lef for cell OAI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OR2X1.lef</font>
+<font color="#AAAAAA">OR2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Generating LEF output OR2X1.lef for cell OR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">XNOR2X1.lef</font>
+<font color="#AAAAAA">XNOR2X1.lef -> 10.08 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 80 lines.</font>
+<font color="#AAAAAA">Generating LEF output XNOR2X1.lef for cell XNOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA"> INFO: Reading base liberty: /home/philipp/libresilicon/StdCellLib/Catalog/libresilicon.libtemplate</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: BUFX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: HAX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INV.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX4.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX8.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: MUX2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND3X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: XNOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(BUFX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(HAX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INV)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX4)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX8)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(MUX2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND3X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NOR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(XNOR2X1)</font>
+<font color="#AAAAAA"> INFO: Number of cells in base: 19, number of cells in output: 19</font>
+<font color="#AAAAAA"> INFO: Write liberty: libresilicon.lib</font>
+<font color="#AAAAAA">Now generating the demo wafer, the macro placement and the test-bench</font>
+<font color="#AAAAAA">Now building the Caravel user-project</font>
+<font color="#AAAAAA">cd openlane && make user_proj_example</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird betreten</font>
+<font color="#AAAAAA">###############################################</font>
+<font color="#00AAAA">[INFO]: </font>
+ <font color="#00AAAA">___ ____ ___ ____ _ ____ ____ ___</font>
+ <font color="#00AAAA">/ \ | \ / _]| \ | | / || \ / _]</font>
+ <font color="#00AAAA">| || o ) [_ | _ || | | o || _ | / [_</font>
+ <font color="#00AAAA">| O || _/ _]| | || |___ | || | || _]</font>
+ <font color="#00AAAA">| || | | [_ | | || || _ || | || [_</font>
+ <font color="#00AAAA">\___/ |__| |_____||__|__||_____||__|__||__|__||_____|</font>
+
+
+<font color="#00AAAA">[INFO]: Version: v0.15</font>
+<font color="#00AAAA">[INFO]: Running non-interactively</font>
+<font color="#00AAAA">[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls</font>
+<font color="#00AAAA">[INFO]: PDK: sky130A</font>
+<font color="#00AAAA">[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A</font>
+<font color="#00AAAA">[INFO]: Standard Cell Library: sky130_fd_sc_ls</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#AA5500">[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Preparing LEF Files</font>
+<font color="#00AAAA">[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef</font>
+<font color="#00AAAA">[INFO]: The number of available metal layers is 6</font>
+<font color="#00AAAA">[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5</font>
+<font color="#00AAAA">[INFO]: Merging LEF Files...</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: MACROs matched found: 399</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">NAND3X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND3X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX8.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX8.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX4.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX4.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">HAX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">HAX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">MUX2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">MUX2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">BUFX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">BUFX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NAND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">XNOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">XNOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INV.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INV.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#00AAAA">[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef</font>
+<font color="#00AAAA">[INFO]: Trimming Liberty...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Storing configs into config.tcl ...</font>
+<font color="#00AAAA">[INFO]: Preparation complete</font>
+<font color="#00AAAA">[INFO]: Running Synthesis...</font>
+<font color="#00AAAA">[INFO]: current step index: 1</font>
+
+<font color="#AAAAAA"> /----------------------------------------------------------------------------\</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | yosys -- Yosys Open SYnthesis Suite |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Permission to use, copy, modify, and/or distribute this software for any |</font>
+<font color="#AAAAAA"> | purpose with or without fee is hereby granted, provided that the above |</font>
+<font color="#AAAAAA"> | copyright notice and this permission notice appear in all copies. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |</font>
+<font color="#AAAAAA"> | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |</font>
+<font color="#AAAAAA"> | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |</font>
+<font color="#AAAAAA"> | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |</font>
+<font color="#AAAAAA"> | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |</font>
+<font color="#AAAAAA"> | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |</font>
+<font color="#AAAAAA"> | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> \----------------------------------------------------------------------------/</font>
+
+<font color="#AAAAAA"> Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox</font>
+
+<font color="#AAAAAA">1. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 386 cell types from liberty file.</font>
+
+<font color="#AAAAAA">2. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 19 cell types from liberty file.</font>
+
+<font color="#AAAAAA">3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-19.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:21.1-30.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:32.1-42.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:44.1-55.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-65.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX2'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX4'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\CLKBUF1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:87.1-97.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\HAX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-107.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INV'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:109.1-117.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-127.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:129.1-137.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX4'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:139.1-147.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX8'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:149.1-159.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\MUX2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:161.1-170.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:172.1-182.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:184.1-193.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:207.1-217.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:219.1-230.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:232.1-241.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:254.1-263.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XNOR2X1'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XOR2X1'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\user_proj_example'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">6. Generating Graphviz representation of design.</font>
+<font color="#AAAAAA">Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.</font>
+<font color="#AAAAAA">Dumping module user_proj_example to page 1.</font>
+
+<font color="#AAAAAA">7. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">7.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">7.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">8. Executing TRIBUF pass.</font>
+
+<font color="#AAAAAA">9. Executing SYNTH pass.</font>
+
+<font color="#AAAAAA">9.1. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.1.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.1.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.2. Executing PROC pass (convert processes to netlists).</font>
+
+<font color="#AAAAAA">9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).</font>
+<font color="#AAAAAA">Removed a total of 0 dead cases.</font>
+
+<font color="#AAAAAA">9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).</font>
+<font color="#AAAAAA">Removed 0 redundant assignments.</font>
+<font color="#AAAAAA">Promoted 0 assignments to connections.</font>
+
+<font color="#AAAAAA">9.2.4. Executing PROC_INIT pass (extract init attributes).</font>
+
+<font color="#AAAAAA">9.2.5. Executing PROC_ARST pass (detect async resets in processes).</font>
+
+<font color="#AAAAAA">9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).</font>
+
+<font color="#AAAAAA">9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).</font>
+
+<font color="#AAAAAA">9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).</font>
+
+<font color="#AAAAAA">9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.3. Executing FLATTEN pass (flatten design).</font>
+
+<font color="#AAAAAA">9.4. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.6. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">found and reported 179 problems.</font>
+
+<font color="#AAAAAA">9.7. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.7.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.7.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.7.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.8. Executing FSM pass (extract and optimize FSM).</font>
+
+<font color="#AAAAAA">9.8.1. Executing FSM_DETECT pass (finding FSMs in design).</font>
+
+<font color="#AAAAAA">9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).</font>
+
+<font color="#AAAAAA">9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).</font>
+
+<font color="#AAAAAA">9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).</font>
+
+<font color="#AAAAAA">9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).</font>
+
+<font color="#AAAAAA">9.9. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.9.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.9.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.9.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.10. Executing WREDUCE pass (reducing word size of cells).</font>
+
+<font color="#AAAAAA">9.11. Executing PEEPOPT pass (run peephole optimizers).</font>
+
+<font color="#AAAAAA">9.12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.13. Executing ALUMACC pass (create $alu and $macc cells).</font>
+<font color="#AAAAAA">Extracting $alu and $macc cells in module user_proj_example:</font>
+<font color="#AAAAAA"> created 0 $alu and 0 $macc cells.</font>
+
+<font color="#AAAAAA">9.14. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">9.15. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.15.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.15.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.15.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.16. Executing MEMORY pass.</font>
+
+<font color="#AAAAAA">9.16.1. Executing OPT_MEM pass (optimize memories).</font>
+<font color="#AAAAAA">Performed a total of 0 transformations.</font>
+
+<font color="#AAAAAA">9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).</font>
+
+<font color="#AAAAAA">9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).</font>
+
+<font color="#AAAAAA">9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).</font>
+
+<font color="#AAAAAA">9.17. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.18.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+<font color="#AAAAAA"><suppressed ~87 debug messages></font>
+
+<font color="#AAAAAA">9.18.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.18.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).</font>
+
+<font color="#AAAAAA">9.20. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.20.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.20.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.6. Executing OPT_SHARE pass.</font>
+
+<font color="#AAAAAA">9.20.7. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.20.9. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.10. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_bool_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_logic_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_compare_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_various'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_registers'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_shiftx'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_fa'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lcu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_macc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alumacc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_u'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_trunc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_div'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_mod'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_floor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_divfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_modfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pow'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pmux'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lut'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">9.21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~67 debug messages></font>
+
+<font color="#AAAAAA">9.22. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.22.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.22.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.22.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.22.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.23. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">9.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">9.24. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.24.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.24.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.24.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.24.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.25. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.25.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.25.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.26. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">9.27. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">10. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">11. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">11.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">11.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">11.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">11.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">13. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">mapping tbuf</font>
+
+<font color="#AAAAAA">14. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_TBUF_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">14.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">15. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">16. Executing MUXCOVER pass (mapping to wider MUXes).</font>
+<font color="#AAAAAA">Covering MUX trees in module user_proj_example..</font>
+<font color="#AAAAAA"> Treeifying 0 MUXes:</font>
+<font color="#AAAAAA"> Finished treeification: Found 0 trees.</font>
+<font color="#AAAAAA"> Covering trees:</font>
+<font color="#AAAAAA"> Added a total of 0 decoder MUXes.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">17. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">17.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX4_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">17.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">18. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">19. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">19.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">19.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">20. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">21.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_P_'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_N_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~4 debug messages></font>
+
+<font color="#AAAAAA">22. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">23. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfxtp_2 (noninv, pins=3, area=28.77) is a direct match for cell type $_DFF_P_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfrtp_2 (noninv, pins=4, area=38.36) is a direct match for cell type $_DFF_PN0_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfstp_2 (noninv, pins=4, area=39.96) is a direct match for cell type $_DFF_PN1_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfbbn_2 (noninv, pins=6, area=47.95) is a direct match for cell type $_DFFSR_NNN_.</font>
+<font color="#AAAAAA"> final dff cell mappings:</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_N_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN1_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPP_</font>
+
+<font color="#AAAAAA">23.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).</font>
+<font color="#AAAAAA">Mapping DFF cells in module `\user_proj_example':</font>
+
+<font color="#AAAAAA">24. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">[INFO]: ABC: WireLoad : S_4</font>
+
+<font color="#AAAAAA">25. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">25.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-semHpd/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">26. Executing SETUNDEF pass (replace undef values with defined constants).</font>
+
+<font color="#AAAAAA">27. Executing HILOMAP pass (mapping to constant drivers).</font>
+
+<font color="#AAAAAA">28. Executing SPLITNETS pass (splitting up multi-bit signals).</font>
+
+<font color="#AAAAAA">29. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+<font color="#AAAAAA">Removed 0 unused cells and 217 unused wires.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">30. Executing INSBUF pass (insert buffer cells for connected wires).</font>
+
+<font color="#AAAAAA">31. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">32. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 236</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+<font color="#AAAAAA"> sky130_fd_sc_ls__conb_1 217</font>
+
+<font color="#AAAAAA"> Area for cell type \AND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AND2X2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \BUFX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \HAX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INV is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX4 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX8 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \MUX2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND3X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NOR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \XNOR2X1 is unknown!</font>
+
+<font color="#AAAAAA"> Chip area for module '\user_proj_example': 1040.558400</font>
+
+<font color="#AAAAAA">33. Executing Verilog backend.</font>
+<font color="#AAAAAA">Dumping module `\user_proj_example'.</font>
+
+<font color="#AAAAAA">Warnings: 179 unique messages, 179 total</font>
+<font color="#AAAAAA">End of script. Logfile hash: 76decf997b, CPU: user 22.05s system 0.83s, MEM: 386.61 MB peak</font>
+<font color="#AAAAAA">Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+<font color="#AAAAAA">Time spent: 38% 4x read_liberty (8 sec), 36% 4x stat (8 sec), 21% 1x dfflibmap (4 sec), ...</font>
+<font color="#00AAAA">[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v</font>
+<font color="#00AAAA">[INFO]: Running Static Timing Analysis...</font>
+<font color="#00AAAA">[INFO]: current step index: 2</font>
+<font color="#AAAAAA">OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.</font>
+<font color="#AAAAAA">License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html></font>
+
+<font color="#AAAAAA">This is free software, and you are free to change and redistribute it</font>
+<font color="#AAAAAA">under certain conditions; type `show_copying' for details. </font>
+<font color="#AAAAAA">This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 671, module AND2X1 not found. Creating black box for AND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 676, module AND2X2 not found. Creating black box for AND2X2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 681, module AOI21X1 not found. Creating black box for AOI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 687, module AOI22X1 not found. Creating black box for AOI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 694, module BUFX2 not found. Creating black box for BUFX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 698, module HAX1 not found. Creating black box for HAX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 704, module INV not found. Creating black box for INV.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 708, module INVX1 not found. Creating black box for INVX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 712, module INVX2 not found. Creating black box for INVX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 716, module INVX4 not found. Creating black box for INVX4.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 720, module INVX8 not found. Creating black box for INVX8.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 724, module MUX2X1 not found. Creating black box for MUX2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 730, module NAND2X1 not found. Creating black box for NAND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 735, module NAND3X1 not found. Creating black box for NAND3X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 741, module NOR2X1 not found. Creating black box for NOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 746, module OAI21X1 not found. Creating black box for OAI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 752, module OAI22X1 not found. Creating black box for OAI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 759, module OR2X1 not found. Creating black box for OR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 764, module XNOR2X1 not found. Creating black box for XNOR2X1.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#00AAAA">[INFO]: Synthesis was successful</font>
+<font color="#00AAAA">[INFO]: Running Floorplanning...</font>
+<font color="#00AAAA">[INFO]: Running Initial Floorplanning...</font>
+<font color="#00AAAA">[INFO]: current step index: 3</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master BUFX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master HAX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INV has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX4 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX8 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master MUX2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND3X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master XNOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[INFO IFP-0001] Added 82 rows of 601 sites.</font>
+<font color="#00AAAA">[INFO]: Core area width: 288.48</font>
+<font color="#00AAAA">[INFO]: Core area height: 273.36</font>
+<font color="#00AAAA">[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#00AAAA">[INFO]: current step index: 4</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Top-level design name: user_proj_example</font>
+<font color="#AAAAAA">Block boundaries: 0 0 300000 300000</font>
+<font color="#AAAAAA">Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Manual Macro Placement...</font>
+<font color="#00AAAA">[INFO]: current step index: 5</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Placing the following macros:</font>
+<font color="#AAAAAA">{'AND2X1': ['38400', '23310', 'N'], 'AND2X2': ['38400', '29970', 'N'], 'AOI21X1': ['38400', '36630', 'N'], 'AOI22X1': ['38400', '43290', 'N'], 'BUFX2': ['38400', '49950', 'N'], 'BUFX4': ['38400', '56610', 'N'], 'CLKBUF1': ['38400', '63270', 'N'], 'HAX1': ['38400', '69930', 'N'], 'INV': ['38400', '76590', 'N'], 'INVX1': ['38400', '83250', 'N'], 'INVX2': ['38400', '89910', 'N'], 'INVX4': ['38400', '96570', 'N'], 'INVX8': ['38400', '103230', 'N'], 'MUX2X1': ['38400', '109890', 'N'], 'NAND2X1': ['38400', '116550', 'N'], 'NAND3X1': ['38400', '123210', 'N'], 'NOR2X1': ['38400', '129870', 'N'], 'NOR3X1': ['38400', '136530', 'N'], 'OAI21X1': ['38400', '143190', 'N'], 'OAI22X1': ['38400', '149850', 'N'], 'OR2X1': ['38400', '156510', 'N'], 'OR2X2': ['38400', '163170', 'N'], 'XNOR2X1': ['38400', '169830', 'N'], 'XOR2X1': ['38400', '176490', 'N']}</font>
+<font color="#AAAAAA">Design name: user_proj_example</font>
+<font color="#AAAAAA">Placing AND2X1</font>
+<font color="#AAAAAA">Placing AND2X2</font>
+<font color="#AAAAAA">Placing AOI21X1</font>
+<font color="#AAAAAA">Placing AOI22X1</font>
+<font color="#AAAAAA">Placing BUFX2</font>
+<font color="#AAAAAA">Placing HAX1</font>
+<font color="#AAAAAA">Placing INV</font>
+<font color="#AAAAAA">Placing INVX1</font>
+<font color="#AAAAAA">Placing INVX2</font>
+<font color="#AAAAAA">Placing INVX4</font>
+<font color="#AAAAAA">Placing INVX8</font>
+<font color="#AAAAAA">Placing MUX2X1</font>
+<font color="#AAAAAA">Placing NAND2X1</font>
+<font color="#AAAAAA">Placing NAND3X1</font>
+<font color="#AAAAAA">Placing NOR2X1</font>
+<font color="#AAAAAA">Placing OAI21X1</font>
+<font color="#AAAAAA">Placing OAI22X1</font>
+<font color="#AAAAAA">Placing OR2X1</font>
+<font color="#AAAAAA">Placing XNOR2X1</font>
+<font color="#AAAAAA">Traceback (most recent call last):</font>
+<font color="#AAAAAA"> File "/openLANE_flow/scripts/manual_macro_place.py", line 119, in <module></font>
+<font color="#AAAAAA"> assert not macros, ("Macros not found:", macros)</font>
+<font color="#AAAAAA">AssertionError: ('Macros not found:', {'BUFX4': ['38400', '56610', 'N'], 'CLKBUF1': ['38400', '63270', 'N'], 'NOR3X1': ['38400', '136530', 'N'], 'OR2X2': ['38400', '163170', 'N'], 'XOR2X1': ['38400', '176490', 'N']})</font>
+<font color="#AA0000">[ERROR]: during executing: "python3 /openLANE_flow/scripts/manual_macro_place.py -l /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef -id /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def -o /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def -c /project/openlane/user_proj_example/runs/user_proj_example/tmp/macro_placement.cfg -f |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/5-macro_placement.log"</font>
+<font color="#AA0000">[ERROR]: Exit code: 1</font>
+<font color="#AA0000">[ERROR]: Last 10 lines:</font>
+<font color="#AA0000">child process exited abnormally</font>
+
+<font color="#AA0000">[ERROR]: Please check python3 log file</font>
+<font color="#AA0000">[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow failed for user_proj_example/13-06_18-37 in 0h1m0s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">No antenna report found.</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#AA0000">[ERROR]: Flow Failed.</font>
+
+<font color="#AAAAAA"> while executing</font>
+<font color="#AAAAAA">"try_catch python3 $::env(SCRIPTS_DIR)/manual_macro_place.py -l $::env(MERGED_LEF) -id $::env(CURRENT_DEF) -o ${fbasename}.macro_placement.def -c $::en..."</font>
+<font color="#AAAAAA"> (procedure "manual_macro_placement" line 6)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"manual_macro_placement f"</font>
+<font color="#AAAAAA"> (procedure "run_floorplan" line 29)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_floorplan"</font>
+<font color="#AAAAAA"> (procedure "run_non_interactive_mode" line 15)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_non_interactive_mode {*}$argv"</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {</font>
+ <font color="#AAAAAA">puts_info "Running interactively"</font>
+ <font color="#AAAAAA">if { [info exists arg_values(-file)..."</font>
+<font color="#AAAAAA"> (file "/openLANE_flow/flow.tcl" line 223)</font>
+<font color="#AAAAAA">make[1]: *** [Makefile:43: user_proj_example] Fehler 1</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen</font>
+<font color="#AAAAAA">make: *** [Makefile:71: user_proj_example] Fehler 2</font>
+<font color="#AAAAAA">Deployment done.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ bash deploy2caravel.sh </font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lib“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef/orig“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/gds“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/mag“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">Cleaning up old files</font>
+<font color="#AAAAAA">Copying files that were created by StdCellLib</font>
+<font color="#AAAAAA">Removing cells with DRC issues left</font>
+<font color="#AAAAAA">Checking AND2X1</font>
+<font color="#AAAAAA">Checking AND2X2</font>
+<font color="#AAAAAA">Checking AOI21X1</font>
+<font color="#AAAAAA">Checking AOI22X1</font>
+<font color="#AAAAAA">Checking BUFX2</font>
+<font color="#AAAAAA">Checking BUFX4</font>
+<font color="#AAAAAA">Removing cell with 2 DRC issues:</font>
+<font color="#AAAAAA">Checking CLKBUF1</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking corr_XOR2X1</font>
+<font color="#AAAAAA">Error: Could not find DRC: /home/philipp/libresilicon/StdCellLib/corr_XOR2X1.drc No such file or directory</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking HAX1</font>
+<font color="#AAAAAA">Checking INV</font>
+<font color="#AAAAAA">Checking INVX1</font>
+<font color="#AAAAAA">Checking INVX2</font>
+<font color="#AAAAAA">Checking INVX4</font>
+<font color="#AAAAAA">Checking INVX8</font>
+<font color="#AAAAAA">Checking LATCH</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking MUX2X1</font>
+<font color="#AAAAAA">Checking NAND2X1</font>
+<font color="#AAAAAA">Checking NAND3X1</font>
+<font color="#AAAAAA">Checking NOR2X1</font>
+<font color="#AAAAAA">Checking NOR3X1</font>
+<font color="#AAAAAA">Removing cell with 60 DRC issues:</font>
+<font color="#AAAAAA">Checking OAI21X1</font>
+<font color="#AAAAAA">Checking OAI22X1</font>
+<font color="#AAAAAA">Checking OR2X1</font>
+<font color="#AAAAAA">Checking OR2X2</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking XNOR2X1</font>
+<font color="#AAAAAA">Checking XOR2X1</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Now cleaning up the files for Sky130</font>
+<font color="#AAAAAA">AND2X1.lef</font>
+<font color="#AAAAAA">AND2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X1.lef for cell AND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AND2X2.lef</font>
+<font color="#AAAAAA">AND2X2.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X2.lef for cell AND2X2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI21X1.lef</font>
+<font color="#AAAAAA">AOI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI21X1.lef for cell AOI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI22X1.lef</font>
+<font color="#AAAAAA">AOI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI22X1.lef for cell AOI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">BUFX2.lef</font>
+<font color="#AAAAAA">BUFX2.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output BUFX2.lef for cell BUFX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">HAX1.lef</font>
+<font color="#AAAAAA">HAX1.lef -> 15.84 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output HAX1.lef for cell HAX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INV.lef</font>
+<font color="#AAAAAA">INV.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INV.lef for cell INV:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX1.lef</font>
+<font color="#AAAAAA">INVX1.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX1.lef for cell INVX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX2.lef</font>
+<font color="#AAAAAA">INVX2.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX2.lef for cell INVX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX4.lef</font>
+<font color="#AAAAAA">INVX4.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 69 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX4.lef for cell INVX4:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX8.lef</font>
+<font color="#AAAAAA">INVX8.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 83 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX8.lef for cell INVX8:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">MUX2X1.lef</font>
+<font color="#AAAAAA">MUX2X1.lef -> 8.64 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output MUX2X1.lef for cell MUX2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND2X1.lef</font>
+<font color="#AAAAAA">NAND2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND2X1.lef for cell NAND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND3X1.lef</font>
+<font color="#AAAAAA">NAND3X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND3X1.lef for cell NAND3X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NOR2X1.lef</font>
+<font color="#AAAAAA">NOR2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NOR2X1.lef for cell NOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI21X1.lef</font>
+<font color="#AAAAAA">OAI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI21X1.lef for cell OAI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI22X1.lef</font>
+<font color="#AAAAAA">OAI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI22X1.lef for cell OAI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OR2X1.lef</font>
+<font color="#AAAAAA">OR2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Generating LEF output OR2X1.lef for cell OR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">XNOR2X1.lef</font>
+<font color="#AAAAAA">XNOR2X1.lef -> 10.08 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 80 lines.</font>
+<font color="#AAAAAA">Generating LEF output XNOR2X1.lef for cell XNOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA"> INFO: Reading base liberty: /home/philipp/libresilicon/StdCellLib/Catalog/libresilicon.libtemplate</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: BUFX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: HAX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INV.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX4.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX8.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: MUX2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND3X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: XNOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(BUFX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(HAX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INV)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX4)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX8)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(MUX2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND3X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NOR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(XNOR2X1)</font>
+<font color="#AAAAAA"> INFO: Number of cells in base: 19, number of cells in output: 19</font>
+<font color="#AAAAAA"> INFO: Write liberty: libresilicon.lib</font>
+<font color="#AAAAAA">Now generating the demo wafer, the macro placement and the test-bench</font>
+<font color="#AAAAAA">Now building the Caravel user-project</font>
+<font color="#AAAAAA">cd openlane && make user_proj_example</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird betreten</font>
+<font color="#AAAAAA">###############################################</font>
+<font color="#00AAAA">[INFO]: </font>
+ <font color="#00AAAA">___ ____ ___ ____ _ ____ ____ ___</font>
+ <font color="#00AAAA">/ \ | \ / _]| \ | | / || \ / _]</font>
+ <font color="#00AAAA">| || o ) [_ | _ || | | o || _ | / [_</font>
+ <font color="#00AAAA">| O || _/ _]| | || |___ | || | || _]</font>
+ <font color="#00AAAA">| || | | [_ | | || || _ || | || [_</font>
+ <font color="#00AAAA">\___/ |__| |_____||__|__||_____||__|__||__|__||_____|</font>
+
+
+<font color="#00AAAA">[INFO]: Version: v0.15</font>
+<font color="#00AAAA">[INFO]: Running non-interactively</font>
+<font color="#00AAAA">[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls</font>
+<font color="#00AAAA">[INFO]: PDK: sky130A</font>
+<font color="#00AAAA">[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A</font>
+<font color="#00AAAA">[INFO]: Standard Cell Library: sky130_fd_sc_ls</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#AA5500">[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Preparing LEF Files</font>
+<font color="#00AAAA">[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef</font>
+<font color="#00AAAA">[INFO]: The number of available metal layers is 6</font>
+<font color="#00AAAA">[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5</font>
+<font color="#00AAAA">[INFO]: Merging LEF Files...</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: MACROs matched found: 399</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">NAND3X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND3X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX8.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX8.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX4.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX4.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">HAX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">HAX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">MUX2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">MUX2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">BUFX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">BUFX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NAND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">XNOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">XNOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INV.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INV.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#00AAAA">[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef</font>
+<font color="#00AAAA">[INFO]: Trimming Liberty...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Storing configs into config.tcl ...</font>
+<font color="#00AAAA">[INFO]: Preparation complete</font>
+<font color="#00AAAA">[INFO]: Running Synthesis...</font>
+<font color="#00AAAA">[INFO]: current step index: 1</font>
+
+<font color="#AAAAAA"> /----------------------------------------------------------------------------\</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | yosys -- Yosys Open SYnthesis Suite |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Permission to use, copy, modify, and/or distribute this software for any |</font>
+<font color="#AAAAAA"> | purpose with or without fee is hereby granted, provided that the above |</font>
+<font color="#AAAAAA"> | copyright notice and this permission notice appear in all copies. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |</font>
+<font color="#AAAAAA"> | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |</font>
+<font color="#AAAAAA"> | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |</font>
+<font color="#AAAAAA"> | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |</font>
+<font color="#AAAAAA"> | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |</font>
+<font color="#AAAAAA"> | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |</font>
+<font color="#AAAAAA"> | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> \----------------------------------------------------------------------------/</font>
+
+<font color="#AAAAAA"> Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox</font>
+
+<font color="#AAAAAA">1. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 386 cell types from liberty file.</font>
+
+<font color="#AAAAAA">2. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 19 cell types from liberty file.</font>
+
+<font color="#AAAAAA">3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-19.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:21.1-30.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:32.1-42.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:44.1-55.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-65.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:67.1-77.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\HAX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:79.1-87.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INV'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:89.1-97.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-107.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:109.1-117.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX4'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-127.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX8'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:129.1-139.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\MUX2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:141.1-150.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:152.1-162.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:164.1-173.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:175.1-185.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:187.1-198.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:200.1-209.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:211.1-220.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XNOR2X1'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\user_proj_example'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">6. Generating Graphviz representation of design.</font>
+<font color="#AAAAAA">Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.</font>
+<font color="#AAAAAA">Dumping module user_proj_example to page 1.</font>
+
+<font color="#AAAAAA">7. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">7.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">7.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">8. Executing TRIBUF pass.</font>
+
+<font color="#AAAAAA">9. Executing SYNTH pass.</font>
+
+<font color="#AAAAAA">9.1. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.1.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.1.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.2. Executing PROC pass (convert processes to netlists).</font>
+
+<font color="#AAAAAA">9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).</font>
+<font color="#AAAAAA">Removed a total of 0 dead cases.</font>
+
+<font color="#AAAAAA">9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).</font>
+<font color="#AAAAAA">Removed 0 redundant assignments.</font>
+<font color="#AAAAAA">Promoted 0 assignments to connections.</font>
+
+<font color="#AAAAAA">9.2.4. Executing PROC_INIT pass (extract init attributes).</font>
+
+<font color="#AAAAAA">9.2.5. Executing PROC_ARST pass (detect async resets in processes).</font>
+
+<font color="#AAAAAA">9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).</font>
+
+<font color="#AAAAAA">9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).</font>
+
+<font color="#AAAAAA">9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).</font>
+
+<font color="#AAAAAA">9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.3. Executing FLATTEN pass (flatten design).</font>
+
+<font color="#AAAAAA">9.4. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.6. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">found and reported 179 problems.</font>
+
+<font color="#AAAAAA">9.7. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.7.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.7.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.7.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.8. Executing FSM pass (extract and optimize FSM).</font>
+
+<font color="#AAAAAA">9.8.1. Executing FSM_DETECT pass (finding FSMs in design).</font>
+
+<font color="#AAAAAA">9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).</font>
+
+<font color="#AAAAAA">9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).</font>
+
+<font color="#AAAAAA">9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).</font>
+
+<font color="#AAAAAA">9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).</font>
+
+<font color="#AAAAAA">9.9. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.9.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.9.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.9.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.10. Executing WREDUCE pass (reducing word size of cells).</font>
+
+<font color="#AAAAAA">9.11. Executing PEEPOPT pass (run peephole optimizers).</font>
+
+<font color="#AAAAAA">9.12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.13. Executing ALUMACC pass (create $alu and $macc cells).</font>
+<font color="#AAAAAA">Extracting $alu and $macc cells in module user_proj_example:</font>
+<font color="#AAAAAA"> created 0 $alu and 0 $macc cells.</font>
+
+<font color="#AAAAAA">9.14. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">9.15. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.15.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.15.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.15.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.16. Executing MEMORY pass.</font>
+
+<font color="#AAAAAA">9.16.1. Executing OPT_MEM pass (optimize memories).</font>
+<font color="#AAAAAA">Performed a total of 0 transformations.</font>
+
+<font color="#AAAAAA">9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).</font>
+
+<font color="#AAAAAA">9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).</font>
+
+<font color="#AAAAAA">9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).</font>
+
+<font color="#AAAAAA">9.17. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.18.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+<font color="#AAAAAA"><suppressed ~87 debug messages></font>
+
+<font color="#AAAAAA">9.18.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.18.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).</font>
+
+<font color="#AAAAAA">9.20. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.20.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.20.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.6. Executing OPT_SHARE pass.</font>
+
+<font color="#AAAAAA">9.20.7. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.20.9. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.10. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_bool_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_logic_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_compare_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_various'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_registers'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_shiftx'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_fa'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lcu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_macc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alumacc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_u'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_trunc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_div'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_mod'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_floor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_divfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_modfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pow'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pmux'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lut'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">9.21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~67 debug messages></font>
+
+<font color="#AAAAAA">9.22. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.22.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.22.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.22.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.22.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.23. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">9.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">9.24. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.24.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.24.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.24.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.24.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.25. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.25.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.25.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.26. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">9.27. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">10. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">11. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">11.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">11.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">11.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">11.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">13. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">mapping tbuf</font>
+
+<font color="#AAAAAA">14. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_TBUF_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">14.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">15. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">16. Executing MUXCOVER pass (mapping to wider MUXes).</font>
+<font color="#AAAAAA">Covering MUX trees in module user_proj_example..</font>
+<font color="#AAAAAA"> Treeifying 0 MUXes:</font>
+<font color="#AAAAAA"> Finished treeification: Found 0 trees.</font>
+<font color="#AAAAAA"> Covering trees:</font>
+<font color="#AAAAAA"> Added a total of 0 decoder MUXes.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">17. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">17.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX4_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">17.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">18. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">19. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">19.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">19.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">20. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">21.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_P_'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_N_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~4 debug messages></font>
+
+<font color="#AAAAAA">22. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">23. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfxtp_2 (noninv, pins=3, area=28.77) is a direct match for cell type $_DFF_P_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfrtp_2 (noninv, pins=4, area=38.36) is a direct match for cell type $_DFF_PN0_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfstp_2 (noninv, pins=4, area=39.96) is a direct match for cell type $_DFF_PN1_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfbbn_2 (noninv, pins=6, area=47.95) is a direct match for cell type $_DFFSR_NNN_.</font>
+<font color="#AAAAAA"> final dff cell mappings:</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_N_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN1_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPP_</font>
+
+<font color="#AAAAAA">23.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).</font>
+<font color="#AAAAAA">Mapping DFF cells in module `\user_proj_example':</font>
+
+<font color="#AAAAAA">24. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">[INFO]: ABC: WireLoad : S_4</font>
+
+<font color="#AAAAAA">25. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">25.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-lDi3pC/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">26. Executing SETUNDEF pass (replace undef values with defined constants).</font>
+
+<font color="#AAAAAA">27. Executing HILOMAP pass (mapping to constant drivers).</font>
+
+<font color="#AAAAAA">28. Executing SPLITNETS pass (splitting up multi-bit signals).</font>
+
+<font color="#AAAAAA">29. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+<font color="#AAAAAA">Removed 0 unused cells and 217 unused wires.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">30. Executing INSBUF pass (insert buffer cells for connected wires).</font>
+
+<font color="#AAAAAA">31. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">32. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 236</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+<font color="#AAAAAA"> sky130_fd_sc_ls__conb_1 217</font>
+
+<font color="#AAAAAA"> Area for cell type \AND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AND2X2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \BUFX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \HAX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INV is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX4 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX8 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \MUX2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND3X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NOR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \XNOR2X1 is unknown!</font>
+
+<font color="#AAAAAA"> Chip area for module '\user_proj_example': 1040.558400</font>
+
+<font color="#AAAAAA">33. Executing Verilog backend.</font>
+<font color="#AAAAAA">Dumping module `\user_proj_example'.</font>
+
+<font color="#AAAAAA">Warnings: 179 unique messages, 179 total</font>
+<font color="#AAAAAA">End of script. Logfile hash: ed1a35b6ad, CPU: user 21.56s system 0.86s, MEM: 386.82 MB peak</font>
+<font color="#AAAAAA">Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+<font color="#AAAAAA">Time spent: 37% 4x read_liberty (8 sec), 37% 4x stat (8 sec), 21% 1x dfflibmap (4 sec), ...</font>
+<font color="#00AAAA">[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v</font>
+<font color="#00AAAA">[INFO]: Running Static Timing Analysis...</font>
+<font color="#00AAAA">[INFO]: current step index: 2</font>
+<font color="#AAAAAA">OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.</font>
+<font color="#AAAAAA">License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html></font>
+
+<font color="#AAAAAA">This is free software, and you are free to change and redistribute it</font>
+<font color="#AAAAAA">under certain conditions; type `show_copying' for details. </font>
+<font color="#AAAAAA">This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 671, module AND2X1 not found. Creating black box for AND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 676, module AND2X2 not found. Creating black box for AND2X2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 681, module AOI21X1 not found. Creating black box for AOI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 687, module AOI22X1 not found. Creating black box for AOI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 694, module BUFX2 not found. Creating black box for BUFX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 698, module HAX1 not found. Creating black box for HAX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 704, module INV not found. Creating black box for INV.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 708, module INVX1 not found. Creating black box for INVX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 712, module INVX2 not found. Creating black box for INVX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 716, module INVX4 not found. Creating black box for INVX4.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 720, module INVX8 not found. Creating black box for INVX8.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 724, module MUX2X1 not found. Creating black box for MUX2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 730, module NAND2X1 not found. Creating black box for NAND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 735, module NAND3X1 not found. Creating black box for NAND3X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 741, module NOR2X1 not found. Creating black box for NOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 746, module OAI21X1 not found. Creating black box for OAI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 752, module OAI22X1 not found. Creating black box for OAI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 759, module OR2X1 not found. Creating black box for OR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 764, module XNOR2X1 not found. Creating black box for XNOR2X1.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#00AAAA">[INFO]: Synthesis was successful</font>
+<font color="#00AAAA">[INFO]: Running Floorplanning...</font>
+<font color="#00AAAA">[INFO]: Running Initial Floorplanning...</font>
+<font color="#00AAAA">[INFO]: current step index: 3</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master BUFX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master HAX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INV has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX4 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX8 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master MUX2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND3X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master XNOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[INFO IFP-0001] Added 82 rows of 601 sites.</font>
+<font color="#00AAAA">[INFO]: Core area width: 288.48</font>
+<font color="#00AAAA">[INFO]: Core area height: 273.36</font>
+<font color="#00AAAA">[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#00AAAA">[INFO]: current step index: 4</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Top-level design name: user_proj_example</font>
+<font color="#AAAAAA">Block boundaries: 0 0 300000 300000</font>
+<font color="#AAAAAA">Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Manual Macro Placement...</font>
+<font color="#00AAAA">[INFO]: current step index: 5</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Placing the following macros:</font>
+<font color="#AAAAAA">{'AND2X1': ['38400', '23310', 'N'], 'AND2X2': ['38400', '29970', 'N'], 'AOI21X1': ['38400', '36630', 'N'], 'AOI22X1': ['38400', '43290', 'N'], 'BUFX2': ['38400', '49950', 'N'], 'BUFX4': ['38400', '56610', 'N'], 'CLKBUF1': ['38400', '63270', 'N'], 'HAX1': ['38400', '69930', 'N'], 'INV': ['38400', '76590', 'N'], 'INVX1': ['38400', '83250', 'N'], 'INVX2': ['38400', '89910', 'N'], 'INVX4': ['38400', '96570', 'N'], 'INVX8': ['38400', '103230', 'N'], 'MUX2X1': ['38400', '109890', 'N'], 'NAND2X1': ['38400', '116550', 'N'], 'NAND3X1': ['38400', '123210', 'N'], 'NOR2X1': ['38400', '129870', 'N'], 'NOR3X1': ['38400', '136530', 'N'], 'OAI21X1': ['38400', '143190', 'N'], 'OAI22X1': ['38400', '149850', 'N'], 'OR2X1': ['38400', '156510', 'N'], 'OR2X2': ['38400', '163170', 'N'], 'XNOR2X1': ['38400', '169830', 'N'], 'XOR2X1': ['38400', '176490', 'N']}</font>
+<font color="#AAAAAA">Design name: user_proj_example</font>
+<font color="#AAAAAA">Placing AND2X1</font>
+<font color="#AAAAAA">Placing AND2X2</font>
+<font color="#AAAAAA">Placing AOI21X1</font>
+<font color="#AAAAAA">Placing AOI22X1</font>
+<font color="#AAAAAA">Placing BUFX2</font>
+<font color="#AAAAAA">Placing HAX1</font>
+<font color="#AAAAAA">Placing INV</font>
+<font color="#AAAAAA">Placing INVX1</font>
+<font color="#AAAAAA">Placing INVX2</font>
+<font color="#AAAAAA">Placing INVX4</font>
+<font color="#AAAAAA">Placing INVX8</font>
+<font color="#AAAAAA">Placing MUX2X1</font>
+<font color="#AAAAAA">Placing NAND2X1</font>
+<font color="#AAAAAA">Placing NAND3X1</font>
+<font color="#AAAAAA">Placing NOR2X1</font>
+<font color="#AAAAAA">Placing OAI21X1</font>
+<font color="#AAAAAA">Placing OAI22X1</font>
+<font color="#AAAAAA">Placing OR2X1</font>
+<font color="#AAAAAA">Placing XNOR2X1</font>
+<font color="#AAAAAA">Traceback (most recent call last):</font>
+<font color="#AAAAAA"> File "/openLANE_flow/scripts/manual_macro_place.py", line 119, in <module></font>
+<font color="#AAAAAA"> assert not macros, ("Macros not found:", macros)</font>
+<font color="#AAAAAA">AssertionError: ('Macros not found:', {'BUFX4': ['38400', '56610', 'N'], 'CLKBUF1': ['38400', '63270', 'N'], 'NOR3X1': ['38400', '136530', 'N'], 'OR2X2': ['38400', '163170', 'N'], 'XOR2X1': ['38400', '176490', 'N']})</font>
+<font color="#AA0000">[ERROR]: during executing: "python3 /openLANE_flow/scripts/manual_macro_place.py -l /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef -id /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def -o /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def -c /project/openlane/user_proj_example/runs/user_proj_example/tmp/macro_placement.cfg -f |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/5-macro_placement.log"</font>
+<font color="#AA0000">[ERROR]: Exit code: 1</font>
+<font color="#AA0000">[ERROR]: Last 10 lines:</font>
+<font color="#AA0000">child process exited abnormally</font>
+
+<font color="#AA0000">[ERROR]: Please check python3 log file</font>
+<font color="#AA0000">[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow failed for user_proj_example/13-06_18-40 in 0h1m0s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log</font>
+<font color="#00AAAA">Source not found.</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">No antenna report found.</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#AA0000">[ERROR]: Flow Failed.</font>
+
+<font color="#AAAAAA"> while executing</font>
+<font color="#AAAAAA">"try_catch python3 $::env(SCRIPTS_DIR)/manual_macro_place.py -l $::env(MERGED_LEF) -id $::env(CURRENT_DEF) -o ${fbasename}.macro_placement.def -c $::en..."</font>
+<font color="#AAAAAA"> (procedure "manual_macro_placement" line 6)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"manual_macro_placement f"</font>
+<font color="#AAAAAA"> (procedure "run_floorplan" line 29)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_floorplan"</font>
+<font color="#AAAAAA"> (procedure "run_non_interactive_mode" line 15)</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"run_non_interactive_mode {*}$argv"</font>
+<font color="#AAAAAA"> invoked from within</font>
+<font color="#AAAAAA">"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {</font>
+ <font color="#AAAAAA">puts_info "Running interactively"</font>
+ <font color="#AAAAAA">if { [info exists arg_values(-file)..."</font>
+<font color="#AAAAAA"> (file "/openLANE_flow/flow.tcl" line 223)</font>
+<font color="#AAAAAA">make[1]: *** [Makefile:43: user_proj_example] Fehler 1</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen</font>
+<font color="#AAAAAA">make: *** [Makefile:71: user_proj_example] Fehler 2</font>
+<font color="#AAAAAA">Deployment done.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ bash deploy2caravel.sh </font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lib“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/lef/orig“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/gds“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">mkdir: das Verzeichnis »/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/cells/mag“ kann nicht angelegt werden: Die Datei existiert bereits</font>
+<font color="#AAAAAA">Cleaning up old files</font>
+<font color="#AAAAAA">Copying files that were created by StdCellLib</font>
+<font color="#AAAAAA">Removing cells with DRC issues left</font>
+<font color="#AAAAAA">Checking AND2X1</font>
+<font color="#AAAAAA">Checking AND2X2</font>
+<font color="#AAAAAA">Checking AOI21X1</font>
+<font color="#AAAAAA">Checking AOI22X1</font>
+<font color="#AAAAAA">Checking BUFX2</font>
+<font color="#AAAAAA">Checking BUFX4</font>
+<font color="#AAAAAA">Removing cell with 2 DRC issues:</font>
+<font color="#AAAAAA">Checking CLKBUF1</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking corr_XOR2X1</font>
+<font color="#AAAAAA">Error: Could not find DRC: /home/philipp/libresilicon/StdCellLib/corr_XOR2X1.drc No such file or directory</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking HAX1</font>
+<font color="#AAAAAA">Checking INV</font>
+<font color="#AAAAAA">Checking INVX1</font>
+<font color="#AAAAAA">Checking INVX2</font>
+<font color="#AAAAAA">Checking INVX4</font>
+<font color="#AAAAAA">Checking INVX8</font>
+<font color="#AAAAAA">Checking LATCH</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Checking MUX2X1</font>
+<font color="#AAAAAA">Checking NAND2X1</font>
+<font color="#AAAAAA">Checking NAND3X1</font>
+<font color="#AAAAAA">Checking NOR2X1</font>
+<font color="#AAAAAA">Checking NOR3X1</font>
+<font color="#AAAAAA">Removing cell with 60 DRC issues:</font>
+<font color="#AAAAAA">Checking OAI21X1</font>
+<font color="#AAAAAA">Checking OAI22X1</font>
+<font color="#AAAAAA">Checking OR2X1</font>
+<font color="#AAAAAA">Checking OR2X2</font>
+<font color="#AAAAAA">Removing cell with 7 DRC issues:</font>
+<font color="#AAAAAA">Checking XNOR2X1</font>
+<font color="#AAAAAA">Checking XOR2X1</font>
+<font color="#AAAAAA">Removing cell with 1 DRC issues:</font>
+<font color="#AAAAAA">Now cleaning up the files for Sky130</font>
+<font color="#AAAAAA">AND2X1.lef</font>
+<font color="#AAAAAA">AND2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X1.lef for cell AND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AND2X2.lef</font>
+<font color="#AAAAAA">AND2X2.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 70 lines.</font>
+<font color="#AAAAAA">Generating LEF output AND2X2.lef for cell AND2X2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AND2X2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI21X1.lef</font>
+<font color="#AAAAAA">AOI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI21X1.lef for cell AOI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">AOI22X1.lef</font>
+<font color="#AAAAAA">AOI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output AOI22X1.lef for cell AOI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell AOI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">BUFX2.lef</font>
+<font color="#AAAAAA">BUFX2.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output BUFX2.lef for cell BUFX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell BUFX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">HAX1.lef</font>
+<font color="#AAAAAA">HAX1.lef -> 15.84 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output HAX1.lef for cell HAX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell HAX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INV.lef</font>
+<font color="#AAAAAA">INV.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INV.lef for cell INV:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INV</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX1.lef</font>
+<font color="#AAAAAA">INVX1.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX1.lef for cell INVX1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX2.lef</font>
+<font color="#AAAAAA">INVX2.lef -> 2.88 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 57 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX2.lef for cell INVX2:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX2</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX4.lef</font>
+<font color="#AAAAAA">INVX4.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 69 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX4.lef for cell INVX4:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX4</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">INVX8.lef</font>
+<font color="#AAAAAA">INVX8.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 83 lines.</font>
+<font color="#AAAAAA">Generating LEF output INVX8.lef for cell INVX8:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell INVX8</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">MUX2X1.lef</font>
+<font color="#AAAAAA">MUX2X1.lef -> 8.64 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 89 lines.</font>
+<font color="#AAAAAA">Generating LEF output MUX2X1.lef for cell MUX2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell MUX2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND2X1.lef</font>
+<font color="#AAAAAA">NAND2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND2X1.lef for cell NAND2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NAND3X1.lef</font>
+<font color="#AAAAAA">NAND3X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output NAND3X1.lef for cell NAND3X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NAND3X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">NOR2X1.lef</font>
+<font color="#AAAAAA">NOR2X1.lef -> 4.32 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Generating LEF output NOR2X1.lef for cell NOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell NOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI21X1.lef</font>
+<font color="#AAAAAA">OAI21X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 87 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI21X1.lef for cell OAI21X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI21X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OAI22X1.lef</font>
+<font color="#AAAAAA">OAI22X1.lef -> 7.2 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 100 lines.</font>
+<font color="#AAAAAA">Generating LEF output OAI22X1.lef for cell OAI22X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OAI22X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">OR2X1.lef</font>
+<font color="#AAAAAA">OR2X1.lef -> 5.76 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Generating LEF output OR2X1.lef for cell OR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell OR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA">XNOR2X1.lef</font>
+<font color="#AAAAAA">XNOR2X1.lef -> 10.08 3.33</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Input style sky130: scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.81-0-gb184e85</font>
+<font color="#AAAAAA">Reading LEF data from file XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 80 lines.</font>
+<font color="#AAAAAA">Generating LEF output XNOR2X1.lef for cell XNOR2X1:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell XNOR2X1</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.010000</font>
+<font color="#AAAAAA"> INFO: Reading base liberty: /home/philipp/libresilicon/StdCellLib/Catalog/libresilicon.libtemplate</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AND2X2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: AOI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: BUFX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: HAX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INV.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX2.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX4.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: INVX8.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: MUX2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NAND3X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: NOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI21X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OAI22X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: OR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Reading liberty: XNOR2X1.lib</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AND2X2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(AOI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(BUFX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(HAX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INV)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX2)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX4)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(INVX8)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(MUX2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NAND3X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(NOR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI21X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OAI22X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(OR2X1)</font>
+<font color="#AAAAAA"> INFO: Add group: cell(XNOR2X1)</font>
+<font color="#AAAAAA"> INFO: Number of cells in base: 19, number of cells in output: 19</font>
+<font color="#AAAAAA"> INFO: Write liberty: libresilicon.lib</font>
+<font color="#AAAAAA">Now generating the demo wafer, the macro placement and the test-bench</font>
+<font color="#AAAAAA">Name "main::name" used only once: possible typo at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Use of uninitialized value $name in concatenation (.) or string at /media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts/placement.pl line 18.</font>
+<font color="#AAAAAA">Now building the Caravel user-project</font>
+<font color="#AAAAAA">cd openlane && make user_proj_example</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird betreten</font>
+<font color="#AAAAAA">###############################################</font>
+<font color="#00AAAA">[INFO]: </font>
+ <font color="#00AAAA">___ ____ ___ ____ _ ____ ____ ___</font>
+ <font color="#00AAAA">/ \ | \ / _]| \ | | / || \ / _]</font>
+ <font color="#00AAAA">| || o ) [_ | _ || | | o || _ | / [_</font>
+ <font color="#00AAAA">| O || _/ _]| | || |___ | || | || _]</font>
+ <font color="#00AAAA">| || | | [_ | | || || _ || | || [_</font>
+ <font color="#00AAAA">\___/ |__| |_____||__|__||_____||__|__||__|__||_____|</font>
+
+
+<font color="#00AAAA">[INFO]: Version: v0.15</font>
+<font color="#00AAAA">[INFO]: Running non-interactively</font>
+<font color="#00AAAA">[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#00AAAA">[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls</font>
+<font color="#00AAAA">[INFO]: PDK: sky130A</font>
+<font color="#00AAAA">[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A</font>
+<font color="#00AAAA">[INFO]: Standard Cell Library: sky130_fd_sc_ls</font>
+<font color="#00AAAA">[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl</font>
+<font color="#AA5500">[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">[INFO]: Preparing LEF Files</font>
+<font color="#00AAAA">[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef</font>
+<font color="#00AAAA">[INFO]: The number of available metal layers is 6</font>
+<font color="#00AAAA">[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5</font>
+<font color="#00AAAA">[INFO]: Merging LEF Files...</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">sky130_fd_sc_ls.lef: MACROs matched found: 399</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs</font>
+<font color="#AAAAAA">NAND3X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND3X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX8.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX8.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX4.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX4.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OAI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OAI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">HAX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">HAX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI21X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI21X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">MUX2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">MUX2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">BUFX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">BUFX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">OR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">OR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">NAND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">NAND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X2.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X2.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AOI22X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AOI22X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">XNOR2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">XNOR2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">AND2X1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">AND2X1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INVX1.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INVX1.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">INV.lef: SITEs matched found: 0</font>
+<font color="#AAAAAA">INV.lef: MACROs matched found: 1</font>
+<font color="#AAAAAA">mergeLef.py : Merging LEFs complete</font>
+<font color="#00AAAA">[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef</font>
+<font color="#00AAAA">[INFO]: Trimming Liberty...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Storing configs into config.tcl ...</font>
+<font color="#00AAAA">[INFO]: Preparation complete</font>
+<font color="#00AAAA">[INFO]: Running Synthesis...</font>
+<font color="#00AAAA">[INFO]: current step index: 1</font>
+
+<font color="#AAAAAA"> /----------------------------------------------------------------------------\</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | yosys -- Yosys Open SYnthesis Suite |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | Permission to use, copy, modify, and/or distribute this software for any |</font>
+<font color="#AAAAAA"> | purpose with or without fee is hereby granted, provided that the above |</font>
+<font color="#AAAAAA"> | copyright notice and this permission notice appear in all copies. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |</font>
+<font color="#AAAAAA"> | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |</font>
+<font color="#AAAAAA"> | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |</font>
+<font color="#AAAAAA"> | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |</font>
+<font color="#AAAAAA"> | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |</font>
+<font color="#AAAAAA"> | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |</font>
+<font color="#AAAAAA"> | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |</font>
+<font color="#AAAAAA"> | |</font>
+<font color="#AAAAAA"> \----------------------------------------------------------------------------/</font>
+
+<font color="#AAAAAA"> Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.</font>
+<font color="#AAAAAA">[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox</font>
+
+<font color="#AAAAAA">1. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 386 cell types from liberty file.</font>
+
+<font color="#AAAAAA">2. Executing Liberty frontend.</font>
+<font color="#AAAAAA">Imported 19 cell types from liberty file.</font>
+
+<font color="#AAAAAA">3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-19.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:21.1-30.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AND2X2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:32.1-42.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:44.1-55.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\AOI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-65.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\BUFX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:67.1-77.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\HAX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:79.1-87.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INV'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:89.1-97.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-107.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX2'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:109.1-117.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX4'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-127.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\INVX8'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:129.1-139.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\MUX2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:141.1-150.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:152.1-162.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NAND3X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:164.1-173.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\NOR2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:175.1-185.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI21X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:187.1-198.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OAI22X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:200.1-209.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\OR2X1'.</font>
+<font color="#AAAAAA">Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:211.1-220.10.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\XNOR2X1'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v</font>
+<font color="#AAAAAA">Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\user_proj_example'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">6. Generating Graphviz representation of design.</font>
+<font color="#AAAAAA">Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.</font>
+<font color="#AAAAAA">Dumping module user_proj_example to page 1.</font>
+
+<font color="#AAAAAA">7. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">7.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">7.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">8. Executing TRIBUF pass.</font>
+
+<font color="#AAAAAA">9. Executing SYNTH pass.</font>
+
+<font color="#AAAAAA">9.1. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.1.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.1.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.2. Executing PROC pass (convert processes to netlists).</font>
+
+<font color="#AAAAAA">9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).</font>
+<font color="#AAAAAA">Removed a total of 0 dead cases.</font>
+
+<font color="#AAAAAA">9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).</font>
+<font color="#AAAAAA">Removed 0 redundant assignments.</font>
+<font color="#AAAAAA">Promoted 0 assignments to connections.</font>
+
+<font color="#AAAAAA">9.2.4. Executing PROC_INIT pass (extract init attributes).</font>
+
+<font color="#AAAAAA">9.2.5. Executing PROC_ARST pass (detect async resets in processes).</font>
+
+<font color="#AAAAAA">9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).</font>
+
+<font color="#AAAAAA">9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).</font>
+
+<font color="#AAAAAA">9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).</font>
+
+<font color="#AAAAAA">9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).</font>
+<font color="#AAAAAA">Cleaned up 0 empty switches.</font>
+
+<font color="#AAAAAA">9.3. Executing FLATTEN pass (flatten design).</font>
+
+<font color="#AAAAAA">9.4. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.6. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [36] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [35] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [33] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [32] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [31] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [29] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [27] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [25] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [23] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [21] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [18] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [17] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [15] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [13] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [12] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [11] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [10] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [8] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [7] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [6] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [4] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [3] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [1] is used but has no driver.</font>
+<font color="#AAAAAA">Warning: Wire user_proj_example.\io_out [0] is used but has no driver.</font>
+<font color="#AAAAAA">found and reported 179 problems.</font>
+
+<font color="#AAAAAA">9.7. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.7.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.7.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.7.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.7.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.7.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.8. Executing FSM pass (extract and optimize FSM).</font>
+
+<font color="#AAAAAA">9.8.1. Executing FSM_DETECT pass (finding FSMs in design).</font>
+
+<font color="#AAAAAA">9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).</font>
+
+<font color="#AAAAAA">9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).</font>
+
+<font color="#AAAAAA">9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).</font>
+
+<font color="#AAAAAA">9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).</font>
+
+<font color="#AAAAAA">9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).</font>
+
+<font color="#AAAAAA">9.9. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.9.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.9.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.9.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.9.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.9.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.10. Executing WREDUCE pass (reducing word size of cells).</font>
+
+<font color="#AAAAAA">9.11. Executing PEEPOPT pass (run peephole optimizers).</font>
+
+<font color="#AAAAAA">9.12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.13. Executing ALUMACC pass (create $alu and $macc cells).</font>
+<font color="#AAAAAA">Extracting $alu and $macc cells in module user_proj_example:</font>
+<font color="#AAAAAA"> created 0 $alu and 0 $macc cells.</font>
+
+<font color="#AAAAAA">9.14. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">9.15. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.15.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.15.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.15.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.15.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.15.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.16. Executing MEMORY pass.</font>
+
+<font color="#AAAAAA">9.16.1. Executing OPT_MEM pass (optimize memories).</font>
+<font color="#AAAAAA">Performed a total of 0 transformations.</font>
+
+<font color="#AAAAAA">9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).</font>
+
+<font color="#AAAAAA">9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).</font>
+
+<font color="#AAAAAA">9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).</font>
+
+<font color="#AAAAAA">9.17. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.18.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+<font color="#AAAAAA"><suppressed ~87 debug messages></font>
+
+<font color="#AAAAAA">9.18.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.18.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.18.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).</font>
+
+<font color="#AAAAAA">9.20. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.20.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">9.20.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.20.6. Executing OPT_SHARE pass.</font>
+
+<font color="#AAAAAA">9.20.7. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.20.9. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.20.10. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">9.21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_bool_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_logic_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_compare_ops'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_various'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_simplemap_registers'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_shift_shiftx'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_fa'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lcu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alu'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_macc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_alumacc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_u'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_trunc'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_div'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_mod'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$__div_mod_floor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_divfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_modfloor'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pow'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_pmux'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\_90_lut'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">9.21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~67 debug messages></font>
+
+<font color="#AAAAAA">9.22. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.22.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.22.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.22.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.22.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.23. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">9.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">9.24. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">9.24.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">9.24.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">9.24.3. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">9.24.5. Finished fast OPT passes.</font>
+
+<font color="#AAAAAA">9.25. Executing HIERARCHY pass (managing design hierarchy).</font>
+
+<font color="#AAAAAA">9.25.1. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+
+<font color="#AAAAAA">9.25.2. Analyzing design hierarchy..</font>
+<font color="#AAAAAA">Top module: \user_proj_example</font>
+<font color="#AAAAAA">Removed 0 unused modules.</font>
+
+<font color="#AAAAAA">9.26. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">9.27. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">10. Executing SHARE pass (SAT-based resource sharing).</font>
+
+<font color="#AAAAAA">11. Executing OPT pass (performing simple optimizations).</font>
+
+<font color="#AAAAAA">11.1. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.2. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).</font>
+<font color="#AAAAAA">Running muxtree optimizer on module \user_proj_example..</font>
+<font color="#AAAAAA"> Creating internal representation of mux trees.</font>
+<font color="#AAAAAA"> No muxes found in this module.</font>
+<font color="#AAAAAA">Removed 0 multiplexer ports.</font>
+
+<font color="#AAAAAA">11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).</font>
+<font color="#AAAAAA"> Optimizing cells in module \user_proj_example.</font>
+<font color="#AAAAAA">Performed a total of 0 changes.</font>
+
+<font color="#AAAAAA">11.5. Executing OPT_MERGE pass (detect identical cells).</font>
+<font color="#AAAAAA">Finding identical cells in module `\user_proj_example'.</font>
+<font color="#AAAAAA">Removed a total of 0 cells.</font>
+
+<font color="#AAAAAA">11.6. Executing OPT_DFF pass (perform DFF optimizations).</font>
+
+<font color="#AAAAAA">11.7. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">11.8. Executing OPT_EXPR pass (perform const folding).</font>
+<font color="#AAAAAA">Optimizing module user_proj_example.</font>
+
+<font color="#AAAAAA">11.9. Finished OPT passes. (There is nothing left to do.)</font>
+
+<font color="#AAAAAA">12. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+
+<font color="#AAAAAA">13. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">mapping tbuf</font>
+
+<font color="#AAAAAA">14. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_TBUF_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">14.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">15. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">16. Executing MUXCOVER pass (mapping to wider MUXes).</font>
+<font color="#AAAAAA">Covering MUX trees in module user_proj_example..</font>
+<font color="#AAAAAA"> Treeifying 0 MUXes:</font>
+<font color="#AAAAAA"> Finished treeification: Found 0 trees.</font>
+<font color="#AAAAAA"> Covering trees:</font>
+<font color="#AAAAAA"> Added a total of 0 decoder MUXes.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">17. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">17.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX4_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">17.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">18. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">19. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">19.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_MUX_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">19.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~3 debug messages></font>
+
+<font color="#AAAAAA">20. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">21. Executing TECHMAP pass (map to technology primitives).</font>
+
+<font color="#AAAAAA">21.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v</font>
+<font color="#AAAAAA">Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v' to AST representation.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_P_'.</font>
+<font color="#AAAAAA">Generating RTLIL representation for module `\$_DLATCH_N_'.</font>
+<font color="#AAAAAA">Successfully finished Verilog frontend.</font>
+
+<font color="#AAAAAA">21.2. Continuing TECHMAP pass.</font>
+<font color="#AAAAAA">No more expansions possible.</font>
+<font color="#AAAAAA"><suppressed ~4 debug messages></font>
+
+<font color="#AAAAAA">22. Executing SIMPLEMAP pass (map simple cells to gate primitives).</font>
+
+<font color="#AAAAAA">23. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfxtp_2 (noninv, pins=3, area=28.77) is a direct match for cell type $_DFF_P_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfrtp_2 (noninv, pins=4, area=38.36) is a direct match for cell type $_DFF_PN0_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfstp_2 (noninv, pins=4, area=39.96) is a direct match for cell type $_DFF_PN1_.</font>
+<font color="#AAAAAA"> cell sky130_fd_sc_ls__dfbbn_2 (noninv, pins=6, area=47.95) is a direct match for cell type $_DFFSR_NNN_.</font>
+<font color="#AAAAAA"> final dff cell mappings:</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_N_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NN1_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_NP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP0_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFF_PP1_</font>
+<font color="#AAAAAA"> \sky130_fd_sc_ls__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_NPP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PNP_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPN_</font>
+<font color="#AAAAAA"> unmapped dff cell: $_DFFSR_PPP_</font>
+
+<font color="#AAAAAA">23.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).</font>
+<font color="#AAAAAA">Mapping DFF cells in module `\user_proj_example':</font>
+
+<font color="#AAAAAA">24. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 19</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+
+<font color="#AAAAAA">[INFO]: ABC: WireLoad : S_4</font>
+
+<font color="#AAAAAA">25. Executing ABC pass (technology mapping using ABC).</font>
+
+<font color="#AAAAAA">25.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-astuwy/input.blif'..</font>
+<font color="#AAAAAA">Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.</font>
+<font color="#AAAAAA">Don't call ABC as there is nothing to map.</font>
+<font color="#AAAAAA">Removing temp directory.</font>
+
+<font color="#AAAAAA">26. Executing SETUNDEF pass (replace undef values with defined constants).</font>
+
+<font color="#AAAAAA">27. Executing HILOMAP pass (mapping to constant drivers).</font>
+
+<font color="#AAAAAA">28. Executing SPLITNETS pass (splitting up multi-bit signals).</font>
+
+<font color="#AAAAAA">29. Executing OPT_CLEAN pass (remove unused cells and wires).</font>
+<font color="#AAAAAA">Finding unused cells or wires in module \user_proj_example..</font>
+<font color="#AAAAAA">Removed 0 unused cells and 217 unused wires.</font>
+<font color="#AAAAAA"><suppressed ~1 debug messages></font>
+
+<font color="#AAAAAA">30. Executing INSBUF pass (insert buffer cells for connected wires).</font>
+
+<font color="#AAAAAA">31. Executing CHECK pass (checking for obvious problems).</font>
+<font color="#AAAAAA">checking module user_proj_example..</font>
+<font color="#AAAAAA">found and reported 0 problems.</font>
+
+<font color="#AAAAAA">32. Printing statistics.</font>
+
+<font color="#AAAAAA">=== user_proj_example ===</font>
+
+<font color="#AAAAAA"> Number of wires: 16</font>
+<font color="#AAAAAA"> Number of wire bits: 604</font>
+<font color="#AAAAAA"> Number of public wires: 16</font>
+<font color="#AAAAAA"> Number of public wire bits: 604</font>
+<font color="#AAAAAA"> Number of memories: 0</font>
+<font color="#AAAAAA"> Number of memory bits: 0</font>
+<font color="#AAAAAA"> Number of processes: 0</font>
+<font color="#AAAAAA"> Number of cells: 236</font>
+<font color="#AAAAAA"> AND2X1 1</font>
+<font color="#AAAAAA"> AND2X2 1</font>
+<font color="#AAAAAA"> AOI21X1 1</font>
+<font color="#AAAAAA"> AOI22X1 1</font>
+<font color="#AAAAAA"> BUFX2 1</font>
+<font color="#AAAAAA"> HAX1 1</font>
+<font color="#AAAAAA"> INV 1</font>
+<font color="#AAAAAA"> INVX1 1</font>
+<font color="#AAAAAA"> INVX2 1</font>
+<font color="#AAAAAA"> INVX4 1</font>
+<font color="#AAAAAA"> INVX8 1</font>
+<font color="#AAAAAA"> MUX2X1 1</font>
+<font color="#AAAAAA"> NAND2X1 1</font>
+<font color="#AAAAAA"> NAND3X1 1</font>
+<font color="#AAAAAA"> NOR2X1 1</font>
+<font color="#AAAAAA"> OAI21X1 1</font>
+<font color="#AAAAAA"> OAI22X1 1</font>
+<font color="#AAAAAA"> OR2X1 1</font>
+<font color="#AAAAAA"> XNOR2X1 1</font>
+<font color="#AAAAAA"> sky130_fd_sc_ls__conb_1 217</font>
+
+<font color="#AAAAAA"> Area for cell type \AND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AND2X2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \AOI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \BUFX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \HAX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INV is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX2 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX4 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \INVX8 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \MUX2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NAND3X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \NOR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI21X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OAI22X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \OR2X1 is unknown!</font>
+<font color="#AAAAAA"> Area for cell type \XNOR2X1 is unknown!</font>
+
+<font color="#AAAAAA"> Chip area for module '\user_proj_example': 1040.558400</font>
+
+<font color="#AAAAAA">33. Executing Verilog backend.</font>
+<font color="#AAAAAA">Dumping module `\user_proj_example'.</font>
+
+<font color="#AAAAAA">Warnings: 179 unique messages, 179 total</font>
+<font color="#AAAAAA">End of script. Logfile hash: 6d67308f2b, CPU: user 22.03s system 0.80s, MEM: 386.66 MB peak</font>
+<font color="#AAAAAA">Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)</font>
+<font color="#AAAAAA">Time spent: 37% 4x read_liberty (8 sec), 37% 4x stat (8 sec), 21% 1x dfflibmap (4 sec), ...</font>
+<font color="#00AAAA">[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v</font>
+<font color="#00AAAA">[INFO]: Running Static Timing Analysis...</font>
+<font color="#00AAAA">[INFO]: current step index: 2</font>
+<font color="#AAAAAA">OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.</font>
+<font color="#AAAAAA">License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html></font>
+
+<font color="#AAAAAA">This is free software, and you are free to change and redistribute it</font>
+<font color="#AAAAAA">under certain conditions; type `show_copying' for details. </font>
+<font color="#AAAAAA">This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 671, module AND2X1 not found. Creating black box for AND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 676, module AND2X2 not found. Creating black box for AND2X2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 681, module AOI21X1 not found. Creating black box for AOI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 687, module AOI22X1 not found. Creating black box for AOI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 694, module BUFX2 not found. Creating black box for BUFX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 698, module HAX1 not found. Creating black box for HAX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 704, module INV not found. Creating black box for INV.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 708, module INVX1 not found. Creating black box for INVX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 712, module INVX2 not found. Creating black box for INVX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 716, module INVX4 not found. Creating black box for INVX4.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 720, module INVX8 not found. Creating black box for INVX8.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 724, module MUX2X1 not found. Creating black box for MUX2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 730, module NAND2X1 not found. Creating black box for NAND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 735, module NAND3X1 not found. Creating black box for NAND3X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 741, module NOR2X1 not found. Creating black box for NOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 746, module OAI21X1 not found. Creating black box for OAI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 752, module OAI22X1 not found. Creating black box for OAI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 759, module OR2X1 not found. Creating black box for OR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 764, module XNOR2X1 not found. Creating black box for XNOR2X1.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#00AAAA">[INFO]: Synthesis was successful</font>
+<font color="#00AAAA">[INFO]: Running Floorplanning...</font>
+<font color="#00AAAA">[INFO]: Running Initial Floorplanning...</font>
+<font color="#00AAAA">[INFO]: current step index: 3</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AND2X2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master AOI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master BUFX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master HAX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INV has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX2 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX4 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master INVX8 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master MUX2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NAND3X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master NOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI21X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OAI22X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master OR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[WARNING ORD-1000] LEF master XNOR2X1 has no liberty cell.</font>
+<font color="#AAAAAA">[INFO IFP-0001] Added 82 rows of 601 sites.</font>
+<font color="#00AAAA">[INFO]: Core area width: 288.48</font>
+<font color="#00AAAA">[INFO]: Core area height: 273.36</font>
+<font color="#00AAAA">[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#00AAAA">[INFO]: current step index: 4</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def</font>
+<font color="#AAAAAA">Top-level design name: user_proj_example</font>
+<font color="#AAAAAA">Block boundaries: 0 0 300000 300000</font>
+<font color="#AAAAAA">Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#00AAAA">[INFO]: Manual Macro Placement...</font>
+<font color="#00AAAA">[INFO]: current step index: 5</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def</font>
+<font color="#AAAAAA">Placing the following macros:</font>
+<font color="#AAAAAA">{}</font>
+<font color="#AAAAAA">Design name: user_proj_example</font>
+<font color="#AAAAAA">Successfully placed 0 instances</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def</font>
+<font color="#00AAAA">[INFO]: Running Tap/Decap Insertion...</font>
+<font color="#00AAAA">[INFO]: current step index: 6</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 236 components and 1400 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def</font>
+<font color="#AAAAAA">Step 1: Cut rows...</font>
+<font color="#AAAAAA">[INFO TAP-0001] Macro blocks found: 0</font>
+<font color="#AAAAAA">[INFO TAP-0002] #Original rows: 82</font>
+<font color="#AAAAAA">[INFO TAP-0003] #Cut rows: 0</font>
+<font color="#AAAAAA">Step 2: Insert endcaps...</font>
+<font color="#AAAAAA">[INFO TAP-0004] #Endcaps inserted: 164</font>
+<font color="#AAAAAA">Step 3: Insert tapcells...</font>
+<font color="#AAAAAA">[INFO TAP-0005] #Tapcells inserted: 882</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 7</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: Power planning the following nets</font>
+<font color="#00AAAA">[INFO]: Power: vccd1 vccd2 vdda1 vdda2</font>
+<font color="#00AAAA">[INFO]: Ground: vssd1 vssd2 vssa1 vssa2</font>
+<font color="#00AAAA">[INFO]: Generating PDN...</font>
+<font color="#00AAAA">[INFO]: current step index: 8</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 604 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl</font>
+<font color="#AAAAAA">[INFO] [PDNG-0008] Design Name is user_proj_example</font>
+<font color="#AAAAAA">[INFO] [PDNG-0009] Reading technology data</font>
+<font color="#AAAAAA">[INFO] [PDNG-0011] ****** INFO ******</font>
+<font color="#AAAAAA">Type: stdcell, grid</font>
+<font color="#AAAAAA"> Stdcell Rails</font>
+<font color="#AAAAAA"> Layer: met1 - width: 0.480 pitch: 3.330 offset: 0.000 </font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Layer: met4 - width: 1.600 pitch: 153.600 offset: 16.320 </font>
+<font color="#AAAAAA"> Connect: {met1 met4}</font>
+<font color="#AAAAAA">Type: macro, macro_1</font>
+<font color="#AAAAAA"> Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Connect: {met4_PIN_ver met5}</font>
+<font color="#AAAAAA">[INFO] [PDNG-0012] **** END INFO ****</font>
+<font color="#AAAAAA">[INFO] [PDNG-0013] Inserting stdcell grid - grid</font>
+<font color="#AAAAAA">[INFO] [PDNG-0015] Writing to database</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0022] Using voltage 0.000V for VDD network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vccd1.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (22.080um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 151.200um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vccd1 = 2876.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vccd1.</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vssd1 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0021] Using voltage 0.000V for ground network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vssd1.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 10.800um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 151.200um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vssd1 = 2810.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vssd1.</font>
+<font color="#00AAAA">[INFO]: PDN generation was successful.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def</font>
+<font color="#00AAAA">[INFO]: Generating PDN...</font>
+<font color="#00AAAA">[INFO]: current step index: 9</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 606 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 2 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl</font>
+<font color="#AAAAAA">[INFO] [PDNG-0008] Design Name is user_proj_example</font>
+<font color="#AAAAAA">[INFO] [PDNG-0009] Reading technology data</font>
+<font color="#AAAAAA">[INFO] [PDNG-0011] ****** INFO ******</font>
+<font color="#AAAAAA">Type: stdcell, grid</font>
+<font color="#AAAAAA"> Stdcell Rails</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Layer: met4 - width: 1.600 pitch: 153.600 offset: 19.620 </font>
+<font color="#AAAAAA"> Connect: </font>
+<font color="#AAAAAA">Type: macro, macro_1</font>
+<font color="#AAAAAA"> Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Connect: {met4_PIN_ver met5}</font>
+<font color="#AAAAAA">[INFO] [PDNG-0012] **** END INFO ****</font>
+<font color="#AAAAAA">[INFO] [PDNG-0013] Inserting stdcell grid - grid</font>
+<font color="#AAAAAA">[INFO] [PDNG-0015] Writing to database</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vccd2 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0022] Using voltage 0.000V for VDD network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vccd2.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (21.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (172.800um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vccd2 = 3.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vccd2.</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vssd2 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0021] Using voltage 0.000V for ground network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vssd2.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (97.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vssd2 = 3.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vssd2.</font>
+<font color="#00AAAA">[INFO]: PDN generation was successful.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def</font>
+<font color="#00AAAA">[INFO]: Generating PDN...</font>
+<font color="#00AAAA">[INFO]: current step index: 10</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 608 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 4 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl</font>
+<font color="#AAAAAA">[INFO] [PDNG-0008] Design Name is user_proj_example</font>
+<font color="#AAAAAA">[INFO] [PDNG-0009] Reading technology data</font>
+<font color="#AAAAAA">[INFO] [PDNG-0011] ****** INFO ******</font>
+<font color="#AAAAAA">Type: stdcell, grid</font>
+<font color="#AAAAAA"> Stdcell Rails</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Layer: met4 - width: 1.600 pitch: 153.600 offset: 22.920 </font>
+<font color="#AAAAAA"> Connect: </font>
+<font color="#AAAAAA">Type: macro, macro_1</font>
+<font color="#AAAAAA"> Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Connect: {met4_PIN_ver met5}</font>
+<font color="#AAAAAA">[INFO] [PDNG-0012] **** END INFO ****</font>
+<font color="#AAAAAA">[INFO] [PDNG-0013] Inserting stdcell grid - grid</font>
+<font color="#AAAAAA">[INFO] [PDNG-0015] Writing to database</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vdda1 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0022] Using voltage 0.000V for VDD network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vdda1.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vdda1 = 2.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vdda1.</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vssa1 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0021] Using voltage 0.000V for ground network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vssa1.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vssa1 = 3.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vssa1.</font>
+<font color="#00AAAA">[INFO]: PDN generation was successful.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def</font>
+<font color="#00AAAA">[INFO]: Generating PDN...</font>
+<font color="#00AAAA">[INFO]: current step index: 11</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 610 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 6 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN</font>
+<font color="#AAAAAA">[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl</font>
+<font color="#AAAAAA">[INFO] [PDNG-0008] Design Name is user_proj_example</font>
+<font color="#AAAAAA">[INFO] [PDNG-0009] Reading technology data</font>
+<font color="#AAAAAA">[INFO] [PDNG-0011] ****** INFO ******</font>
+<font color="#AAAAAA">Type: stdcell, grid</font>
+<font color="#AAAAAA"> Stdcell Rails</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Layer: met4 - width: 1.600 pitch: 153.600 offset: 26.220 </font>
+<font color="#AAAAAA"> Connect: </font>
+<font color="#AAAAAA">Type: macro, macro_1</font>
+<font color="#AAAAAA"> Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90</font>
+<font color="#AAAAAA"> Straps</font>
+<font color="#AAAAAA"> Connect: {met4_PIN_ver met5}</font>
+<font color="#AAAAAA">[INFO] [PDNG-0012] **** END INFO ****</font>
+<font color="#AAAAAA">[INFO] [PDNG-0013] Inserting stdcell grid - grid</font>
+<font color="#AAAAAA">[INFO] [PDNG-0015] Writing to database</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vdda2 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0022] Using voltage 0.000V for VDD network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vdda2.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vdda2 = 3.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vdda2.</font>
+<font color="#AAAAAA">[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.</font>
+<font color="#AAAAAA">[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.</font>
+<font color="#AAAAAA">[WARNING PSM-0019] Voltage on net vssa2 is not explicitly set.</font>
+<font color="#AAAAAA">[WARNING PSM-0021] Using voltage 0.000V for ground network.</font>
+<font color="#AAAAAA">[INFO PSM-0026] Creating G matrix.</font>
+<font color="#AAAAAA">[INFO PSM-0028] Extracting power stripes on net vssa2.</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (108.000um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).</font>
+<font color="#AAAAAA">[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).</font>
+<font color="#AAAAAA">[INFO PSM-0031] Number of nodes on net vssa2 = 3.</font>
+<font color="#AAAAAA">[INFO PSM-0037] G matrix created sucessfully.</font>
+<font color="#AAAAAA">[INFO PSM-0040] Connection between all PDN nodes established in net vssa2.</font>
+<font color="#00AAAA">[INFO]: PDN generation was successful.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def</font>
+<font color="#00AAAA">[INFO]: Running Placement...</font>
+<font color="#AA5500">[WARNING]: Performing Random Global Placement...</font>
+<font color="#00AAAA">[INFO]: current step index: 12</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def</font>
+<font color="#AAAAAA">Design name: user_proj_example</font>
+<font color="#AAAAAA">Core Area Boundaries: 5760 13320 294240 286380</font>
+<font color="#AAAAAA">Number of instances 1282</font>
+<font color="#AAAAAA">Placed 236 instances</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def</font>
+<font color="#00AAAA">[INFO]: Skipping OpenPhySyn Timing Optimizations.</font>
+<font color="#00AAAA">[INFO]: Running Resizer Design Optimizations...</font>
+<font color="#00AAAA">[INFO]: Generating Exclude List...</font>
+<font color="#00AAAA">[INFO]: Creating ::env(DONT_USE_CELLS)...</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/resizer.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1282 components and 3820 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 604 nets and 277 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">[INFO RSZ-0027] Inserted 367 input buffers.</font>
+<font color="#AAAAAA">[INFO RSZ-0028] Inserted 237 output buffers.</font>
+<font color="#AAAAAA">[INFO RSZ-0039] Resized 271 instances.</font>
+<font color="#AAAAAA">Design Stats</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total instances 1886</font>
+<font color="#AAAAAA">multi row instances 0</font>
+<font color="#AAAAAA">fixed instances 1046</font>
+<font color="#AAAAAA">nets 1216</font>
+<font color="#AAAAAA">design area 78772.3 u^2</font>
+<font color="#AAAAAA">fixed area 2458.3 u^2</font>
+<font color="#AAAAAA">movable area 5324.3 u^2</font>
+<font color="#AAAAAA">utilization 7 %</font>
+<font color="#AAAAAA">utilization padded 15 %</font>
+<font color="#AAAAAA">rows 82</font>
+<font color="#AAAAAA">row height 3.3 u</font>
+
+<font color="#AAAAAA">Placement Analysis</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total displacement 12784.9 u</font>
+<font color="#AAAAAA">average displacement 6.8 u</font>
+<font color="#AAAAAA">max displacement 77.1 u</font>
+<font color="#AAAAAA">original HPWL 72578.5 u</font>
+<font color="#AAAAAA">legalized HPWL 77226.1 u</font>
+<font color="#AAAAAA">delta HPWL 6 %</font>
+
+<font color="#AAAAAA">[INFO DPL-0020] Mirrored 285 instances</font>
+<font color="#AAAAAA">[INFO DPL-0021] HPWL before 77226.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0022] HPWL after 77031.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0023] HPWL delta -0.3 %</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def</font>
+<font color="#00AAAA">[INFO]: Writing Verilog...</font>
+<font color="#00AAAA">[INFO]: current step index: 13</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1886 components and 7444 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1485 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def</font>
+<font color="#00AAAA">[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v</font>
+<font color="#00AAAA">[INFO]: Running Static Timing Analysis...</font>
+<font color="#00AAAA">[INFO]: current step index: 14</font>
+<font color="#AAAAAA">OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.</font>
+<font color="#AAAAAA">License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html></font>
+
+<font color="#AAAAAA">This is free software, and you are free to change and redistribute it</font>
+<font color="#AAAAAA">under certain conditions; type `show_copying' for details. </font>
+<font color="#AAAAAA">This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 50, module AND2X1 not found. Creating black box for AND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 53, module AND2X2 not found. Creating black box for AND2X2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 56, module AOI21X1 not found. Creating black box for AOI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 60, module AOI22X1 not found. Creating black box for AOI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 65, module BUFX2 not found. Creating black box for BUFX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 67, module HAX1 not found. Creating black box for HAX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 71, module INV not found. Creating black box for INV.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 73, module INVX1 not found. Creating black box for INVX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 75, module INVX2 not found. Creating black box for INVX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 77, module INVX4 not found. Creating black box for INVX4.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 79, module INVX8 not found. Creating black box for INVX8.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 81, module MUX2X1 not found. Creating black box for MUX2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 85, module NAND2X1 not found. Creating black box for NAND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 88, module NAND3X1 not found. Creating black box for NAND3X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 92, module NOR2X1 not found. Creating black box for NOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 95, module OAI21X1 not found. Creating black box for OAI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 99, module OAI22X1 not found. Creating black box for OAI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 104, module OR2X1 not found. Creating black box for OR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 107, module XNOR2X1 not found. Creating black box for XNOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 491, module sky130_fd_sc_ls__tapvpwrvgnd_1 not found. Creating black box for PHY_164.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#00AAAA">[INFO]: Running Detailed Placement...</font>
+<font color="#00AAAA">[INFO]: current step index: 15</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1886 components and 7444 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1485 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def</font>
+<font color="#AAAAAA">Design Stats</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total instances 1886</font>
+<font color="#AAAAAA">multi row instances 0</font>
+<font color="#AAAAAA">fixed instances 1046</font>
+<font color="#AAAAAA">nets 1216</font>
+<font color="#AAAAAA">design area 78772.3 u^2</font>
+<font color="#AAAAAA">fixed area 2458.3 u^2</font>
+<font color="#AAAAAA">movable area 5324.3 u^2</font>
+<font color="#AAAAAA">utilization 7 %</font>
+<font color="#AAAAAA">utilization padded 14 %</font>
+<font color="#AAAAAA">rows 82</font>
+<font color="#AAAAAA">row height 3.3 u</font>
+
+<font color="#AAAAAA">Placement Analysis</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total displacement 0.0 u</font>
+<font color="#AAAAAA">average displacement 0.0 u</font>
+<font color="#AAAAAA">max displacement 0.0 u</font>
+<font color="#AAAAAA">original HPWL 77031.1 u</font>
+<font color="#AAAAAA">legalized HPWL 77226.1 u</font>
+<font color="#AAAAAA">delta HPWL 0 %</font>
+
+<font color="#AAAAAA">[INFO DPL-0020] Mirrored 285 instances</font>
+<font color="#AAAAAA">[INFO DPL-0021] HPWL before 77226.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0022] HPWL after 77031.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0023] HPWL delta -0.3 %</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 16</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: current step index: 17</font>
+<font color="#00AAAA">[INFO]: Running Resizer Timing Optimizations...</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/resizer.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1886 components and 7444 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1485 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">[WARNING STA-0357] virtual clock can not be propagated.</font>
+<font color="#AAAAAA">[INFO RSZ-0033] No hold violations found.</font>
+<font color="#AAAAAA">Design Stats</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total instances 1886</font>
+<font color="#AAAAAA">multi row instances 0</font>
+<font color="#AAAAAA">fixed instances 1046</font>
+<font color="#AAAAAA">nets 1216</font>
+<font color="#AAAAAA">design area 78772.3 u^2</font>
+<font color="#AAAAAA">fixed area 2458.3 u^2</font>
+<font color="#AAAAAA">movable area 5324.3 u^2</font>
+<font color="#AAAAAA">utilization 7 %</font>
+<font color="#AAAAAA">utilization padded 15 %</font>
+<font color="#AAAAAA">rows 82</font>
+<font color="#AAAAAA">row height 3.3 u</font>
+
+<font color="#AAAAAA">Placement Analysis</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total displacement 0.0 u</font>
+<font color="#AAAAAA">average displacement 0.0 u</font>
+<font color="#AAAAAA">max displacement 0.0 u</font>
+<font color="#AAAAAA">original HPWL 77031.1 u</font>
+<font color="#AAAAAA">legalized HPWL 77226.1 u</font>
+<font color="#AAAAAA">delta HPWL 0 %</font>
+
+<font color="#AAAAAA">[INFO DPL-0020] Mirrored 285 instances</font>
+<font color="#AAAAAA">[INFO DPL-0021] HPWL before 77226.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0022] HPWL after 77031.1 u</font>
+<font color="#AAAAAA">[INFO DPL-0023] HPWL delta -0.3 %</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def</font>
+<font color="#00AAAA">[INFO]: Writing Verilog...</font>
+<font color="#00AAAA">[INFO]: current step index: 18</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1886 components and 7444 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1485 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def</font>
+<font color="#00AAAA">[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v</font>
+<font color="#00AAAA">[INFO]: Running Static Timing Analysis...</font>
+<font color="#00AAAA">[INFO]: current step index: 19</font>
+<font color="#AAAAAA">OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.</font>
+<font color="#AAAAAA">License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html></font>
+
+<font color="#AAAAAA">This is free software, and you are free to change and redistribute it</font>
+<font color="#AAAAAA">under certain conditions; type `show_copying' for details. </font>
+<font color="#AAAAAA">This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 50, module AND2X1 not found. Creating black box for AND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 53, module AND2X2 not found. Creating black box for AND2X2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 56, module AOI21X1 not found. Creating black box for AOI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 60, module AOI22X1 not found. Creating black box for AOI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 65, module BUFX2 not found. Creating black box for BUFX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 67, module HAX1 not found. Creating black box for HAX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 71, module INV not found. Creating black box for INV.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 73, module INVX1 not found. Creating black box for INVX1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 75, module INVX2 not found. Creating black box for INVX2.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 77, module INVX4 not found. Creating black box for INVX4.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 79, module INVX8 not found. Creating black box for INVX8.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 81, module MUX2X1 not found. Creating black box for MUX2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 85, module NAND2X1 not found. Creating black box for NAND2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 88, module NAND3X1 not found. Creating black box for NAND3X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 92, module NOR2X1 not found. Creating black box for NOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 95, module OAI21X1 not found. Creating black box for OAI21X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 99, module OAI22X1 not found. Creating black box for OAI22X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 104, module OR2X1 not found. Creating black box for OR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 107, module XNOR2X1 not found. Creating black box for XNOR2X1.</font>
+<font color="#AAAAAA">Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 491, module sky130_fd_sc_ls__tapvpwrvgnd_1 not found. Creating black box for PHY_164.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#00AAAA">[INFO]: Routing...</font>
+<font color="#00AAAA">[INFO]: Running Global Routing...</font>
+<font color="#00AAAA">[INFO]: current step index: 20</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 1886 components and 7444 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1485 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def</font>
+<font color="#AAAAAA">Min routing layer: 2</font>
+<font color="#AAAAAA">Max routing layer: 6</font>
+<font color="#AAAAAA">Global adjustment: 0.0</font>
+<font color="#AAAAAA">Unidirectional routing: true</font>
+<font color="#AAAAAA">Grid origin: (0, 0)</font>
+<font color="#AAAAAA">[INFO GRT-0004] #DB Obstructions: 0</font>
+<font color="#AAAAAA">[INFO GRT-0005] #DB Obstacles: 21579</font>
+<font color="#AAAAAA">[INFO GRT-0006] #DB Macros: 0</font>
+<font color="#AAAAAA">[INFO GRT-0017] Found 0 clock nets</font>
+<font color="#AAAAAA">[INFO GRT-0001] Minimum degree: 2</font>
+<font color="#AAAAAA">[INFO GRT-0002] Maximum degree: 2</font>
+<font color="#AAAAAA">[INFO GRT-0018] Processing 15608 obstacles on layer 1</font>
+<font color="#AAAAAA">[INFO GRT-0019] Processing 4121 obstacles on layer 2</font>
+<font color="#AAAAAA">[INFO GRT-0022] Processing 16 obstacles on layer 5</font>
+<font color="#AAAAAA">[INFO GRT-0020] Reducing resources of layer 1 by 99%</font>
+<font color="#AAAAAA">[INFO] WIRELEN : 9502, WIRELEN1 : 0</font>
+<font color="#AAAAAA">[INFO] NumSeg : 835</font>
+<font color="#AAAAAA">[INFO] NumShift: 0</font>
+<font color="#AAAAAA">First L Route</font>
+<font color="#AAAAAA">[INFO] WIRELEN : 9502, WIRELEN1 : 9502</font>
+<font color="#AAAAAA">[INFO] NumSeg : 835</font>
+<font color="#AAAAAA">[INFO] NumShift: 0</font>
+<font color="#AAAAAA">[Overflow Report] Total hCap : 46135</font>
+<font color="#AAAAAA">[Overflow Report] Total vCap : 36068</font>
+<font color="#AAAAAA">[Overflow Report] Total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">Second L Route</font>
+<font color="#AAAAAA">[Overflow Report] Total hCap : 46135</font>
+<font color="#AAAAAA">[Overflow Report] Total vCap : 36068</font>
+<font color="#AAAAAA">[Overflow Report] Total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">First Z Route</font>
+<font color="#AAAAAA">[Overflow Report] Total hCap : 46135</font>
+<font color="#AAAAAA">[Overflow Report] Total vCap : 36068</font>
+<font color="#AAAAAA">[Overflow Report] Total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">[INFO] LV routing round 0, enlarge 10 </font>
+<font color="#AAAAAA">[INFO] 10 threshold, 10 expand</font>
+<font color="#AAAAAA">[Overflow Report] total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">[INFO] LV routing round 1, enlarge 15 </font>
+<font color="#AAAAAA">[INFO] 5 threshold, 15 expand</font>
+<font color="#AAAAAA">[Overflow Report] total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">[INFO] LV routing round 2, enlarge 20 </font>
+<font color="#AAAAAA">[INFO] 1 threshold, 20 expand</font>
+<font color="#AAAAAA">[Overflow Report] total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">Usage checked</font>
+<font color="#AAAAAA">Maze routing finished</font>
+<font color="#AAAAAA">[INFO] P3 runtime: 0.000000 sec</font>
+<font color="#AAAAAA">[INFO] Final 2D results: </font>
+<font color="#AAAAAA">[Overflow Report] total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Num Overflow e: 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">Layer Assignment Begins</font>
+<font color="#AAAAAA">Layer assignment finished</font>
+<font color="#AAAAAA">[INFO] 2D + Layer Assignment Runtime: 0.010000 sec</font>
+<font color="#AAAAAA">Post Processing Begins </font>
+<font color="#AAAAAA">Post Processsing finished</font>
+<font color="#AAAAAA"> Starting via filling</font>
+<font color="#AAAAAA">[INFO] Via related to pin nodes 2661</font>
+<font color="#AAAAAA">[INFO] Via related stiner nodes 0</font>
+<font color="#AAAAAA">Via filling finished</font>
+
+<font color="#AAAAAA">Final usage/overflow report: </font>
+<font color="#AAAAAA">[INFO] Usage per layer: </font>
+<font color="#AAAAAA"> Layer 1 usage: 0</font>
+<font color="#AAAAAA"> Layer 2 usage: 3936</font>
+<font color="#AAAAAA"> Layer 3 usage: 5484</font>
+<font color="#AAAAAA"> Layer 4 usage: 82</font>
+<font color="#AAAAAA"> Layer 5 usage: 0</font>
+<font color="#AAAAAA"> Layer 6 usage: 0</font>
+
+<font color="#AAAAAA">[INFO] Capacity per layer: </font>
+<font color="#AAAAAA"> Layer 1 capacity: 0</font>
+<font color="#AAAAAA"> Layer 2 capacity: 27855</font>
+<font color="#AAAAAA"> Layer 3 capacity: 24920</font>
+<font color="#AAAAAA"> Layer 4 capacity: 15000</font>
+<font color="#AAAAAA"> Layer 5 capacity: 11148</font>
+<font color="#AAAAAA"> Layer 6 capacity: 3280</font>
+
+<font color="#AAAAAA">[INFO] Use percentage per layer: </font>
+<font color="#AAAAAA"> Layer 1 use percentage: 0.0%</font>
+<font color="#AAAAAA"> Layer 2 use percentage: 14.13%</font>
+<font color="#AAAAAA"> Layer 3 use percentage: 22.01%</font>
+<font color="#AAAAAA"> Layer 4 use percentage: 0.55%</font>
+<font color="#AAAAAA"> Layer 5 use percentage: 0.00%</font>
+<font color="#AAAAAA"> Layer 6 use percentage: 0.00%</font>
+
+<font color="#AAAAAA">[INFO] Overflow per layer: </font>
+<font color="#AAAAAA"> Layer 1 overflow: 0</font>
+<font color="#AAAAAA"> Layer 2 overflow: 0</font>
+<font color="#AAAAAA"> Layer 3 overflow: 0</font>
+<font color="#AAAAAA"> Layer 4 overflow: 0</font>
+<font color="#AAAAAA"> Layer 5 overflow: 0</font>
+<font color="#AAAAAA"> Layer 6 overflow: 0</font>
+
+<font color="#AAAAAA">[Overflow Report] Total Usage : 9502</font>
+<font color="#AAAAAA">[Overflow Report] Total Capacity: 82203</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">[INFO] Final usage : 9502</font>
+<font color="#AAAAAA">[INFO] Final number of vias : 3182</font>
+<font color="#AAAAAA">[INFO] Final usage 3D : 19048</font>
+<font color="#AAAAAA">[INFO GRT-0018] Total wirelength: 91144 um</font>
+<font color="#AAAAAA">Repairing antennas...</font>
+<font color="#AAAAAA">[WARNING GRT-0025] No OR_DEFAULT vias defined</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">Notice 0: Split top of 1 T shapes.</font>
+<font color="#AAAAAA">[INFO GRT-0012] #Antenna violations: 118</font>
+<font color="#AAAAAA">Design Stats</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total instances 2116</font>
+<font color="#AAAAAA">multi row instances 0</font>
+<font color="#AAAAAA">fixed instances 1499</font>
+<font color="#AAAAAA">nets 1216</font>
+<font color="#AAAAAA">design area 78772.3 u^2</font>
+<font color="#AAAAAA">fixed area 4571.4 u^2</font>
+<font color="#AAAAAA">movable area 3946.4 u^2</font>
+<font color="#AAAAAA">utilization 5 %</font>
+<font color="#AAAAAA">utilization padded 5 %</font>
+<font color="#AAAAAA">rows 82</font>
+<font color="#AAAAAA">row height 3.3 u</font>
+
+<font color="#AAAAAA">Placement Analysis</font>
+<font color="#AAAAAA">--------------------------------</font>
+<font color="#AAAAAA">total displacement 0.0 u</font>
+<font color="#AAAAAA">average displacement 0.0 u</font>
+<font color="#AAAAAA">max displacement 0.0 u</font>
+<font color="#AAAAAA">original HPWL 77263.9 u</font>
+<font color="#AAAAAA">legalized HPWL 77388.7 u</font>
+<font color="#AAAAAA">delta HPWL 0 %</font>
+
+<font color="#AAAAAA">[WARNING DPL-0005] Overlap check failed (10).</font>
+<font color="#AAAAAA">[INFO GRT-0015] 230 diodes inserted</font>
+<font color="#AAAAAA">Min routing layer: 2</font>
+<font color="#AAAAAA">Max routing layer: 6</font>
+<font color="#AAAAAA">Global adjustment: 0.0</font>
+<font color="#AAAAAA">Unidirectional routing: true</font>
+<font color="#AAAAAA">Grid origin: (0, 0)</font>
+<font color="#AAAAAA">[INFO GRT-0004] #DB Obstructions: 0</font>
+<font color="#AAAAAA">[INFO GRT-0005] #DB Obstacles: 22959</font>
+<font color="#AAAAAA">[INFO GRT-0006] #DB Macros: 0</font>
+<font color="#AAAAAA">[INFO GRT-0001] Minimum degree: 2</font>
+<font color="#AAAAAA">[INFO GRT-0002] Maximum degree: 5</font>
+<font color="#AAAAAA">[INFO GRT-0018] Processing 16298 obstacles on layer 1</font>
+<font color="#AAAAAA">[INFO GRT-0019] Processing 4581 obstacles on layer 2</font>
+<font color="#AAAAAA">[INFO GRT-0022] Processing 16 obstacles on layer 5</font>
+<font color="#AAAAAA">[INFO GRT-0020] Reducing resources of layer 1 by 99%</font>
+<font color="#AAAAAA">[INFO GRT-0009] #Nets to reroute: 377</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 15, 16</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 16, 17</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 15, 16</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 15, 16</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 15, 16</font>
+<font color="#AAAAAA">[WARNING UKN-0000] Underflow in reduce</font>
+<font color="#AAAAAA">[WARNING UKN-0000] cap, reducedCap: 16, 17</font>
+
+<font color="#AAAAAA">Final usage/overflow report: </font>
+
+<font color="#AAAAAA">[Overflow Report] Total Usage : 8283</font>
+<font color="#AAAAAA">[Overflow Report] Total Capacity: 81180</font>
+<font color="#AAAAAA">[Overflow Report] Max H Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max V Overflow: 0</font>
+<font color="#AAAAAA">[Overflow Report] Max Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] H Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] V Overflow : 0</font>
+<font color="#AAAAAA">[Overflow Report] Final Overflow: 0</font>
+
+<font color="#AAAAAA">[INFO] Final usage : 8283</font>
+<font color="#AAAAAA">[INFO] Final number of vias : 1582</font>
+<font color="#AAAAAA">[INFO] Final usage 3D : 13029</font>
+<font color="#AAAAAA">[WARNING DPL-0005] Overlap check failed (10).</font>
+<font color="#AAAAAA">[INFO GRT-0014] Num routed nets: 899</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.</font>
+<font color="#AAAAAA">Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.</font>
+<font color="#AAAAAA">create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)</font>
+<font color="#AAAAAA">set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting output delay to: $output_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting output delay to: 2.0</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting input delay to: $input_delay_value"</font>
+<font color="#AAAAAA">[INFO]: Setting input delay to: 2.0</font>
+<font color="#AAAAAA">set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]</font>
+<font color="#AAAAAA">set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]</font>
+<font color="#AAAAAA">#set rst_indx [lsearch [all_inputs] [get_port resetn]]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]</font>
+<font color="#AAAAAA">#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]</font>
+<font color="#AAAAAA">set all_inputs_wo_clk_rst $all_inputs_wo_clk</font>
+<font color="#AAAAAA"># correct resetn</font>
+<font color="#AAAAAA">set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst</font>
+<font color="#AAAAAA">#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}</font>
+<font color="#AAAAAA">set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]</font>
+<font color="#AAAAAA"># TODO set this as parameter</font>
+<font color="#AAAAAA">set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]</font>
+<font color="#AAAAAA">set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]</font>
+<font color="#AAAAAA">puts "\[INFO\]: Setting load to: $cap_load"</font>
+<font color="#AAAAAA">[INFO]: Setting load to: 0.02205</font>
+<font color="#AAAAAA">set_load $cap_load [all_outputs]</font>
+<font color="#AAAAAA">No paths found.</font>
+<font color="#AAAAAA">No paths found.</font>
+<font color="#AAAAAA">No paths found.</font>
+<font color="#AAAAAA">wns 0.00</font>
+<font color="#AAAAAA">tns 0.00</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide</font>
+<font color="#00AAAA">[INFO]: Current Def is /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def</font>
+<font color="#00AAAA">[INFO]: Current Guide is /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide</font>
+<font color="#00AAAA">[INFO]: Running Fill Insertion...</font>
+<font color="#00AAAA">[INFO]: current step index: 21</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 2116 components and 8594 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1715 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def</font>
+<font color="#AAAAAA">[INFO DPL-0001] Placed 7217 filler instances.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def</font>
+<font color="#00AAAA">[INFO]: Writing Verilog...</font>
+<font color="#00AAAA">[INFO]: current step index: 22</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 9333 components and 37462 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1715 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def</font>
+<font color="#00AAAA">[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_preroute.v</font>
+<font color="#00AAAA">[INFO]: Running Detailed Routing...</font>
+<font color="#00AAAA">[INFO]: current step index: 23</font>
+
+<font color="#AAAAAA">reading lef ...</font>
+
+<font color="#AAAAAA">units: 1000</font>
+<font color="#AAAAAA">#layers: 13</font>
+<font color="#AAAAAA">#macros: 418</font>
+<font color="#AAAAAA">#vias: 25</font>
+<font color="#AAAAAA">#viarulegen: 25</font>
+
+<font color="#AAAAAA">reading def ...</font>
+
+<font color="#AAAAAA">design: user_proj_example</font>
+<font color="#AAAAAA">die area: ( 0 0 ) ( 300000 300000 )</font>
+<font color="#AAAAAA">trackPts: 12</font>
+<font color="#AAAAAA">defvias: 3</font>
+<font color="#AAAAAA">#components: 9333</font>
+<font color="#AAAAAA">#terminals: 620</font>
+<font color="#AAAAAA">#snets: 8</font>
+<font color="#AAAAAA">#nets: 1208</font>
+
+<font color="#AAAAAA">reading guide ...</font>
+
+<font color="#AAAAAA">#guides: 4636</font>
+<font color="#AAAAAA">Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...</font>
+<font color="#AAAAAA">Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...</font>
+<font color="#AAAAAA">done initConstraintLayerIdx</font>
+<font color="#AAAAAA">List of default vias:</font>
+<font color="#AAAAAA"> Layer mcon</font>
+<font color="#AAAAAA"> default via: L1M1_PR_MR</font>
+<font color="#AAAAAA"> Layer via</font>
+<font color="#AAAAAA"> default via: M1M2_PR</font>
+<font color="#AAAAAA"> Layer via2</font>
+<font color="#AAAAAA"> default via: via2_FR</font>
+<font color="#AAAAAA"> Layer via3</font>
+<font color="#AAAAAA"> default via: M3M4_PR_M</font>
+<font color="#AAAAAA"> Layer via4</font>
+<font color="#AAAAAA"> default via: via4_FR</font>
+<font color="#AAAAAA">Writing reference output def...</font>
+
+<font color="#AAAAAA">libcell analysis ...</font>
+
+<font color="#AAAAAA">instance analysis ...</font>
+<font color="#AAAAAA">#unique instances = 50</font>
+
+<font color="#AAAAAA">init region query ...</font>
+<font color="#AAAAAA"> complete FR_MASTERSLICE</font>
+<font color="#AAAAAA"> complete FR_VIA</font>
+<font color="#AAAAAA"> complete li1</font>
+<font color="#AAAAAA"> complete mcon</font>
+<font color="#AAAAAA"> complete met1</font>
+<font color="#AAAAAA"> complete via</font>
+<font color="#AAAAAA"> complete met2</font>
+<font color="#AAAAAA"> complete via2</font>
+<font color="#AAAAAA"> complete met3</font>
+<font color="#AAAAAA"> complete via3</font>
+<font color="#AAAAAA"> complete met4</font>
+<font color="#AAAAAA"> complete via4</font>
+<font color="#AAAAAA"> complete met5</font>
+
+<font color="#AAAAAA">FR_MASTERSLICE shape region query size = 0</font>
+<font color="#AAAAAA">FR_VIA shape region query size = 0</font>
+<font color="#AAAAAA">li1 shape region query size = 76934</font>
+<font color="#AAAAAA">mcon shape region query size = 98078</font>
+<font color="#AAAAAA">met1 shape region query size = 19181</font>
+<font color="#AAAAAA">via shape region query size = 664</font>
+<font color="#AAAAAA">met2 shape region query size = 936</font>
+<font color="#AAAAAA">via2 shape region query size = 664</font>
+<font color="#AAAAAA">met3 shape region query size = 332</font>
+<font color="#AAAAAA">via3 shape region query size = 664</font>
+<font color="#AAAAAA">met4 shape region query size = 198</font>
+<font color="#AAAAAA">via4 shape region query size = 0</font>
+<font color="#AAAAAA">met5 shape region query size = 0</font>
+
+
+<font color="#AAAAAA">start pin access</font>
+<font color="#AAAAAA"> complete 94 pins</font>
+<font color="#AAAAAA"> complete 44 unique inst patterns</font>
+<font color="#AAAAAA"> complete 837 groups</font>
+<font color="#AAAAAA">Expt1 runtime (pin-level access point gen): 0.997188</font>
+<font color="#AAAAAA">Expt2 runtime (design-level access pattern gen): 0.198724</font>
+<font color="#AAAAAA">#scanned instances = 9333</font>
+<font color="#AAAAAA">#unique instances = 50</font>
+<font color="#AAAAAA">#stdCellGenAp = 614</font>
+<font color="#AAAAAA">#stdCellValidPlanarAp = 223</font>
+<font color="#AAAAAA">#stdCellValidViaAp = 457</font>
+<font color="#AAAAAA">#stdCellPinNoAp = 0</font>
+<font color="#AAAAAA">#stdCellPinCnt = 1485</font>
+<font color="#AAAAAA">#instTermValidViaApCnt = 0</font>
+<font color="#AAAAAA">#macroGenAp = 0</font>
+<font color="#AAAAAA">#macroValidPlanarAp = 0</font>
+<font color="#AAAAAA">#macroValidViaAp = 0</font>
+<font color="#AAAAAA">#macroNoAp = 0</font>
+
+<font color="#AAAAAA">complete pin access</font>
+<font color="#AAAAAA">cpu time = 00:00:02, elapsed time = 00:00:01, memory = 27.97 (MB), peak = 30.04 (MB)</font>
+
+<font color="#AAAAAA">post process guides ...</font>
+<font color="#AAAAAA">GCELLGRID X 0 DO 41 STEP 7200 ;</font>
+<font color="#AAAAAA">GCELLGRID Y 0 DO 41 STEP 7200 ;</font>
+<font color="#AAAAAA"> complete FR_MASTERSLICE</font>
+<font color="#AAAAAA"> complete FR_VIA</font>
+<font color="#AAAAAA"> complete li1</font>
+<font color="#AAAAAA"> complete mcon</font>
+<font color="#AAAAAA"> complete met1</font>
+<font color="#AAAAAA"> complete via</font>
+<font color="#AAAAAA"> complete met2</font>
+<font color="#AAAAAA"> complete via2</font>
+<font color="#AAAAAA"> complete met3</font>
+<font color="#AAAAAA"> complete via3</font>
+<font color="#AAAAAA"> complete met4</font>
+<font color="#AAAAAA"> complete via4</font>
+<font color="#AAAAAA"> complete met5</font>
+
+<font color="#AAAAAA">building cmap ... </font>
+
+<font color="#AAAAAA">init guide query ...</font>
+<font color="#AAAAAA"> complete FR_MASTERSLICE (guide)</font>
+<font color="#AAAAAA"> complete FR_VIA (guide)</font>
+<font color="#AAAAAA"> complete li1 (guide)</font>
+<font color="#AAAAAA"> complete mcon (guide)</font>
+<font color="#AAAAAA"> complete met1 (guide)</font>
+<font color="#AAAAAA"> complete via (guide)</font>
+<font color="#AAAAAA"> complete met2 (guide)</font>
+<font color="#AAAAAA"> complete via2 (guide)</font>
+<font color="#AAAAAA"> complete met3 (guide)</font>
+<font color="#AAAAAA"> complete via3 (guide)</font>
+<font color="#AAAAAA"> complete met4 (guide)</font>
+<font color="#AAAAAA"> complete via4 (guide)</font>
+<font color="#AAAAAA"> complete met5 (guide)</font>
+
+<font color="#AAAAAA">FR_MASTERSLICE guide region query size = 0</font>
+<font color="#AAAAAA">FR_VIA guide region query size = 0</font>
+<font color="#AAAAAA">li1 guide region query size = 1146</font>
+<font color="#AAAAAA">mcon guide region query size = 0</font>
+<font color="#AAAAAA">met1 guide region query size = 1366</font>
+<font color="#AAAAAA">via guide region query size = 0</font>
+<font color="#AAAAAA">met2 guide region query size = 1339</font>
+<font color="#AAAAAA">via2 guide region query size = 0</font>
+<font color="#AAAAAA">met3 guide region query size = 0</font>
+<font color="#AAAAAA">via3 guide region query size = 0</font>
+<font color="#AAAAAA">met4 guide region query size = 0</font>
+<font color="#AAAAAA">via4 guide region query size = 0</font>
+<font color="#AAAAAA">met5 guide region query size = 0</font>
+
+<font color="#AAAAAA">init gr pin query ...</font>
+
+
+<font color="#AAAAAA">start track assignment</font>
+<font color="#AAAAAA">Done with 2485 vertical wires in 1 frboxes and 1366 horizontal wires in 1 frboxes.</font>
+<font color="#AAAAAA">Done with 578 vertical wires in 1 frboxes and 217 horizontal wires in 1 frboxes.</font>
+
+<font color="#AAAAAA">complete track assignment</font>
+<font color="#AAAAAA">cpu time = 00:00:01, elapsed time = 00:00:01, memory = 40.30 (MB), peak = 51.48 (MB)</font>
+
+<font color="#AAAAAA">post processing ...</font>
+
+<font color="#AAAAAA">start routing data preparation</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)</font>
+<font color="#AAAAAA">initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)</font>
+<font color="#AAAAAA">initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)</font>
+<font color="#AAAAAA">cpu time = 00:00:00, elapsed time = 00:00:00, memory = 41.36 (MB), peak = 51.48 (MB)</font>
+
+<font color="#AAAAAA">start detail routing ...</font>
+<font color="#AAAAAA">start 0th optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 84.03 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 88.41 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 18 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 82.33 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 18 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 84.70 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 18 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 84.79 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 34 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 89.45 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 34 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:06, memory = 94.39 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 44 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:07, memory = 89.90 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 44 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:07, memory = 90.10 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 51 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:08, memory = 50.19 (MB)</font>
+<font color="#AAAAAA"> number of violations = 51</font>
+<font color="#AAAAAA">cpu time = 00:00:15, elapsed time = 00:00:09, memory = 45.69 (MB), peak = 396.17 (MB)</font>
+<font color="#AAAAAA">total wire length = 76522 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 12 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29388 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47113 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 8 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3054</font>
+<font color="#AAAAAA">up-via summary (total 3054):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1356</font>
+<font color="#AAAAAA"> met1 1694</font>
+<font color="#AAAAAA"> met2 4</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3054</font>
+
+
+<font color="#AAAAAA">start 1st optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 51 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 79.20 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 51 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 84.04 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 51 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 86.52 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 44 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 92.69 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 44 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 94.24 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 33 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 83.54 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 33 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 86.33 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 33 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:06, memory = 87.71 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 31 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:07, memory = 91.53 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:08, memory = 48.92 (MB)</font>
+<font color="#AAAAAA"> number of violations = 13</font>
+<font color="#AAAAAA">cpu time = 00:00:15, elapsed time = 00:00:09, memory = 45.70 (MB), peak = 396.19 (MB)</font>
+<font color="#AAAAAA">total wire length = 76497 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 21 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29371 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47091 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 12 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3067</font>
+<font color="#AAAAAA">up-via summary (total 3067):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1362</font>
+<font color="#AAAAAA"> met1 1699</font>
+<font color="#AAAAAA"> met2 6</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3067</font>
+
+
+<font color="#AAAAAA">start 2nd optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 51.88 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 69.16 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 73.46 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 79.39 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 88.82 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 15 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 71.30 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 15 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 84.84 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 15 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 88.61 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 14 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 80.60 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 70.74 (MB)</font>
+<font color="#AAAAAA"> number of violations = 13</font>
+<font color="#AAAAAA">cpu time = 00:00:10, elapsed time = 00:00:06, memory = 64.61 (MB), peak = 414.14 (MB)</font>
+<font color="#AAAAAA">total wire length = 76498 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 30 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29378 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47081 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 8 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3054</font>
+<font color="#AAAAAA">up-via summary (total 3054):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1374</font>
+<font color="#AAAAAA"> met1 1676</font>
+<font color="#AAAAAA"> met2 4</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3054</font>
+
+
+<font color="#AAAAAA">start 3rd optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 77.75 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 13 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 86.07 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 8 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 76.51 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 8 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 84.50 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 8 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 84.50 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 4 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 86.14 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 4 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 86.37 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 79.62 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 79.62 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 79.84 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:06, elapsed time = 00:00:06, memory = 80.32 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 17th optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 80.32 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 80.32 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 80.32 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 80.57 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 80.83 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:04, elapsed time = 00:00:05, memory = 80.91 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 25th optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 80.91 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 80.96 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 80.96 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 80.96 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 80.96 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:04, elapsed time = 00:00:05, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 33rd optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:05, elapsed time = 00:00:05, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 41st optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:06, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:05, elapsed time = 00:00:06, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 49th optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:05, elapsed time = 00:00:05, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">start 57th optimization iteration ...</font>
+<font color="#AAAAAA"> completing 10% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 20% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:00, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 30% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:01, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 40% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 50% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:02, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 60% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 70% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:03, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 80% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:04, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 90% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> completing 100% with 0 violations</font>
+<font color="#AAAAAA"> elapsed time = 00:00:05, memory = 81.07 (MB)</font>
+<font color="#AAAAAA"> number of violations = 0</font>
+<font color="#AAAAAA">cpu time = 00:00:05, elapsed time = 00:00:05, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+
+<font color="#AAAAAA">complete detail routing</font>
+<font color="#AAAAAA">total wire length = 76500 um</font>
+<font color="#AAAAAA">total wire length on LAYER li1 = 29 um</font>
+<font color="#AAAAAA">total wire length on LAYER met1 = 29376 um</font>
+<font color="#AAAAAA">total wire length on LAYER met2 = 47080 um</font>
+<font color="#AAAAAA">total wire length on LAYER met3 = 13 um</font>
+<font color="#AAAAAA">total wire length on LAYER met4 = 0 um</font>
+<font color="#AAAAAA">total wire length on LAYER met5 = 0 um</font>
+<font color="#AAAAAA">total number of vias = 3058</font>
+<font color="#AAAAAA">up-via summary (total 3058):</font>
+
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> FR_MASTERSLICE 0</font>
+<font color="#AAAAAA"> li1 1372</font>
+<font color="#AAAAAA"> met1 1678</font>
+<font color="#AAAAAA"> met2 8</font>
+<font color="#AAAAAA"> met3 0</font>
+<font color="#AAAAAA"> met4 0</font>
+<font color="#AAAAAA">-----------------------</font>
+<font color="#AAAAAA"> 3058</font>
+
+<font color="#AAAAAA">cpu time = 00:01:20, elapsed time = 00:01:06, memory = 81.07 (MB), peak = 422.46 (MB)</font>
+
+<font color="#AAAAAA">post processing ...</font>
+
+<font color="#AAAAAA">Runtime taken (hrt): 72.2057</font>
+<font color="#00AAAA">[INFO]: No DRC violations after detailed routing.</font>
+<font color="#00AAAA">[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def to /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 24</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Routing completed for user_proj_example/13-06_18-43 in 0h6m36s</font>
+<font color="#00AAAA">[INFO]: Writing Powered Verilog...</font>
+<font color="#00AAAA">[INFO]: current step index: 25</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 620 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 9333 components and 37462 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1715 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">Top-level design name: user_proj_example</font>
+<font color="#AAAAAA">Default power net: vccd1</font>
+<font color="#AAAAAA">Default ground net: vssd1</font>
+<font color="#AAAAAA">Found a total of 4 power ports.</font>
+<font color="#AAAAAA">Found a total of 4 ground ports.</font>
+<font color="#AAAAAA">Modified power connections of 9333 cells (Remaining: 0 ).</font>
+<font color="#00AAAA">[INFO]: Writing Verilog...</font>
+<font color="#00AAAA">[INFO]: current step index: 26</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/25-user_proj_example.powered.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 612 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 9333 components and 37462 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1210 nets and 37245 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/25-user_proj_example.powered.def</font>
+<font color="#00AAAA">[INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is.</font>
+<font color="#00AAAA">[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_preroute.v to /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v</font>
+<font color="#00AAAA">[INFO]: Running Magic to generate various views...</font>
+<font color="#00AAAA">[INFO]: Streaming out GDS II...</font>
+<font color="#00AAAA">[INFO]: current step index: 27</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/openLANE_flow/scripts/magic/mag_gds.tcl" from command line.</font>
+<font color="#AAAAAA">Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read: Processed 769 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 65 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 62 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA"> Processed 5 vias total.</font>
+<font color="#AAAAAA"> Processed 9333 subcell instances total.</font>
+<font color="#AAAAAA"> Processed 620 pins total.</font>
+<font color="#AAAAAA"> Processed 8 special nets total.</font>
+<font color="#AAAAAA"> Processed 1208 nets total.</font>
+<font color="#AAAAAA">DEF read: Processed 21075 lines.</font>
+<font color="#AAAAAA">Root cell box:</font>
+<font color="#AAAAAA"> width x height ( llx, lly ), ( urx, ury ) area (units^2)</font>
+
+<font color="#AAAAAA">microns: 300.00 x 300.00 ( 0.00, 0.00 ), ( 300.00, 300.00) 90000.00 </font>
+<font color="#AAAAAA">lambda: 30000.00 x 30000.00 ( 0.00, 0.00 ), ( 30000.00, 30000.00) 900000000.00</font>
+<font color="#AAAAAA">internal: 60000 x 60000 ( 0, 0 ), ( 60000, 60000) 3600000000</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "HAX1".</font>
+<font color="#AAAAAA">Warning: cell HAX1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "INVX8".</font>
+<font color="#AAAAAA">Warning: cell INVX8 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "AND2X2".</font>
+<font color="#AAAAAA">Warning: cell AND2X2 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "XNOR2X1".</font>
+<font color="#AAAAAA">Warning: cell XNOR2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "OAI22X1".</font>
+<font color="#AAAAAA">Warning: cell OAI22X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "AOI21X1".</font>
+<font color="#AAAAAA">Warning: cell AOI21X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "NAND2X1".</font>
+<font color="#AAAAAA">Warning: cell NAND2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "OAI21X1".</font>
+<font color="#AAAAAA">Warning: cell OAI21X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "INV".</font>
+<font color="#AAAAAA">Warning: cell INV already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "AOI22X1".</font>
+<font color="#AAAAAA">Warning: cell AOI22X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "OR2X1".</font>
+<font color="#AAAAAA">Warning: cell OR2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "INVX1".</font>
+<font color="#AAAAAA">Warning: cell INVX1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "NOR2X1".</font>
+<font color="#AAAAAA">Warning: cell NOR2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "MUX2X1".</font>
+<font color="#AAAAAA">Warning: cell MUX2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "BUFX2".</font>
+<font color="#AAAAAA">Warning: cell BUFX2 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "AND2X1".</font>
+<font color="#AAAAAA">Warning: cell AND2X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "NAND3X1".</font>
+<font color="#AAAAAA">Warning: cell NAND3X1 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "INVX2".</font>
+<font color="#AAAAAA">Warning: cell INVX2 already existed before reading GDS!</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 6.0</font>
+<font color="#AAAAAA">Library name: LIB</font>
+<font color="#AAAAAA">Reading "INVX4".</font>
+<font color="#AAAAAA">Warning: cell INVX4 already existed before reading GDS!</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__decap_4</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__clkbuf_1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__decap_8</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__tapvpwrvgnd_1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__fill_diode_2</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__fill_1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__buf_2</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__clkbuf_2</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__buf_1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__conb_1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__diode_2</font>
+<font color="#AAAAAA"> Generating output for cell OAI21X1</font>
+<font color="#AAAAAA"> Generating output for cell INVX8</font>
+<font color="#AAAAAA"> Generating output for cell INVX2</font>
+<font color="#AAAAAA"> Generating output for cell INVX4</font>
+<font color="#AAAAAA"> Generating output for cell INV</font>
+<font color="#AAAAAA"> Generating output for cell AOI22X1</font>
+<font color="#AAAAAA"> Generating output for cell INVX1</font>
+<font color="#AAAAAA"> Generating output for cell OAI22X1</font>
+<font color="#AAAAAA"> Generating output for cell MUX2X1</font>
+<font color="#AAAAAA"> Generating output for cell AOI21X1</font>
+<font color="#AAAAAA"> Generating output for cell OR2X1</font>
+<font color="#AAAAAA"> Generating output for cell NAND3X1</font>
+<font color="#AAAAAA"> Generating output for cell AND2X2</font>
+<font color="#AAAAAA"> Generating output for cell AND2X1</font>
+<font color="#AAAAAA"> Generating output for cell BUFX2</font>
+<font color="#AAAAAA"> Generating output for cell NAND2X1</font>
+<font color="#AAAAAA"> Generating output for cell NOR2X1</font>
+<font color="#AAAAAA"> Generating output for cell XNOR2X1</font>
+<font color="#AAAAAA"> Generating output for cell HAX1</font>
+<font color="#AAAAAA"> Generating output for cell sky130_fd_sc_ls__clkbuf_4</font>
+<font color="#AAAAAA"> Generating output for cell user_proj_example</font>
+<font color="#AAAAAA">[INFO]: GDS Write Complete</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 28</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: current step index: 29</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/openLANE_flow/scripts/magic/gds_pointers.tcl" from command line.</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 3.0</font>
+<font color="#AAAAAA">Library name: user_proj_example</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__decap_4".</font>
+<font color="#AAAAAA">CIF file read warning: CIF style sky130(): units rescaled by factor of 5 / 1</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__decap_8".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__tapvpwrvgnd_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__fill_diode_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__fill_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__buf_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__buf_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__conb_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__diode_2".</font>
+<font color="#AAAAAA">Reading "OAI21X1".</font>
+<font color="#AAAAAA">Reading "INVX8".</font>
+<font color="#AAAAAA">Reading "INVX2".</font>
+<font color="#AAAAAA">Reading "INVX4".</font>
+<font color="#AAAAAA">Reading "INV".</font>
+<font color="#AAAAAA">Reading "AOI22X1".</font>
+<font color="#AAAAAA">Reading "INVX1".</font>
+<font color="#AAAAAA">Reading "OAI22X1".</font>
+<font color="#AAAAAA">Reading "MUX2X1".</font>
+<font color="#AAAAAA">Reading "AOI21X1".</font>
+<font color="#AAAAAA">Reading "OR2X1".</font>
+<font color="#AAAAAA">Reading "NAND3X1".</font>
+<font color="#AAAAAA">Reading "AND2X2".</font>
+<font color="#AAAAAA">Reading "AND2X1".</font>
+<font color="#AAAAAA">Reading "BUFX2".</font>
+<font color="#AAAAAA">Reading "NAND2X1".</font>
+<font color="#AAAAAA">Reading "NOR2X1".</font>
+<font color="#AAAAAA">Reading "XNOR2X1".</font>
+<font color="#AAAAAA">Reading "HAX1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_4".</font>
+<font color="#AAAAAA">Reading "user_proj_example".</font>
+<font color="#AAAAAA"> 100 uses</font>
+<font color="#AAAAAA"> 200 uses</font>
+<font color="#AAAAAA"> 300 uses</font>
+<font color="#AAAAAA"> 400 uses</font>
+<font color="#AAAAAA"> 500 uses</font>
+<font color="#AAAAAA"> 600 uses</font>
+<font color="#AAAAAA"> 700 uses</font>
+<font color="#AAAAAA"> 800 uses</font>
+<font color="#AAAAAA"> 900 uses</font>
+<font color="#AAAAAA"> 1000 uses</font>
+<font color="#AAAAAA"> 1100 uses</font>
+<font color="#AAAAAA"> 1200 uses</font>
+<font color="#AAAAAA"> 1300 uses</font>
+<font color="#AAAAAA"> 1400 uses</font>
+<font color="#AAAAAA"> 1500 uses</font>
+<font color="#AAAAAA"> 1600 uses</font>
+<font color="#AAAAAA"> 1700 uses</font>
+<font color="#AAAAAA"> 1800 uses</font>
+<font color="#AAAAAA"> 1900 uses</font>
+<font color="#AAAAAA"> 2000 uses</font>
+<font color="#AAAAAA"> 2100 uses</font>
+<font color="#AAAAAA"> 2200 uses</font>
+<font color="#AAAAAA"> 2300 uses</font>
+<font color="#AAAAAA"> 2400 uses</font>
+<font color="#AAAAAA"> 2500 uses</font>
+<font color="#AAAAAA"> 2600 uses</font>
+<font color="#AAAAAA"> 2700 uses</font>
+<font color="#AAAAAA"> 2800 uses</font>
+<font color="#AAAAAA"> 2900 uses</font>
+<font color="#AAAAAA"> 3000 uses</font>
+<font color="#AAAAAA"> 3100 uses</font>
+<font color="#AAAAAA"> 3200 uses</font>
+<font color="#AAAAAA"> 3300 uses</font>
+<font color="#AAAAAA"> 3400 uses</font>
+<font color="#AAAAAA"> 3500 uses</font>
+<font color="#AAAAAA"> 3600 uses</font>
+<font color="#AAAAAA"> 3700 uses</font>
+<font color="#AAAAAA"> 3800 uses</font>
+<font color="#AAAAAA"> 3900 uses</font>
+<font color="#AAAAAA"> 4000 uses</font>
+<font color="#AAAAAA"> 4100 uses</font>
+<font color="#AAAAAA"> 4200 uses</font>
+<font color="#AAAAAA"> 4300 uses</font>
+<font color="#AAAAAA"> 4400 uses</font>
+<font color="#AAAAAA"> 4500 uses</font>
+<font color="#AAAAAA"> 4600 uses</font>
+<font color="#AAAAAA"> 4700 uses</font>
+<font color="#AAAAAA"> 4800 uses</font>
+<font color="#AAAAAA"> 4900 uses</font>
+<font color="#AAAAAA"> 5000 uses</font>
+<font color="#AAAAAA"> 5100 uses</font>
+<font color="#AAAAAA"> 5200 uses</font>
+<font color="#AAAAAA"> 5300 uses</font>
+<font color="#AAAAAA"> 5400 uses</font>
+<font color="#AAAAAA"> 5500 uses</font>
+<font color="#AAAAAA"> 5600 uses</font>
+<font color="#AAAAAA"> 5700 uses</font>
+<font color="#AAAAAA"> 5800 uses</font>
+<font color="#AAAAAA"> 5900 uses</font>
+<font color="#AAAAAA"> 6000 uses</font>
+<font color="#AAAAAA"> 6100 uses</font>
+<font color="#AAAAAA"> 6200 uses</font>
+<font color="#AAAAAA"> 6300 uses</font>
+<font color="#AAAAAA"> 6400 uses</font>
+<font color="#AAAAAA"> 6500 uses</font>
+<font color="#AAAAAA"> 6600 uses</font>
+<font color="#AAAAAA"> 6700 uses</font>
+<font color="#AAAAAA"> 6800 uses</font>
+<font color="#AAAAAA"> 6900 uses</font>
+<font color="#AAAAAA"> 7000 uses</font>
+<font color="#AAAAAA"> 7100 uses</font>
+<font color="#AAAAAA"> 7200 uses</font>
+<font color="#AAAAAA"> 7300 uses</font>
+<font color="#AAAAAA"> 7400 uses</font>
+<font color="#AAAAAA"> 7500 uses</font>
+<font color="#AAAAAA"> 7600 uses</font>
+<font color="#AAAAAA"> 7700 uses</font>
+<font color="#AAAAAA"> 7800 uses</font>
+<font color="#AAAAAA"> 7900 uses</font>
+<font color="#AAAAAA"> 8000 uses</font>
+<font color="#AAAAAA"> 8100 uses</font>
+<font color="#AAAAAA"> 8200 uses</font>
+<font color="#AAAAAA"> 8300 uses</font>
+<font color="#AAAAAA"> 8400 uses</font>
+<font color="#AAAAAA"> 8500 uses</font>
+<font color="#AAAAAA"> 8600 uses</font>
+<font color="#AAAAAA"> 8700 uses</font>
+<font color="#AAAAAA"> 8800 uses</font>
+<font color="#AAAAAA"> 8900 uses</font>
+<font color="#AAAAAA"> 9000 uses</font>
+<font color="#AAAAAA"> 9100 uses</font>
+<font color="#AAAAAA"> 9200 uses</font>
+<font color="#AAAAAA"> 9300 uses</font>
+<font color="#AAAAAA">[INFO]: Wrote /project/openlane/user_proj_example/runs/user_proj_example/tmp/magic/magic_gds_ptrs.mag including GDS pointers.</font>
+<font color="#00AAAA">[INFO]: current step index: 30</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/openLANE_flow/scripts/magic/lef.tcl" from command line.</font>
+<font color="#AAAAAA">Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read: Processed 769 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 65 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 62 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">user_proj_example: 10000 rects</font>
+<font color="#AAAAAA">user_proj_example: 20000 rects</font>
+<font color="#AAAAAA">user_proj_example: 30000 rects</font>
+<font color="#AAAAAA">Processing timestamp mismatches: HAX1, XNOR2X1, NOR2X1, NAND2X1, BUFX2, AND2X1, AND2X2, NAND3X1, OR2X1, AOI21X1, MUX2X1, OAI22X1, INVX1, AOI22X1, INV, INVX4, INVX2, INVX8, OAI21X1.</font>
+<font color="#AAAAAA">[INFO]: Writing abstract LEF</font>
+<font color="#AAAAAA">Generating LEF output /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef for cell user_proj_example:</font>
+<font color="#AAAAAA">Diagnostic: Write LEF header for cell user_proj_example</font>
+<font color="#AAAAAA">Diagnostic: Writing LEF output for cell user_proj_example</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__decap_4" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__decap_4.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__decap_4.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__decap_8" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__decap_8.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__decap_8.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__fill_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__fill_1.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__fill_1.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__fill_diode_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__fill_diode_2.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__fill_diode_2.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_2.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_2.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__buf_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__buf_1.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__buf_1.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__tapvpwrvgnd_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__tapvpwrvgnd_1.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__tapvpwrvgnd_1.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_1.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_1.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_4" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_4.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_4.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__buf_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__buf_2.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__buf_2.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__diode_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__diode_2.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__diode_2.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Warning: Parent cell lists instance of "sky130_fd_sc_ls__conb_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__conb_1.mag.</font>
+<font color="#AAAAAA">The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__conb_1.mag.</font>
+<font color="#AAAAAA">The discovered version will be used.</font>
+<font color="#AAAAAA">Diagnostic: Scale value is 0.005000</font>
+<font color="#AAAAAA">Processing timestamp mismatches: sky130_fd_sc_ls__conb_1, sky130_fd_sc_ls__diode_2, sky130_fd_sc_ls__buf_2, sky130_fd_sc_ls__clkbuf_4, sky130_fd_sc_ls__clkbuf_1, sky130_fd_sc_ls__tapvpwrvgnd_1, sky130_fd_sc_ls__buf_1, sky130_fd_sc_ls__clkbuf_2, sky130_fd_sc_ls__fill_diode_2, sky130_fd_sc_ls__fill_1, sky130_fd_sc_ls__decap_8, sky130_fd_sc_ls__decap_4.</font>
+<font color="#AAAAAA">[INFO]: LEF Write Complete</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.156-0-g7e29496</font>
+<font color="#00AAAA">[INFO]: current step index: 31</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/openLANE_flow/scripts/magic/maglef.tcl" from command line.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 5230 lines.</font>
+<font color="#AAAAAA">[INFO]: DONE GENERATING MAGLEF VIEW</font>
+<font color="#00AAAA">[INFO]: Running Klayout to re-generate GDS-II...</font>
+<font color="#00AAAA">[INFO]: Streaming out GDS II...</font>
+<font color="#00AAAA">[INFO]: current step index: 32</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">Design Name: user_proj_example</font>
+<font color="#AAAAAA">Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds</font>
+<font color="#AAAAAA">Extra GDSes:</font>
+<font color="#AAAAAA">/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/gds/sky130_fd_sc_ls.gds /project/openlane/user_proj_example/../../cells/gds/HAX1.gds /project/openlane/user_proj_example/../../cells/gds/INVX8.gds /project/openlane/user_proj_example/../../cells/gds/AND2X2.gds /project/openlane/user_proj_example/../../cells/gds/XNOR2X1.gds /project/openlane/user_proj_example/../../cells/gds/OAI22X1.gds /project/openlane/user_proj_example/../../cells/gds/AOI21X1.gds /project/openlane/user_proj_example/../../cells/gds/NAND2X1.gds /project/openlane/user_proj_example/../../cells/gds/OAI21X1.gds /project/openlane/user_proj_example/../../cells/gds/INV.gds /project/openlane/user_proj_example/../../cells/gds/AOI22X1.gds /project/openlane/user_proj_example/../../cells/gds/OR2X1.gds /project/openlane/user_proj_example/../../cells/gds/INVX1.gds /project/openlane/user_proj_example/../../cells/gds/NOR2X1.gds /project/openlane/user_proj_example/../../cells/gds/MUX2X1.gds /project/openlane/user_proj_example/../../cells/gds/BUFX2.gds /project/openlane/user_proj_example/../../cells/gds/AND2X1.gds /project/openlane/user_proj_example/../../cells/gds/NAND3X1.gds /project/openlane/user_proj_example/../../cells/gds/INVX2.gds /project/openlane/user_proj_example/../../cells/gds/INVX4.gds</font>
+<font color="#AAAAAA">[INFO] Clearing cells...</font>
+<font color="#AAAAAA">[INFO] Merging GDS files...</font>
+ <font color="#AAAAAA">/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/gds/sky130_fd_sc_ls.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/HAX1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/INVX8.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/AND2X2.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/XNOR2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/OAI22X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/AOI21X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/NAND2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/OAI21X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/INV.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/AOI22X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/OR2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/INVX1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/NOR2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/MUX2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/BUFX2.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/AND2X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/NAND3X1.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/INVX2.gds</font>
+ <font color="#AAAAAA">/project/openlane/user_proj_example/../../cells/gds/INVX4.gds</font>
+<font color="#AAAAAA">[INFO] Copying toplevel cell 'user_proj_example'</font>
+<font color="#AAAAAA">WARNING: no fill config file specified</font>
+<font color="#AAAAAA">[INFO] Checking for missing GDS...</font>
+<font color="#AAAAAA">[INFO] All LEF cells have matching GDS cells</font>
+<font color="#AAAAAA">[INFO] Writing out GDS '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Back-up GDS-II streamed out.</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 33</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: Running XOR on the layouts using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 34</font>
+<font color="#AAAAAA">First Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds</font>
+<font color="#AAAAAA">Second Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds</font>
+<font color="#AAAAAA">Design Name: user_proj_example</font>
+<font color="#AAAAAA">Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds ..</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds ..</font>
+<font color="#AAAAAA">--- Running XOR for 122/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.350s</font>
+<font color="#AAAAAA">XOR differences: 123</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 235/4 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">XOR differences: 1</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 236/0 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.670s</font>
+<font color="#AAAAAA">XOR differences: 3</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 237/0 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">XOR differences: 1</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 64/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.330s</font>
+<font color="#AAAAAA">XOR differences: 162</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 64/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.660s</font>
+<font color="#AAAAAA">XOR differences: 35</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 64/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.150s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 64/59 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.150s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 65/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.840s</font>
+<font color="#AAAAAA">XOR differences: 14889</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 65/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.100s</font>
+<font color="#AAAAAA">XOR differences: 1905</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 66/15 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 846</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 66/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 1.920s</font>
+<font color="#AAAAAA">XOR differences: 17698</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 66/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 3.010s</font>
+<font color="#AAAAAA">XOR differences: 99044</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.110s</font>
+<font color="#AAAAAA">--- Running XOR for 67/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.270s</font>
+<font color="#AAAAAA">XOR differences: 16501</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 67/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 4.590s</font>
+<font color="#AAAAAA">XOR differences: 2548</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 67/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 2.290s</font>
+<font color="#AAAAAA">XOR differences: 55661</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.070s</font>
+<font color="#AAAAAA">--- Running XOR for 67/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.070s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 68/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.600s</font>
+<font color="#AAAAAA">XOR differences: 210</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 68/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 1.250s</font>
+<font color="#AAAAAA">XOR differences: 1734</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 68/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.100s</font>
+<font color="#AAAAAA">XOR differences: 4684</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 68/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.180s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 978</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.280s</font>
+<font color="#AAAAAA">XOR differences: 2002</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 1344</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.090s</font>
+<font color="#AAAAAA">--- Running XOR for 70/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 340</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 70/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 1328</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 71/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">XOR differences: 31</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 71/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 31</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 71/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 78/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.380s</font>
+<font color="#AAAAAA">XOR differences: 6545</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 81/23 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">XOR differences: 410</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 81/4 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.630s</font>
+<font color="#AAAAAA">XOR differences: 3</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 83/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.160s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 93/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.640s</font>
+<font color="#AAAAAA">XOR differences: 933</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 94/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.620s</font>
+<font color="#AAAAAA">XOR differences: 890</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 95/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.320s</font>
+<font color="#AAAAAA">XOR differences: 1616</font>
+<font color="#AAAAAA">"_output" in: xor.drc:41</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">Writing layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds ..</font>
+<font color="#AAAAAA">Total run time: 25.760s</font>
+<font color="#00AAAA">[INFO]: Taking a Screenshot of the Layout Using Klayout...</font>
+<font color="#00AAAA">[INFO]: current step index: 35</font>
+<font color="#AAAAAA">Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds</font>
+<font color="#AAAAAA">[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt</font>
+<font color="#AAAAAA">[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds</font>
+<font color="#AAAAAA">Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=2407014, record number=149179, cell=XOR)</font>
+<font color="#AAAAAA">Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=12613030, record number=756854, cell=XOR)</font>
+<font color="#AAAAAA">Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=12658406, record number=756859, cell=XOR)</font>
+<font color="#AAAAAA">[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds.png'</font>
+<font color="#AAAAAA">Done</font>
+<font color="#00AAAA">[INFO]: Screenshot taken.</font>
+<font color="#00AAAA">[INFO]: current step index: 36</font>
+<font color="#AAAAAA">First Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds</font>
+<font color="#AAAAAA">Second Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds</font>
+<font color="#AAAAAA">Design Name: user_proj_example</font>
+<font color="#AAAAAA">Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.xml</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds ..</font>
+<font color="#AAAAAA">Reading /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds ..</font>
+<font color="#AAAAAA">--- Running XOR for 122/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.340s</font>
+<font color="#AAAAAA">XOR differences: 123</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 235/4 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 1</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 236/0 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.680s</font>
+<font color="#AAAAAA">XOR differences: 3</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 237/0 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">XOR differences: 1</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 64/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.320s</font>
+<font color="#AAAAAA">XOR differences: 162</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 64/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.650s</font>
+<font color="#AAAAAA">XOR differences: 35</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 64/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.160s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 64/59 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.160s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 65/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.850s</font>
+<font color="#AAAAAA">XOR differences: 14889</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.100s</font>
+<font color="#AAAAAA">--- Running XOR for 65/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.100s</font>
+<font color="#AAAAAA">XOR differences: 1905</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 66/15 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 846</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 66/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 1.930s</font>
+<font color="#AAAAAA">XOR differences: 17698</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.140s</font>
+<font color="#AAAAAA">--- Running XOR for 66/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 2.920s</font>
+<font color="#AAAAAA">XOR differences: 99044</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.670s</font>
+<font color="#AAAAAA">--- Running XOR for 67/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.270s</font>
+<font color="#AAAAAA">XOR differences: 16501</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.120s</font>
+<font color="#AAAAAA">--- Running XOR for 67/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 4.560s</font>
+<font color="#AAAAAA">XOR differences: 2548</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.070s</font>
+<font color="#AAAAAA">--- Running XOR for 67/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 2.340s</font>
+<font color="#AAAAAA">XOR differences: 55661</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.310s</font>
+<font color="#AAAAAA">--- Running XOR for 67/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.070s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 68/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.620s</font>
+<font color="#AAAAAA">XOR differences: 210</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">--- Running XOR for 68/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 1.250s</font>
+<font color="#AAAAAA">XOR differences: 1734</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 68/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.110s</font>
+<font color="#AAAAAA">XOR differences: 4684</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">--- Running XOR for 68/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.170s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.070s</font>
+<font color="#AAAAAA">XOR differences: 978</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 69/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.290s</font>
+<font color="#AAAAAA">XOR differences: 2002</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 69/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 1344</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 69/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 70/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 340</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 70/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 1328</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 71/16 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">XOR differences: 31</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 71/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">XOR differences: 31</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 71/5 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">--- Running XOR for 78/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.020s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.380s</font>
+<font color="#AAAAAA">XOR differences: 6545</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.050s</font>
+<font color="#AAAAAA">--- Running XOR for 81/23 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.060s</font>
+<font color="#AAAAAA">XOR differences: 410</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 81/4 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.650s</font>
+<font color="#AAAAAA">XOR differences: 3</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 83/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.160s</font>
+<font color="#AAAAAA">XOR differences: 0</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 93/44 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.650s</font>
+<font color="#AAAAAA">XOR differences: 933</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 94/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.630s</font>
+<font color="#AAAAAA">XOR differences: 890</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">--- Running XOR for 95/20 ---</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"_input" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.030s</font>
+<font color="#AAAAAA">"^" in: xor.drc:38</font>
+<font color="#AAAAAA">Elapsed: 0.330s</font>
+<font color="#AAAAAA">XOR differences: 1616</font>
+<font color="#AAAAAA">"_output" in: xor.drc:40</font>
+<font color="#AAAAAA">Elapsed: 0.040s</font>
+<font color="#AAAAAA">Writing report database: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.xml ..</font>
+<font color="#AAAAAA">Total run time: 42.890s</font>
+<font color="#00AAAA">[INFO]: Klayout XOR Complete</font>
+<font color="#00AAAA">[INFO]: Running Magic Spice Export from LEF...</font>
+<font color="#00AAAA">[INFO]: current step index: 37</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/project/openlane/user_proj_example/runs/user_proj_example/tmp/magic_spice.tcl" from command line.</font>
+<font color="#AAAAAA">Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.</font>
+<font color="#AAAAAA">LEF read: Processed 769 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 65 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 79 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 81 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 62 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 68 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 90 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 74 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 64 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA">LEF read: Processed 53 lines.</font>
+<font color="#AAAAAA">Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.</font>
+<font color="#AAAAAA">This action cannot be undone.</font>
+<font color="#AAAAAA"> Processed 5 vias total.</font>
+<font color="#AAAAAA"> Processed 9333 subcell instances total.</font>
+<font color="#AAAAAA"> Processed 620 pins total.</font>
+<font color="#AAAAAA"> Processed 8 special nets total.</font>
+<font color="#AAAAAA"> Processed 1208 nets total.</font>
+<font color="#AAAAAA">DEF read: Processed 21075 lines.</font>
+<font color="#AAAAAA">Processing user_proj_example</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__clkbuf_4 into sky130_fd_sc_ls__clkbuf_4.ext:</font>
+<font color="#AAAAAA">Extracting HAX1 into HAX1.ext:</font>
+<font color="#AAAAAA">Extracting XNOR2X1 into XNOR2X1.ext:</font>
+<font color="#AAAAAA">Extracting NOR2X1 into NOR2X1.ext:</font>
+<font color="#AAAAAA">Extracting NAND2X1 into NAND2X1.ext:</font>
+<font color="#AAAAAA">Extracting BUFX2 into BUFX2.ext:</font>
+<font color="#AAAAAA">Extracting AND2X1 into AND2X1.ext:</font>
+<font color="#AAAAAA">Extracting AND2X2 into AND2X2.ext:</font>
+<font color="#AAAAAA">Extracting NAND3X1 into NAND3X1.ext:</font>
+<font color="#AAAAAA">Extracting OR2X1 into OR2X1.ext:</font>
+<font color="#AAAAAA">Extracting AOI21X1 into AOI21X1.ext:</font>
+<font color="#AAAAAA">Extracting MUX2X1 into MUX2X1.ext:</font>
+<font color="#AAAAAA">Extracting OAI22X1 into OAI22X1.ext:</font>
+<font color="#AAAAAA">Extracting INVX1 into INVX1.ext:</font>
+<font color="#AAAAAA">Extracting AOI22X1 into AOI22X1.ext:</font>
+<font color="#AAAAAA">Extracting INV into INV.ext:</font>
+<font color="#AAAAAA">Extracting INVX4 into INVX4.ext:</font>
+<font color="#AAAAAA">Extracting INVX2 into INVX2.ext:</font>
+<font color="#AAAAAA">Extracting INVX8 into INVX8.ext:</font>
+<font color="#AAAAAA">Extracting OAI21X1 into OAI21X1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__diode_2 into sky130_fd_sc_ls__diode_2.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__conb_1 into sky130_fd_sc_ls__conb_1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__buf_1 into sky130_fd_sc_ls__buf_1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__clkbuf_2 into sky130_fd_sc_ls__clkbuf_2.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__buf_2 into sky130_fd_sc_ls__buf_2.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__fill_1 into sky130_fd_sc_ls__fill_1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__fill_diode_2 into sky130_fd_sc_ls__fill_diode_2.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__tapvpwrvgnd_1 into sky130_fd_sc_ls__tapvpwrvgnd_1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__decap_8 into sky130_fd_sc_ls__decap_8.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__clkbuf_1 into sky130_fd_sc_ls__clkbuf_1.ext:</font>
+<font color="#AAAAAA">Extracting sky130_fd_sc_ls__decap_4 into sky130_fd_sc_ls__decap_4.ext:</font>
+<font color="#AAAAAA">Extracting user_proj_example into user_proj_example.ext:</font>
+<font color="#AAAAAA">exttospice finished.</font>
+<font color="#AAAAAA">Using technology "sky130A", version 1.0.156-0-g7e29496</font>
+<font color="#00AAAA">[INFO]: No Illegal overlaps detected during extraction.</font>
+<font color="#00AAAA">[INFO]: Saving Magic Views in /project</font>
+<font color="#00AAAA">[INFO]: Running LEF LVS...</font>
+<font color="#00AAAA">[INFO]: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.spice against /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v</font>
+<font color="#00AAAA">[INFO]: current step index: 38</font>
+<font color="#AAAAAA">Netgen 1.5.167 compiled on Wed Feb 17 03:29:37 UTC 2021</font>
+<font color="#AAAAAA">Warning: netgen command 'format' use fully-qualified name '::netgen::format'</font>
+<font color="#AAAAAA">Warning: netgen command 'global' use fully-qualified name '::netgen::global'</font>
+<font color="#AAAAAA">Generating JSON file result</font>
+<font color="#AAAAAA">Reading netlist file /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.spice</font>
+<font color="#AAAAAA">Reading netlist file /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v</font>
+<font color="#AAAAAA">Warning: A case-insensitive file has been read and so the</font> <font color="#AAAAAA">verilog file must be treated case-insensitive to match.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module AND2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module AND2X2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module AOI21X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module AOI22X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module BUFX2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module HAX1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module INV.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module INVX1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module INVX2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module INVX4.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module INVX8.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module MUX2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module NAND2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module NAND3X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module NOR2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module OAI21X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module OAI22X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module OR2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module XNOR2X1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__conb_1.</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _024_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _025_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _026_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _027_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _028_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _029_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _030_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _031_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _032_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _033_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _034_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _035_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _036_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _037_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _038_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _039_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _040_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _041_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _042_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _043_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _044_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _045_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _046_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _047_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _048_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _049_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _050_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _051_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _052_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _053_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _054_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _055_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _056_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _057_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _058_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _059_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _060_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _061_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _062_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _063_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _064_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _065_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _066_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _067_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _068_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _069_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _070_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _071_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _072_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _073_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _074_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _075_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _076_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _077_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _078_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _079_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _080_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _081_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _082_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _083_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _084_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _085_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _086_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _087_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _088_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _089_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _090_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _091_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _092_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _093_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _094_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _095_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _096_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _097_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _098_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _099_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _100_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _101_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _102_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _103_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _104_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _105_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _106_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _107_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _108_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _109_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _110_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _111_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _112_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _113_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _114_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _115_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _116_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _117_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _118_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _119_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _120_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _121_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _122_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _123_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _124_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _125_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _126_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _127_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _128_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _129_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _130_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _131_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _132_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _133_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _134_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _135_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _136_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _137_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _138_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _139_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _140_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _141_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _142_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _143_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _144_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _145_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _146_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _147_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _148_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _149_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _150_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _151_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _152_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _153_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _154_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _155_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _156_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _157_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _158_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _159_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _160_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _161_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _162_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _163_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _164_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _165_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _166_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _167_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _168_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _169_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _170_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _171_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _172_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _173_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _174_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _175_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _176_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _177_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _178_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _179_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _180_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _181_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _182_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _183_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _184_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _185_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _186_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _187_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _188_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _189_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _190_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _191_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _192_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _193_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _194_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _195_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _196_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _197_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _198_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _199_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _200_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _201_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _202_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _203_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _204_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _205_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _206_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _207_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _208_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _209_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _210_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _211_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _212_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _213_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _214_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _215_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Note: Implicit pin HI in instance _216_ of sky130_fd_sc_ls__conb_1 in cell user_proj_example</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__decap_4.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__tapvpwrvgnd_1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__clkbuf_1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__clkbuf_2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__buf_2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__buf_1.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__clkbuf_4.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__diode_2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__decap_8.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__fill_diode_2.</font>
+<font color="#AAAAAA">Creating placeholder cell definition for module sky130_fd_sc_ls__fill_1.</font>
+<font color="#AAAAAA">Reading setup file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/netgen/sky130A_setup.tcl</font>
+<font color="#AAAAAA">Comparison output logged to file /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.lef.log</font>
+<font color="#AAAAAA">Logging to file "/project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.lef.log" enabled</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__decap_8'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_8 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__decap_8'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_8 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_8 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__fill_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__fill_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__fill_diode_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_diode_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__fill_diode_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_diode_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__fill_diode_2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__decap_4'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__decap_4'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__decap_4 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__diode_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__diode_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__diode_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__diode_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__diode_2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__clkbuf_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__clkbuf_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__tapvpwrvgnd_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__tapvpwrvgnd_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 2 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__tapvpwrvgnd_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__tapvpwrvgnd_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__tapvpwrvgnd_1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__conb_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__conb_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__conb_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__conb_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__conb_1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__clkbuf_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__clkbuf_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'NAND2X1'</font>
+<font color="#AAAAAA">Circuit NAND2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'NAND2X1'</font>
+<font color="#AAAAAA">Circuit NAND2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit NAND2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__buf_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__buf_2'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__buf_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__buf_1'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__buf_1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'XNOR2X1'</font>
+<font color="#AAAAAA">Circuit XNOR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'XNOR2X1'</font>
+<font color="#AAAAAA">Circuit XNOR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit XNOR2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'AOI21X1'</font>
+<font color="#AAAAAA">Circuit AOI21X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'AOI21X1'</font>
+<font color="#AAAAAA">Circuit AOI21X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit AOI21X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'INVX1'</font>
+<font color="#AAAAAA">Circuit INVX1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'INVX1'</font>
+<font color="#AAAAAA">Circuit INVX1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit INVX1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'INVX2'</font>
+<font color="#AAAAAA">Circuit INVX2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'INVX2'</font>
+<font color="#AAAAAA">Circuit INVX2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit INVX2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'NOR2X1'</font>
+<font color="#AAAAAA">Circuit NOR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'NOR2X1'</font>
+<font color="#AAAAAA">Circuit NOR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit NOR2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'INVX4'</font>
+<font color="#AAAAAA">Circuit INVX4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'INVX4'</font>
+<font color="#AAAAAA">Circuit INVX4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit INVX4 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'OR2X1'</font>
+<font color="#AAAAAA">Circuit OR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'OR2X1'</font>
+<font color="#AAAAAA">Circuit OR2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit OR2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'INVX8'</font>
+<font color="#AAAAAA">Circuit INVX8 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'INVX8'</font>
+<font color="#AAAAAA">Circuit INVX8 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit INVX8 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'OAI22X1'</font>
+<font color="#AAAAAA">Circuit OAI22X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 7 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'OAI22X1'</font>
+<font color="#AAAAAA">Circuit OAI22X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit OAI22X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'BUFX2'</font>
+<font color="#AAAAAA">Circuit BUFX2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'BUFX2'</font>
+<font color="#AAAAAA">Circuit BUFX2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit BUFX2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'NAND3X1'</font>
+<font color="#AAAAAA">Circuit NAND3X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'NAND3X1'</font>
+<font color="#AAAAAA">Circuit NAND3X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit NAND3X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'INV'</font>
+<font color="#AAAAAA">Circuit INV contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 4 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'INV'</font>
+<font color="#AAAAAA">Circuit INV contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit INV contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'sky130_fd_sc_ls__clkbuf_4'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'sky130_fd_sc_ls__clkbuf_4'</font>
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_4 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit sky130_fd_sc_ls__clkbuf_4 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'AOI22X1'</font>
+<font color="#AAAAAA">Circuit AOI22X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 7 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'AOI22X1'</font>
+<font color="#AAAAAA">Circuit AOI22X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit AOI22X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'MUX2X1'</font>
+<font color="#AAAAAA">Circuit MUX2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'MUX2X1'</font>
+<font color="#AAAAAA">Circuit MUX2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit MUX2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'AND2X1'</font>
+<font color="#AAAAAA">Circuit AND2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'AND2X1'</font>
+<font color="#AAAAAA">Circuit AND2X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit AND2X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'AND2X2'</font>
+<font color="#AAAAAA">Circuit AND2X2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 5 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'AND2X2'</font>
+<font color="#AAAAAA">Circuit AND2X2 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit AND2X2 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'OAI21X1'</font>
+<font color="#AAAAAA">Circuit OAI21X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'OAI21X1'</font>
+<font color="#AAAAAA">Circuit OAI21X1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit OAI21X1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'HAX1'</font>
+<font color="#AAAAAA">Circuit HAX1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets, and 6 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'HAX1'</font>
+<font color="#AAAAAA">Circuit HAX1 contains 0 device instances.</font>
+<font color="#AAAAAA">Circuit contains 0 nets.</font>
+
+<font color="#AAAAAA">Circuit HAX1 contains no devices.</font>
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'user_proj_example'</font>
+<font color="#AAAAAA">Circuit user_proj_example contains 9333 device instances.</font>
+<font color="#AAAAAA"> Class: OR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: MUX2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: INV instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_4 instances: 1464</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_8 instances: 4545</font>
+<font color="#AAAAAA"> Class: NAND3X1 instances: 1</font>
+<font color="#AAAAAA"> Class: HAX1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_1 instances: 351</font>
+<font color="#AAAAAA"> Class: OAI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_1 instances: 333</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_2 instances: 242</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_4 instances: 3</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__diode_2 instances: 230</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_diode_2 instances: 1021</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__tapvpwrvgnd_1 instances: 882</font>
+<font color="#AAAAAA"> Class: XNOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: BUFX2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__conb_1 instances: 217</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_1 instances: 11</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_2 instances: 15</font>
+<font color="#AAAAAA"> Class: AND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AND2X2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX1 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX4 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX8 instances: 1</font>
+<font color="#AAAAAA">Circuit contains 1427 nets, and 12 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'user_proj_example'</font>
+<font color="#AAAAAA">Circuit user_proj_example contains 9333 device instances.</font>
+<font color="#AAAAAA"> Class: OR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: MUX2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: INV instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_4 instances: 1464</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_8 instances: 4545</font>
+<font color="#AAAAAA"> Class: NAND3X1 instances: 1</font>
+<font color="#AAAAAA"> Class: HAX1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_1 instances: 351</font>
+<font color="#AAAAAA"> Class: OAI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_1 instances: 333</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_2 instances: 242</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_4 instances: 3</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__diode_2 instances: 230</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_diode_2 instances: 1021</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__tapvpwrvgnd_1 instances: 882</font>
+<font color="#AAAAAA"> Class: XNOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: BUFX2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__conb_1 instances: 217</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_1 instances: 11</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_2 instances: 15</font>
+<font color="#AAAAAA"> Class: AND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AND2X2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX1 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX4 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX8 instances: 1</font>
+<font color="#AAAAAA">Circuit contains 1403 nets, and 6 disconnected pins.</font>
+
+<font color="#AAAAAA">Circuit was modified by parallel/series device merging.</font>
+<font color="#AAAAAA">New circuit summary:</font>
+
+<font color="#AAAAAA">Contents of circuit 1: Circuit: 'user_proj_example'</font>
+<font color="#AAAAAA">Circuit user_proj_example contains 963 device instances.</font>
+<font color="#AAAAAA"> Class: OR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: MUX2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: INV instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_4 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_8 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND3X1 instances: 1</font>
+<font color="#AAAAAA"> Class: HAX1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_1 instances: 333</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_2 instances: 242</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_4 instances: 3</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__diode_2 instances: 118</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_diode_2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__tapvpwrvgnd_1 instances: 1</font>
+<font color="#AAAAAA"> Class: XNOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: BUFX2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__conb_1 instances: 217</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_1 instances: 11</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_2 instances: 15</font>
+<font color="#AAAAAA"> Class: AND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AND2X2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX1 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX4 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX8 instances: 1</font>
+<font color="#AAAAAA">Circuit contains 1427 nets, and 12 disconnected pins.</font>
+<font color="#AAAAAA">Contents of circuit 2: Circuit: 'user_proj_example'</font>
+<font color="#AAAAAA">Circuit user_proj_example contains 963 device instances.</font>
+<font color="#AAAAAA"> Class: OR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: MUX2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: INV instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_4 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__decap_8 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND3X1 instances: 1</font>
+<font color="#AAAAAA"> Class: HAX1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI22X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AOI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: NAND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: OAI21X1 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_1 instances: 333</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_2 instances: 242</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__clkbuf_4 instances: 3</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__diode_2 instances: 118</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__fill_diode_2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__tapvpwrvgnd_1 instances: 1</font>
+<font color="#AAAAAA"> Class: XNOR2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: BUFX2 instances: 1</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__conb_1 instances: 217</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_1 instances: 11</font>
+<font color="#AAAAAA"> Class: sky130_fd_sc_ls__buf_2 instances: 15</font>
+<font color="#AAAAAA"> Class: AND2X1 instances: 1</font>
+<font color="#AAAAAA"> Class: AND2X2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX1 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX2 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX4 instances: 1</font>
+<font color="#AAAAAA"> Class: INVX8 instances: 1</font>
+<font color="#AAAAAA">Circuit contains 1403 nets, and 6 disconnected pins.</font>
+
+<font color="#AAAAAA">Circuit 1 contains 963 devices, Circuit 2 contains 963 devices.</font>
+<font color="#AAAAAA">Circuit 1 contains 1403 nets, Circuit 2 contains 1403 nets.</font>
+
+<font color="#AAAAAA">Circuits match with 21 symmetries.</font>
+<font color="#AAAAAA">Resolving automorphisms by property value.</font>
+<font color="#AAAAAA">Resolving automorphisms by pin name.</font>
+<font color="#AAAAAA">Netlists match with 2 symmetries.</font>
+<font color="#AAAAAA">Circuits match correctly.</font>
+<font color="#AAAAAA">Result: Circuits match uniquely.</font>
+<font color="#AAAAAA">Logging to file "/project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.lef.log" disabled</font>
+<font color="#AAAAAA">LVS Done.</font>
+<font color="#AAAAAA">LVS reports no net, device, pin, or property mismatches.</font>
+
+<font color="#AAAAAA">Total errors = 0</font>
+<font color="#00AAAA">[INFO]: No LVS mismatches.</font>
+<font color="#00AAAA">[INFO]: Running Magic DRC...</font>
+<font color="#00AAAA">[INFO]: current step index: 39</font>
+
+<font color="#AAAAAA">Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.</font>
+<font color="#AAAAAA">Starting magic under Tcl interpreter</font>
+<font color="#AAAAAA">Using the terminal as the console.</font>
+<font color="#AAAAAA">Using NULL graphics device.</font>
+<font color="#AAAAAA">Processing system .magicrc file</font>
+<font color="#AAAAAA">Sourcing design .magicrc for technology sky130A ...</font>
+<font color="#AAAAAA">2 Magic internal units = 1 Lambda</font>
+<font color="#AAAAAA">Input style sky130(): scaleFactor=2, multiplier=2</font>
+<font color="#AAAAAA">Scaled tech values by 2 / 1 to match internal grid scaling</font>
+<font color="#AAAAAA">Loading sky130A Device Generator Menu ...</font>
+<font color="#AAAAAA">Loading "/openLANE_flow/scripts/magic/drc.tcl" from command line.</font>
+<font color="#AAAAAA">Warning: Calma reading is not undoable! I hope that's OK.</font>
+<font color="#AAAAAA">Library written using GDS-II Release 3.0</font>
+<font color="#AAAAAA">Library name: user_proj_example</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__decap_4".</font>
+<font color="#AAAAAA">CIF file read warning: CIF style sky130(): units rescaled by factor of 5 / 1</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__decap_8".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__tapvpwrvgnd_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__fill_diode_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__fill_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__buf_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_2".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__buf_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__conb_1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__diode_2".</font>
+<font color="#AAAAAA">Reading "OAI21X1".</font>
+<font color="#AAAAAA">Reading "INVX8".</font>
+<font color="#AAAAAA">Reading "INVX2".</font>
+<font color="#AAAAAA">Reading "INVX4".</font>
+<font color="#AAAAAA">Reading "INV".</font>
+<font color="#AAAAAA">Reading "AOI22X1".</font>
+<font color="#AAAAAA">Reading "INVX1".</font>
+<font color="#AAAAAA">Reading "OAI22X1".</font>
+<font color="#AAAAAA">Reading "MUX2X1".</font>
+<font color="#AAAAAA">Reading "AOI21X1".</font>
+<font color="#AAAAAA">Reading "OR2X1".</font>
+<font color="#AAAAAA">Reading "NAND3X1".</font>
+<font color="#AAAAAA">Reading "AND2X2".</font>
+<font color="#AAAAAA">Reading "AND2X1".</font>
+<font color="#AAAAAA">Reading "BUFX2".</font>
+<font color="#AAAAAA">Reading "NAND2X1".</font>
+<font color="#AAAAAA">Reading "NOR2X1".</font>
+<font color="#AAAAAA">Reading "XNOR2X1".</font>
+<font color="#AAAAAA">Reading "HAX1".</font>
+<font color="#AAAAAA">Reading "sky130_fd_sc_ls__clkbuf_4".</font>
+<font color="#AAAAAA">Reading "user_proj_example".</font>
+<font color="#AAAAAA"> 100 uses</font>
+<font color="#AAAAAA"> 200 uses</font>
+<font color="#AAAAAA"> 300 uses</font>
+<font color="#AAAAAA"> 400 uses</font>
+<font color="#AAAAAA"> 500 uses</font>
+<font color="#AAAAAA"> 600 uses</font>
+<font color="#AAAAAA"> 700 uses</font>
+<font color="#AAAAAA"> 800 uses</font>
+<font color="#AAAAAA"> 900 uses</font>
+<font color="#AAAAAA"> 1000 uses</font>
+<font color="#AAAAAA"> 1100 uses</font>
+<font color="#AAAAAA"> 1200 uses</font>
+<font color="#AAAAAA"> 1300 uses</font>
+<font color="#AAAAAA"> 1400 uses</font>
+<font color="#AAAAAA"> 1500 uses</font>
+<font color="#AAAAAA"> 1600 uses</font>
+<font color="#AAAAAA"> 1700 uses</font>
+<font color="#AAAAAA"> 1800 uses</font>
+<font color="#AAAAAA"> 1900 uses</font>
+<font color="#AAAAAA"> 2000 uses</font>
+<font color="#AAAAAA"> 2100 uses</font>
+<font color="#AAAAAA"> 2200 uses</font>
+<font color="#AAAAAA"> 2300 uses</font>
+<font color="#AAAAAA"> 2400 uses</font>
+<font color="#AAAAAA"> 2500 uses</font>
+<font color="#AAAAAA"> 2600 uses</font>
+<font color="#AAAAAA"> 2700 uses</font>
+<font color="#AAAAAA"> 2800 uses</font>
+<font color="#AAAAAA"> 2900 uses</font>
+<font color="#AAAAAA"> 3000 uses</font>
+<font color="#AAAAAA"> 3100 uses</font>
+<font color="#AAAAAA"> 3200 uses</font>
+<font color="#AAAAAA"> 3300 uses</font>
+<font color="#AAAAAA"> 3400 uses</font>
+<font color="#AAAAAA"> 3500 uses</font>
+<font color="#AAAAAA"> 3600 uses</font>
+<font color="#AAAAAA"> 3700 uses</font>
+<font color="#AAAAAA"> 3800 uses</font>
+<font color="#AAAAAA"> 3900 uses</font>
+<font color="#AAAAAA"> 4000 uses</font>
+<font color="#AAAAAA"> 4100 uses</font>
+<font color="#AAAAAA"> 4200 uses</font>
+<font color="#AAAAAA"> 4300 uses</font>
+<font color="#AAAAAA"> 4400 uses</font>
+<font color="#AAAAAA"> 4500 uses</font>
+<font color="#AAAAAA"> 4600 uses</font>
+<font color="#AAAAAA"> 4700 uses</font>
+<font color="#AAAAAA"> 4800 uses</font>
+<font color="#AAAAAA"> 4900 uses</font>
+<font color="#AAAAAA"> 5000 uses</font>
+<font color="#AAAAAA"> 5100 uses</font>
+<font color="#AAAAAA"> 5200 uses</font>
+<font color="#AAAAAA"> 5300 uses</font>
+<font color="#AAAAAA"> 5400 uses</font>
+<font color="#AAAAAA"> 5500 uses</font>
+<font color="#AAAAAA"> 5600 uses</font>
+<font color="#AAAAAA"> 5700 uses</font>
+<font color="#AAAAAA"> 5800 uses</font>
+<font color="#AAAAAA"> 5900 uses</font>
+<font color="#AAAAAA"> 6000 uses</font>
+<font color="#AAAAAA"> 6100 uses</font>
+<font color="#AAAAAA"> 6200 uses</font>
+<font color="#AAAAAA"> 6300 uses</font>
+<font color="#AAAAAA"> 6400 uses</font>
+<font color="#AAAAAA"> 6500 uses</font>
+<font color="#AAAAAA"> 6600 uses</font>
+<font color="#AAAAAA"> 6700 uses</font>
+<font color="#AAAAAA"> 6800 uses</font>
+<font color="#AAAAAA"> 6900 uses</font>
+<font color="#AAAAAA"> 7000 uses</font>
+<font color="#AAAAAA"> 7100 uses</font>
+<font color="#AAAAAA"> 7200 uses</font>
+<font color="#AAAAAA"> 7300 uses</font>
+<font color="#AAAAAA"> 7400 uses</font>
+<font color="#AAAAAA"> 7500 uses</font>
+<font color="#AAAAAA"> 7600 uses</font>
+<font color="#AAAAAA"> 7700 uses</font>
+<font color="#AAAAAA"> 7800 uses</font>
+<font color="#AAAAAA"> 7900 uses</font>
+<font color="#AAAAAA"> 8000 uses</font>
+<font color="#AAAAAA"> 8100 uses</font>
+<font color="#AAAAAA"> 8200 uses</font>
+<font color="#AAAAAA"> 8300 uses</font>
+<font color="#AAAAAA"> 8400 uses</font>
+<font color="#AAAAAA"> 8500 uses</font>
+<font color="#AAAAAA"> 8600 uses</font>
+<font color="#AAAAAA"> 8700 uses</font>
+<font color="#AAAAAA"> 8800 uses</font>
+<font color="#AAAAAA"> 8900 uses</font>
+<font color="#AAAAAA"> 9000 uses</font>
+<font color="#AAAAAA"> 9100 uses</font>
+<font color="#AAAAAA"> 9200 uses</font>
+<font color="#AAAAAA"> 9300 uses</font>
+<font color="#AAAAAA">[INFO]: Loading user_proj_example</font>
+
+<font color="#AAAAAA">DRC style is now "drc(full)"</font>
+<font color="#AAAAAA">Loading DRC CIF style.</font>
+<font color="#AAAAAA">[INFO]: COUNT: 4837</font>
+<font color="#AAAAAA">[INFO]: Should be divided by 3 or 4</font>
+<font color="#AAAAAA">[INFO]: DRC Checking DONE (/project/openlane/user_proj_example/runs/user_proj_example/reports/magic/39-magic.drc)</font>
+<font color="#AAAAAA">[INFO]: Saving mag view with DRC errors(/project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.drc.mag)</font>
+<font color="#AAAAAA">[INFO]: Saved</font>
+<font color="#00AAAA">[INFO]: Converting Magic DRC Violations to Magic Readable Format...</font>
+<font color="#00AAAA">[INFO]: Converting Magic DRC Violations to Klayout XML Database...</font>
+<font color="#00AAAA">[INFO]: Converting DRC Violations to RDB Format...</font>
+<font color="#00AAAA">[INFO]: Converted DRC Violations to RDB Format</font>
+<font color="#AA0000">[ERROR]: There are violations in the design after Magic DRC.</font>
+<font color="#AA0000">[ERROR]: Total Number of violations is 4837</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow failed for user_proj_example/13-06_18-43 in 0h10m16s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Magic DRC Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/magic//39-magic.drc</font>
+<font color="#00AAAA">Violation Message "mcon.spacing < 0.19um (mcon.2) "found 200 Times.</font>
+<font color="#00AAAA">Violation Message "Local interconnect spacing < 0.17um (li.3) "found 945 Times.</font>
+<font color="#00AAAA">Violation Message "Local interconnect width < 0.17um (li.1) "found 1 Times.</font>
+<font color="#00AAAA">Violation Message "N-well spacing < 1.27um (nwell.2a) "found 201 Times.</font>
+<font color="#00AAAA">Violation Message "This layer can't abut or partially overlap between subcells "found 8 Times.</font>
+<font color="#00AAAA">Violation Message "Metal1 spacing < 0.14um (met1.2) "found 85 Times.</font>
+<font color="#00AAAA">Violation Message "N-well overlap of P-Diffusion < 0.18um (diff/tap.8) "found 2145 Times.</font>
+<font color="#00AAAA">Violation Message "N-well width < 0.84um (nwell.1) "found 310 Times.</font>
+<font color="#00AAAA">Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 59 Times.</font>
+<font color="#00AAAA">Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 149 Times.</font>
+<font color="#00AAAA">Violation Message "Metal1 width < 0.14um (met1.1) "found 4 Times.</font>
+<font color="#00AAAA">Violation Message "Core local interconnect spacing < 0.14um (li.c2) "found 373 Times.</font>
+<font color="#00AAAA">Violation Message "poly contact spacing to P-diffusion < 0.235um (licon.9 + psdm.5a) "found 357 Times.</font>
+<font color="#00AAAA">Total Magic DRC violations is 4837</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.lef.log</font>
+<font color="#00AAAA">LVS reports no net, device, pin, or property mismatches.</font>
+<font color="#00AAAA">Total errors = 0</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">No antenna report found.</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#AA0000">[ERROR]: Flow Failed.</font>
+<font color="#00AAAA">[INFO]: Running Antenna Checks...</font>
+<font color="#00AAAA">[INFO]: Running OpenROAD Antenna Rule Checker...</font>
+<font color="#00AAAA">[INFO]: current step index: 40</font>
+<font color="#AAAAAA">OpenROAD 0.9.0 1415572a73</font>
+<font color="#AAAAAA">This program is licensed under the BSD-3 license. See the LICENSE file for details.</font>
+<font color="#AAAAAA">Components of this program may be licensed under more restrictive licenses which must be honored.</font>
+<font color="#AAAAAA">Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: Created 13 technology layers</font>
+<font color="#AAAAAA">Notice 0: Created 25 technology vias</font>
+<font color="#AAAAAA">Notice 0: Created 418 library cells</font>
+<font color="#AAAAAA">Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef</font>
+<font color="#AAAAAA">Notice 0: </font>
+<font color="#AAAAAA">Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">Notice 0: Design: user_proj_example</font>
+<font color="#AAAAAA">Notice 0: Created 620 pins.</font>
+<font color="#AAAAAA">Notice 0: Created 9333 components and 37462 component-terminals.</font>
+<font color="#AAAAAA">Notice 0: Created 8 special nets and 0 connections.</font>
+<font color="#AAAAAA">Notice 0: Created 1208 nets and 1715 connections.</font>
+<font color="#AAAAAA">Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def</font>
+<font color="#AAAAAA">Notice 0: Split top of 7 T shapes.</font>
+<font color="#AAAAAA">Number of pins violated: 6</font>
+<font color="#AAAAAA">Number of nets violated: 6</font>
+<font color="#AAAAAA">Total number of nets: 1208</font>
+<font color="#00AAAA">[INFO]: current step index: 41</font>
+<font color="#00AAAA">[INFO]: Your design contains macros, which is not supported by the current integration of CVC. So CVC won't run, however CVC is just a check so it's not critical to your design.</font>
+<font color="#00AAAA">[INFO]: Calculating Runtime From the Start...</font>
+<font color="#00AAAA">[INFO]: Flow completed for user_proj_example/13-06_18-43 in 0h10m33s</font>
+<font color="#00AAAA">[INFO]: Generating Final Summary Report...</font>
+<font color="#00AAAA">[INFO]: Design Name: user_proj_example</font>
+<font color="#00AAAA">Run Directory: /project/openlane/user_proj_example/runs/user_proj_example</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Magic DRC Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/magic//39-magic.drc</font>
+<font color="#00AAAA">Violation Message "mcon.spacing < 0.19um (mcon.2) "found 200 Times.</font>
+<font color="#00AAAA">Violation Message "Local interconnect spacing < 0.17um (li.3) "found 945 Times.</font>
+<font color="#00AAAA">Violation Message "Local interconnect width < 0.17um (li.1) "found 1 Times.</font>
+<font color="#00AAAA">Violation Message "N-well spacing < 1.27um (nwell.2a) "found 201 Times.</font>
+<font color="#00AAAA">Violation Message "This layer can't abut or partially overlap between subcells "found 8 Times.</font>
+<font color="#00AAAA">Violation Message "Metal1 spacing < 0.14um (met1.2) "found 85 Times.</font>
+<font color="#00AAAA">Violation Message "N-well overlap of P-Diffusion < 0.18um (diff/tap.8) "found 2145 Times.</font>
+<font color="#00AAAA">Violation Message "N-well width < 0.84um (nwell.1) "found 310 Times.</font>
+<font color="#00AAAA">Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 59 Times.</font>
+<font color="#00AAAA">Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 149 Times.</font>
+<font color="#00AAAA">Violation Message "Metal1 width < 0.14um (met1.1) "found 4 Times.</font>
+<font color="#00AAAA">Violation Message "Core local interconnect spacing < 0.14um (li.c2) "found 373 Times.</font>
+<font color="#00AAAA">Violation Message "poly contact spacing to P-diffusion < 0.235um (licon.9 + psdm.5a) "found 357 Times.</font>
+<font color="#00AAAA">Total Magic DRC violations is 4837</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">LVS Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.lef.log</font>
+<font color="#00AAAA">LVS reports no net, device, pin, or property mismatches.</font>
+<font color="#00AAAA">Total errors = 0</font>
+<font color="#00AAAA">----------------------------------------</font>
+
+<font color="#00AAAA">Antenna Summary:</font>
+<font color="#00AAAA">Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing//41-antenna.rpt</font>
+<font color="#00AAAA">Number of pins violated: 6</font>
+<font color="#00AAAA">Number of nets violated: 6</font>
+<font color="#00AAAA">[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv</font>
+<font color="#00AA00">[SUCCESS]: Flow Completed Without Fatal Errors.</font>
+<font color="#AAAAAA">mkdir -p ../signoff/user_proj_example/</font>
+<font color="#AAAAAA">cp user_proj_example/runs/user_proj_example/OPENLANE_VERSION ../signoff/user_proj_example/</font>
+<font color="#AAAAAA">cp user_proj_example/runs/user_proj_example/PDK_SOURCES ../signoff/user_proj_example/</font>
+<font color="#AAAAAA">cp user_proj_example/runs/user_proj_example/reports/final_summary_report.csv ../signoff/user_proj_example/</font>
+<font color="#AAAAAA">make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen</font>
+<font color="#AAAAAA">Deployment done.</font>
+<font color="#AAAAAA">philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ </font>
+</pre>
diff --git a/cells/gds/AND2X1.gds b/cells/gds/AND2X1.gds
index a3dd72f..5341e19 100644
--- a/cells/gds/AND2X1.gds
+++ b/cells/gds/AND2X1.gds
Binary files differ
diff --git a/cells/gds/AND2X2.gds b/cells/gds/AND2X2.gds
index 5db1bd8..bb3bd73 100644
--- a/cells/gds/AND2X2.gds
+++ b/cells/gds/AND2X2.gds
Binary files differ
diff --git a/cells/gds/AOI21X1.gds b/cells/gds/AOI21X1.gds
index 3aab362..cde059d 100644
--- a/cells/gds/AOI21X1.gds
+++ b/cells/gds/AOI21X1.gds
Binary files differ
diff --git a/cells/gds/AOI22X1.gds b/cells/gds/AOI22X1.gds
index 8783482..7998a40 100644
--- a/cells/gds/AOI22X1.gds
+++ b/cells/gds/AOI22X1.gds
Binary files differ
diff --git a/cells/gds/BUFX2.gds b/cells/gds/BUFX2.gds
index e316621..9869800 100644
--- a/cells/gds/BUFX2.gds
+++ b/cells/gds/BUFX2.gds
Binary files differ
diff --git a/cells/gds/BUFX4.gds b/cells/gds/BUFX4.gds
deleted file mode 100644
index ae3c08a..0000000
--- a/cells/gds/BUFX4.gds
+++ /dev/null
Binary files differ
diff --git a/cells/gds/CLKBUF1.gds b/cells/gds/CLKBUF1.gds
deleted file mode 100644
index 81e2bed..0000000
--- a/cells/gds/CLKBUF1.gds
+++ /dev/null
Binary files differ
diff --git a/cells/gds/HAX1.gds b/cells/gds/HAX1.gds
index 865ce83..bd5f7f8 100644
--- a/cells/gds/HAX1.gds
+++ b/cells/gds/HAX1.gds
Binary files differ
diff --git a/cells/gds/INV.gds b/cells/gds/INV.gds
index f438358..d790f7f 100644
--- a/cells/gds/INV.gds
+++ b/cells/gds/INV.gds
Binary files differ
diff --git a/cells/gds/INVX1.gds b/cells/gds/INVX1.gds
index 9ee47af..2c556dd 100644
--- a/cells/gds/INVX1.gds
+++ b/cells/gds/INVX1.gds
Binary files differ
diff --git a/cells/gds/INVX2.gds b/cells/gds/INVX2.gds
index 3216ca0..55b1489 100644
--- a/cells/gds/INVX2.gds
+++ b/cells/gds/INVX2.gds
Binary files differ
diff --git a/cells/gds/INVX4.gds b/cells/gds/INVX4.gds
index ebf46b9..30b14dc 100644
--- a/cells/gds/INVX4.gds
+++ b/cells/gds/INVX4.gds
Binary files differ
diff --git a/cells/gds/INVX8.gds b/cells/gds/INVX8.gds
index 875c561..eb790b3 100644
--- a/cells/gds/INVX8.gds
+++ b/cells/gds/INVX8.gds
Binary files differ
diff --git a/cells/gds/LATCH.gds b/cells/gds/LATCH.gds
deleted file mode 100644
index cf892a1..0000000
--- a/cells/gds/LATCH.gds
+++ /dev/null
Binary files differ
diff --git a/cells/gds/LOFTY.gds b/cells/gds/LOFTY.gds
deleted file mode 100644
index 2e28ac4..0000000
--- a/cells/gds/LOFTY.gds
+++ /dev/null
Binary files differ
diff --git a/cells/gds/MUX2X1.gds b/cells/gds/MUX2X1.gds
new file mode 100644
index 0000000..e23f388
--- /dev/null
+++ b/cells/gds/MUX2X1.gds
Binary files differ
diff --git a/cells/gds/NAND2X1.gds b/cells/gds/NAND2X1.gds
new file mode 100644
index 0000000..8fdbb58
--- /dev/null
+++ b/cells/gds/NAND2X1.gds
Binary files differ
diff --git a/cells/gds/NAND3X1.gds b/cells/gds/NAND3X1.gds
new file mode 100644
index 0000000..907abca
--- /dev/null
+++ b/cells/gds/NAND3X1.gds
Binary files differ
diff --git a/cells/gds/NOR2X1.gds b/cells/gds/NOR2X1.gds
new file mode 100644
index 0000000..899eae3
--- /dev/null
+++ b/cells/gds/NOR2X1.gds
Binary files differ
diff --git a/cells/gds/OAI21X1.gds b/cells/gds/OAI21X1.gds
new file mode 100644
index 0000000..d338c37
--- /dev/null
+++ b/cells/gds/OAI21X1.gds
Binary files differ
diff --git a/cells/gds/OAI22X1.gds b/cells/gds/OAI22X1.gds
new file mode 100644
index 0000000..6206f02
--- /dev/null
+++ b/cells/gds/OAI22X1.gds
Binary files differ
diff --git a/cells/gds/OR2X1.gds b/cells/gds/OR2X1.gds
new file mode 100644
index 0000000..8b2fc8e
--- /dev/null
+++ b/cells/gds/OR2X1.gds
Binary files differ
diff --git a/cells/gds/XNOR2X1.gds b/cells/gds/XNOR2X1.gds
new file mode 100644
index 0000000..5a3415e
--- /dev/null
+++ b/cells/gds/XNOR2X1.gds
Binary files differ
diff --git a/cells/lef/AND2X1.lef b/cells/lef/AND2X1.lef
index 4678076..b878be6 100644
--- a/cells/lef/AND2X1.lef
+++ b/cells/lef/AND2X1.lef
@@ -38,17 +38,6 @@
RECT 4.660 0.400 4.950 0.690 ;
END
END Y
- PIN A
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 1.300 1.750 1.590 2.040 ;
- RECT 1.370 1.090 1.510 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
- END
- END A
PIN B
DIRECTION INOUT ;
USE SIGNAL ;
@@ -60,6 +49,17 @@
RECT 2.740 0.800 3.030 1.090 ;
END
END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
END AND2X1
END LIBRARY
diff --git a/cells/lef/AND2X2.lef b/cells/lef/AND2X2.lef
index a6ad78b..22a9a42 100644
--- a/cells/lef/AND2X2.lef
+++ b/cells/lef/AND2X2.lef
@@ -38,17 +38,6 @@
RECT 4.660 0.400 4.950 0.690 ;
END
END Y
- PIN B
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 2.740 1.750 3.030 2.040 ;
- RECT 2.810 1.090 2.950 1.750 ;
- RECT 2.740 0.800 3.030 1.090 ;
- END
- END B
PIN A
DIRECTION INOUT ;
USE SIGNAL ;
@@ -60,6 +49,17 @@
RECT 1.300 0.800 1.590 1.090 ;
END
END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END B
END AND2X2
END LIBRARY
diff --git a/cells/lef/AOI21X1.lef b/cells/lef/AOI21X1.lef
index 746dd95..81f1e94 100644
--- a/cells/lef/AOI21X1.lef
+++ b/cells/lef/AOI21X1.lef
@@ -33,8 +33,8 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 4.660 2.150 4.950 2.440 ;
- RECT 4.730 0.690 4.870 2.150 ;
+ RECT 0.820 2.150 1.110 2.440 ;
+ RECT 0.890 0.690 1.030 2.150 ;
RECT 0.820 0.610 1.110 0.690 ;
RECT 4.660 0.610 4.950 0.690 ;
RECT 0.820 0.470 4.950 0.610 ;
@@ -48,9 +48,9 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.300 1.750 1.590 2.040 ;
- RECT 1.370 1.090 1.510 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
END
END B
PIN A
@@ -70,9 +70,9 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 4.180 1.750 4.470 2.040 ;
- RECT 4.250 1.090 4.390 1.750 ;
- RECT 4.180 0.800 4.470 1.090 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
END
END C
END AOI21X1
diff --git a/cells/lef/AOI22X1.lef b/cells/lef/AOI22X1.lef
index dffb0de..87f7a69 100644
--- a/cells/lef/AOI22X1.lef
+++ b/cells/lef/AOI22X1.lef
@@ -33,9 +33,9 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.780 2.150 2.310 2.440 ;
+ RECT 4.660 2.150 4.950 2.440 ;
RECT 0.820 0.610 1.110 0.690 ;
- RECT 2.090 0.610 2.230 2.150 ;
+ RECT 4.730 0.610 4.870 2.150 ;
RECT 6.100 0.610 6.390 0.690 ;
RECT 0.820 0.470 6.390 0.610 ;
RECT 0.820 0.400 1.110 0.470 ;
@@ -48,12 +48,12 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 5.620 1.750 5.910 2.040 ;
- RECT 5.690 1.090 5.830 1.750 ;
- RECT 5.620 0.800 5.910 1.090 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
END
END B
- PIN C
+ PIN A
DIRECTION INOUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
@@ -63,8 +63,8 @@
RECT 2.810 1.090 2.950 1.750 ;
RECT 2.740 0.800 3.030 1.090 ;
END
- END C
- PIN A
+ END A
+ PIN C
DIRECTION INOUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
@@ -74,16 +74,16 @@
RECT 4.250 1.090 4.390 1.750 ;
RECT 4.180 0.800 4.470 1.090 ;
END
- END A
+ END C
PIN D
DIRECTION INOUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.300 1.750 1.590 2.040 ;
- RECT 1.370 1.090 1.510 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
+ RECT 5.620 1.750 5.910 2.040 ;
+ RECT 5.690 1.090 5.830 1.750 ;
+ RECT 5.620 0.800 5.910 1.090 ;
END
END D
END AOI22X1
diff --git a/cells/lef/BUFX2.lef b/cells/lef/BUFX2.lef
index 9b8ac6c..a021e28 100644
--- a/cells/lef/BUFX2.lef
+++ b/cells/lef/BUFX2.lef
@@ -44,6 +44,8 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
+ RECT 1.300 1.340 1.590 1.630 ;
+ RECT 1.370 1.090 1.510 1.340 ;
RECT 1.300 0.800 1.590 1.090 ;
END
END A
diff --git a/cells/lef/CLKBUF1.lef b/cells/lef/CLKBUF1.lef
deleted file mode 100644
index e54e104..0000000
--- a/cells/lef/CLKBUF1.lef
+++ /dev/null
@@ -1,63 +0,0 @@
-VERSION 5.7 ;
- NOWIREEXTENSIONATPIN ON ;
- DIVIDERCHAR "/" ;
- BUSBITCHARS "[]" ;
-MACRO CLKBUF1
- CLASS CORE ;
- FOREIGN CLKBUF1 ;
- ORIGIN 0.000 0.000 ;
- SIZE 12.960 BY 3.330 ;
- SYMMETRY X Y R90 ;
- SITE unit ;
- PIN vdd
- DIRECTION INOUT ;
- USE POWER ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 3.090 12.960 3.570 ;
- END
- END vdd
- PIN gnd
- DIRECTION INOUT ;
- USE GROUND ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 12.960 0.240 ;
- END
- END gnd
- PIN Y
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 10.660 2.370 11.190 2.440 ;
- RECT 10.660 2.230 12.070 2.370 ;
- RECT 10.660 2.150 11.190 2.230 ;
- RECT 11.930 0.750 12.070 2.230 ;
- RECT 10.900 0.610 11.190 0.690 ;
- RECT 11.690 0.610 12.070 0.750 ;
- RECT 10.900 0.470 11.830 0.610 ;
- RECT 10.900 0.400 11.190 0.470 ;
- END
- END Y
- PIN A
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 1.370 2.630 2.950 2.770 ;
- RECT 1.370 2.040 1.510 2.630 ;
- RECT 2.810 2.040 2.950 2.630 ;
- RECT 1.300 1.750 1.590 2.040 ;
- RECT 2.740 1.750 3.030 2.040 ;
- RECT 1.370 1.090 1.510 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
- END
- END A
-END CLKBUF1
-END LIBRARY
-
diff --git a/cells/lef/HAX1.lef b/cells/lef/HAX1.lef
index a1398a9..04f55a2 100644
--- a/cells/lef/HAX1.lef
+++ b/cells/lef/HAX1.lef
@@ -44,30 +44,11 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.780 2.370 2.070 2.440 ;
- RECT 0.890 2.230 2.070 2.370 ;
- RECT 0.890 0.610 1.030 2.230 ;
- RECT 1.780 2.150 2.070 2.230 ;
- RECT 1.780 0.610 2.070 0.690 ;
- RECT 0.890 0.470 2.070 0.610 ;
- RECT 1.780 0.400 2.070 0.470 ;
+ RECT 0.580 2.150 0.870 2.440 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
END
END YC
- PIN B
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 4.180 1.750 4.470 2.040 ;
- RECT 4.250 1.090 4.390 1.750 ;
- RECT 4.180 0.800 4.470 1.090 ;
- RECT 4.250 0.610 4.390 0.800 ;
- RECT 8.980 0.610 9.270 0.820 ;
- RECT 4.250 0.530 9.270 0.610 ;
- RECT 4.250 0.470 9.190 0.530 ;
- END
- END B
PIN A
DIRECTION INOUT ;
USE SIGNAL ;
@@ -75,15 +56,27 @@
PORT
LAYER met1 ;
RECT 5.620 1.750 5.910 2.040 ;
- RECT 11.380 1.750 11.670 2.040 ;
- RECT 5.690 1.150 5.830 1.750 ;
- RECT 11.450 1.150 11.590 1.750 ;
- RECT 5.690 1.090 11.590 1.150 ;
- RECT 5.620 1.010 11.670 1.090 ;
- RECT 5.620 0.800 5.910 1.010 ;
- RECT 11.380 0.800 11.670 1.010 ;
+ RECT 5.690 1.090 5.830 1.750 ;
+ RECT 5.620 0.800 5.910 1.090 ;
END
END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 9.940 1.750 10.230 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 10.010 1.090 10.150 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ RECT 9.940 0.800 10.230 1.090 ;
+ RECT 4.250 0.610 4.390 0.800 ;
+ RECT 10.010 0.610 10.150 0.800 ;
+ RECT 4.250 0.470 10.150 0.610 ;
+ END
+ END B
END HAX1
END LIBRARY
diff --git a/cells/lef/INVX1.lef b/cells/lef/INVX1.lef
index adccadb..0a4bdb9 100644
--- a/cells/lef/INVX1.lef
+++ b/cells/lef/INVX1.lef
@@ -33,9 +33,9 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.780 2.150 2.070 2.440 ;
- RECT 1.850 0.690 1.990 2.150 ;
- RECT 1.780 0.400 2.070 0.690 ;
+ RECT 0.580 2.150 0.870 2.440 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
END
END Y
PIN A
diff --git a/cells/lef/INVX4.lef b/cells/lef/INVX4.lef
index fa46143..f522aad 100644
--- a/cells/lef/INVX4.lef
+++ b/cells/lef/INVX4.lef
@@ -50,15 +50,15 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.300 1.960 1.590 2.040 ;
- RECT 2.740 1.960 3.030 2.040 ;
- RECT 1.300 1.820 3.030 1.960 ;
- RECT 1.300 1.750 1.590 1.820 ;
- RECT 2.740 1.750 3.030 1.820 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 2.740 1.750 3.030 2.040 ;
RECT 1.370 1.090 1.510 1.750 ;
RECT 2.810 1.090 2.950 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
- RECT 2.740 0.800 3.030 1.090 ;
+ RECT 1.300 1.020 1.590 1.090 ;
+ RECT 2.740 1.020 3.030 1.090 ;
+ RECT 1.300 0.880 3.030 1.020 ;
+ RECT 1.300 0.800 1.590 0.880 ;
+ RECT 2.740 0.800 3.030 0.880 ;
END
END A
END INVX4
diff --git a/cells/lef/INVX8.lef b/cells/lef/INVX8.lef
index 9985013..2fca274 100644
--- a/cells/lef/INVX8.lef
+++ b/cells/lef/INVX8.lef
@@ -33,23 +33,21 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 0.820 2.370 1.110 2.440 ;
+ RECT 0.580 2.370 0.870 2.440 ;
RECT 3.220 2.370 3.510 2.440 ;
- RECT 3.700 2.370 3.990 2.440 ;
- RECT 6.100 2.370 6.390 2.440 ;
- RECT 0.820 2.230 6.390 2.370 ;
- RECT 0.820 2.150 1.110 2.230 ;
+ RECT 0.580 2.230 3.510 2.370 ;
+ RECT 0.580 2.150 0.870 2.230 ;
RECT 3.220 2.150 3.510 2.230 ;
- RECT 3.700 2.150 3.990 2.230 ;
- RECT 6.100 2.150 6.390 2.230 ;
- RECT 0.890 0.690 1.030 2.150 ;
+ RECT 6.100 2.150 6.390 2.440 ;
+ RECT 0.650 0.690 0.790 2.150 ;
RECT 6.170 0.690 6.310 2.150 ;
- RECT 0.820 0.610 1.110 0.690 ;
- RECT 3.220 0.610 3.750 0.690 ;
- RECT 0.820 0.470 3.750 0.610 ;
- RECT 0.820 0.400 1.110 0.470 ;
- RECT 3.220 0.400 3.750 0.470 ;
- RECT 6.100 0.400 6.390 0.690 ;
+ RECT 0.580 0.610 0.870 0.690 ;
+ RECT 3.220 0.610 3.510 0.690 ;
+ RECT 6.100 0.610 6.390 0.690 ;
+ RECT 0.580 0.470 6.390 0.610 ;
+ RECT 0.580 0.400 0.870 0.470 ;
+ RECT 3.220 0.400 3.510 0.470 ;
+ RECT 6.100 0.400 6.390 0.470 ;
END
END Y
PIN A
@@ -58,23 +56,23 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 1.300 1.750 1.590 2.040 ;
- RECT 2.740 1.750 3.030 2.040 ;
- RECT 4.180 1.750 4.470 2.040 ;
- RECT 5.620 1.750 5.910 2.040 ;
+ RECT 1.300 1.960 1.590 2.040 ;
+ RECT 2.740 1.960 3.030 2.040 ;
+ RECT 4.180 1.960 4.470 2.040 ;
+ RECT 5.620 1.960 5.910 2.040 ;
+ RECT 1.300 1.820 5.910 1.960 ;
+ RECT 1.300 1.750 1.590 1.820 ;
+ RECT 2.740 1.750 3.030 1.820 ;
+ RECT 4.180 1.750 4.470 1.820 ;
+ RECT 5.620 1.750 5.910 1.820 ;
RECT 1.370 1.090 1.510 1.750 ;
RECT 2.810 1.090 2.950 1.750 ;
RECT 4.250 1.090 4.390 1.750 ;
RECT 5.690 1.090 5.830 1.750 ;
- RECT 1.300 1.020 1.590 1.090 ;
- RECT 2.740 1.020 3.030 1.090 ;
- RECT 4.180 1.020 4.470 1.090 ;
- RECT 5.620 1.020 5.910 1.090 ;
- RECT 1.300 0.880 5.910 1.020 ;
- RECT 1.300 0.800 1.590 0.880 ;
- RECT 2.740 0.800 3.030 0.880 ;
- RECT 4.180 0.800 4.470 0.880 ;
- RECT 5.620 0.800 5.910 0.880 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ RECT 5.620 0.800 5.910 1.090 ;
END
END A
END INVX8
diff --git a/cells/lef/LATCH.lef b/cells/lef/LATCH.lef
deleted file mode 100644
index 09c6256..0000000
--- a/cells/lef/LATCH.lef
+++ /dev/null
@@ -1,69 +0,0 @@
-VERSION 5.7 ;
- NOWIREEXTENSIONATPIN ON ;
- DIVIDERCHAR "/" ;
- BUSBITCHARS "[]" ;
-MACRO LATCH
- CLASS CORE ;
- FOREIGN LATCH ;
- ORIGIN 0.000 0.000 ;
- SIZE 10.080 BY 3.330 ;
- SYMMETRY X Y R90 ;
- SITE unit ;
- PIN vdd
- DIRECTION INOUT ;
- USE POWER ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 3.090 10.080 3.570 ;
- END
- END vdd
- PIN gnd
- DIRECTION INOUT ;
- USE GROUND ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 10.080 0.240 ;
- END
- END gnd
- PIN Q
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 8.980 2.370 9.270 2.440 ;
- RECT 7.130 2.230 9.270 2.370 ;
- RECT 7.130 2.040 7.270 2.230 ;
- RECT 8.980 2.150 9.270 2.230 ;
- RECT 7.060 1.750 7.350 2.040 ;
- RECT 9.050 0.690 9.190 2.150 ;
- RECT 8.980 0.400 9.270 0.690 ;
- END
- END Q
- PIN D
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 2.740 1.210 3.030 1.500 ;
- END
- END D
- PIN CLK
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 1.300 1.020 1.590 1.090 ;
- RECT 4.180 1.020 4.470 1.090 ;
- RECT 1.300 0.880 4.470 1.020 ;
- RECT 1.300 0.800 1.590 0.880 ;
- RECT 4.180 0.800 4.470 0.880 ;
- END
- END CLK
-END LATCH
-END LIBRARY
-
diff --git a/cells/lef/LOFTY.lef b/cells/lef/LOFTY.lef
deleted file mode 100644
index 6fe954b..0000000
--- a/cells/lef/LOFTY.lef
+++ /dev/null
@@ -1,167 +0,0 @@
-VERSION 5.7 ;
- NOWIREEXTENSIONATPIN ON ;
- DIVIDERCHAR "/" ;
- BUSBITCHARS "[]" ;
-MACRO LOFTY
- CLASS CORE ;
- FOREIGN LOFTY ;
- ORIGIN 0.000 0.000 ;
- SIZE 21.600 BY 3.330 ;
- SYMMETRY X Y R90 ;
- SITE unit ;
- PIN vdd
- DIRECTION INOUT ;
- USE POWER ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 3.090 21.600 3.570 ;
- END
- END vdd
- PIN gnd
- DIRECTION INOUT ;
- USE GROUND ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.000 -0.240 21.600 0.240 ;
- END
- END gnd
- PIN Q
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 2.020 2.290 2.550 2.580 ;
- RECT 2.090 0.690 2.230 2.290 ;
- RECT 2.020 0.400 2.310 0.690 ;
- END
- END Q
- PIN ASEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 5.620 1.750 5.910 2.040 ;
- RECT 5.690 1.090 5.830 1.750 ;
- RECT 5.620 0.800 5.910 1.090 ;
- END
- END ASEL_P
- PIN USEXOR_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 15.700 0.750 15.990 0.820 ;
- RECT 20.020 0.750 20.310 0.820 ;
- RECT 15.700 0.610 20.310 0.750 ;
- RECT 15.700 0.530 15.990 0.610 ;
- RECT 20.020 0.530 20.310 0.610 ;
- END
- END USEXOR_N
- PIN USEMUX_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 0.890 2.230 1.750 2.370 ;
- RECT 0.890 0.690 1.030 2.230 ;
- RECT 1.540 2.170 1.750 2.230 ;
- RECT 1.540 2.040 1.830 2.170 ;
- RECT 1.300 1.880 1.830 2.040 ;
- RECT 1.300 1.750 1.590 1.880 ;
- RECT 1.370 1.090 1.510 1.750 ;
- RECT 1.300 0.800 1.590 1.090 ;
- RECT 0.820 0.400 1.110 0.690 ;
- END
- END USEMUX_N
- PIN USEXOR_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 17.140 1.750 17.430 2.040 ;
- END
- PORT
- LAYER met1 ;
- RECT 8.500 1.750 8.790 2.040 ;
- END
- END USEXOR_P
- PIN ASEL_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 7.060 1.340 7.350 1.630 ;
- RECT 7.130 1.090 7.270 1.340 ;
- RECT 7.060 0.800 7.350 1.090 ;
- END
- END ASEL_N
- PIN BSEL_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 18.580 1.340 18.870 2.040 ;
- END
- END BSEL_N
- PIN BSEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 14.260 1.340 14.550 1.630 ;
- END
- END BSEL_P
- PIN MUXSEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 7.540 2.500 7.830 2.580 ;
- RECT 7.540 2.360 9.190 2.500 ;
- RECT 7.540 2.290 7.830 2.360 ;
- RECT 9.050 2.230 9.190 2.360 ;
- RECT 10.420 2.230 10.710 2.310 ;
- RECT 11.620 2.230 11.910 2.310 ;
- RECT 9.050 2.090 10.710 2.230 ;
- RECT 10.420 2.040 10.710 2.090 ;
- RECT 10.970 2.090 11.910 2.230 ;
- RECT 10.970 2.040 11.110 2.090 ;
- RECT 10.420 2.020 11.110 2.040 ;
- RECT 11.620 2.040 11.910 2.090 ;
- RECT 11.620 2.020 12.150 2.040 ;
- RECT 10.660 1.820 11.110 2.020 ;
- RECT 10.660 1.750 10.950 1.820 ;
- RECT 11.860 1.750 12.150 2.020 ;
- END
- END MUXSEL_P
- PIN USEMUX_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- LAYER met1 ;
- RECT 2.570 2.230 3.430 2.370 ;
- RECT 2.570 2.170 2.790 2.230 ;
- RECT 2.500 2.040 2.790 2.170 ;
- RECT 2.500 1.880 3.030 2.040 ;
- RECT 2.740 1.750 3.030 1.880 ;
- RECT 2.810 1.090 2.950 1.750 ;
- RECT 3.290 1.500 3.430 2.230 ;
- RECT 3.220 1.210 3.510 1.500 ;
- RECT 2.740 0.800 3.030 1.090 ;
- END
- END USEMUX_P
-END LOFTY
-END LIBRARY
-
diff --git a/cells/lef/MUX2X1.lef b/cells/lef/MUX2X1.lef
new file mode 100644
index 0000000..52dd939
--- /dev/null
+++ b/cells/lef/MUX2X1.lef
@@ -0,0 +1,82 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO MUX2X1
+ CLASS CORE ;
+ FOREIGN MUX2X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 8.640 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 8.640 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 8.640 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 5.140 2.150 5.430 2.440 ;
+ RECT 5.210 1.500 5.350 2.150 ;
+ RECT 5.140 1.210 5.430 1.500 ;
+ END
+ END Y
+ PIN S
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 5.620 1.960 5.910 2.040 ;
+ RECT 5.620 1.820 6.310 1.960 ;
+ RECT 5.620 1.750 5.910 1.820 ;
+ RECT 1.300 1.020 1.590 1.090 ;
+ RECT 4.180 1.020 4.470 1.090 ;
+ RECT 1.300 0.880 4.470 1.020 ;
+ RECT 1.300 0.800 1.590 0.880 ;
+ RECT 4.180 0.800 4.470 0.880 ;
+ RECT 4.250 0.610 4.390 0.800 ;
+ RECT 6.170 0.610 6.310 1.820 ;
+ RECT 4.250 0.470 6.310 0.610 ;
+ END
+ END S
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 7.060 1.750 7.350 2.040 ;
+ RECT 7.130 1.090 7.270 1.750 ;
+ RECT 7.060 0.800 7.350 1.090 ;
+ END
+ END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.210 3.030 1.500 ;
+ END
+ END A
+END MUX2X1
+END LIBRARY
+
diff --git a/cells/lef/NAND2X1.lef b/cells/lef/NAND2X1.lef
new file mode 100644
index 0000000..d61cb7f
--- /dev/null
+++ b/cells/lef/NAND2X1.lef
@@ -0,0 +1,69 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO NAND2X1
+ CLASS CORE ;
+ FOREIGN NAND2X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 4.320 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 4.320 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 4.320 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.370 0.870 2.440 ;
+ RECT 3.220 2.370 3.510 2.440 ;
+ RECT 0.580 2.230 3.510 2.370 ;
+ RECT 0.580 2.150 0.870 2.230 ;
+ RECT 3.220 2.150 3.510 2.230 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ END
+ END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END A
+END NAND2X1
+END LIBRARY
+
diff --git a/cells/lef/NAND3X1.lef b/cells/lef/NAND3X1.lef
new file mode 100644
index 0000000..f13ec6d
--- /dev/null
+++ b/cells/lef/NAND3X1.lef
@@ -0,0 +1,80 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO NAND3X1
+ CLASS CORE ;
+ FOREIGN NAND3X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.370 0.870 2.440 ;
+ RECT 3.220 2.370 3.510 2.440 ;
+ RECT 0.580 2.230 3.510 2.370 ;
+ RECT 0.580 2.150 0.870 2.230 ;
+ RECT 3.220 2.150 3.510 2.230 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ END
+ END A
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END C
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END B
+END NAND3X1
+END LIBRARY
+
diff --git a/cells/lef/NOR2X1.lef b/cells/lef/NOR2X1.lef
new file mode 100644
index 0000000..002dd31
--- /dev/null
+++ b/cells/lef/NOR2X1.lef
@@ -0,0 +1,69 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO NOR2X1
+ CLASS CORE ;
+ FOREIGN NOR2X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 4.320 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 4.320 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 4.320 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 3.220 2.150 3.510 2.440 ;
+ RECT 3.290 0.690 3.430 2.150 ;
+ RECT 0.820 0.610 1.110 0.690 ;
+ RECT 3.220 0.610 3.510 0.690 ;
+ RECT 0.820 0.470 3.510 0.610 ;
+ RECT 0.820 0.400 1.110 0.470 ;
+ RECT 3.220 0.400 3.510 0.470 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END B
+END NOR2X1
+END LIBRARY
+
diff --git a/cells/lef/OAI21X1.lef b/cells/lef/OAI21X1.lef
new file mode 100644
index 0000000..7eac8a0
--- /dev/null
+++ b/cells/lef/OAI21X1.lef
@@ -0,0 +1,80 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO OAI21X1
+ CLASS CORE ;
+ FOREIGN OAI21X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 5.760 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 5.760 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 5.760 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.580 2.370 0.870 2.440 ;
+ RECT 4.660 2.370 4.950 2.440 ;
+ RECT 0.580 2.230 4.950 2.370 ;
+ RECT 0.580 2.150 0.870 2.230 ;
+ RECT 4.660 2.150 4.950 2.230 ;
+ RECT 0.650 0.690 0.790 2.150 ;
+ RECT 0.580 0.400 0.870 0.690 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END A
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END C
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ END
+ END B
+END OAI21X1
+END LIBRARY
+
diff --git a/cells/lef/OAI22X1.lef b/cells/lef/OAI22X1.lef
new file mode 100644
index 0000000..5fe6083
--- /dev/null
+++ b/cells/lef/OAI22X1.lef
@@ -0,0 +1,91 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO OAI22X1
+ CLASS CORE ;
+ FOREIGN OAI22X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 7.200 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 7.200 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 7.200 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.820 2.370 1.110 2.440 ;
+ RECT 6.100 2.370 6.390 2.440 ;
+ RECT 0.820 2.230 6.390 2.370 ;
+ RECT 0.820 2.150 1.110 2.230 ;
+ RECT 5.210 1.090 5.350 2.230 ;
+ RECT 6.100 2.150 6.390 2.230 ;
+ RECT 5.140 0.800 5.430 1.090 ;
+ END
+ END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
+ END
+ END B
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 5.620 1.750 5.910 2.040 ;
+ RECT 5.690 1.090 5.830 1.750 ;
+ RECT 5.620 0.800 5.910 1.090 ;
+ END
+ END D
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.180 1.750 4.470 2.040 ;
+ RECT 4.250 1.090 4.390 1.750 ;
+ RECT 4.180 0.800 4.470 1.090 ;
+ END
+ END C
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ RECT 2.810 1.090 2.950 1.750 ;
+ RECT 2.740 0.800 3.030 1.090 ;
+ END
+ END A
+END OAI22X1
+END LIBRARY
+
diff --git a/cells/lef/BUFX4.lef b/cells/lef/OR2X1.lef
similarity index 66%
rename from cells/lef/BUFX4.lef
rename to cells/lef/OR2X1.lef
index 2c25e11..608d513 100644
--- a/cells/lef/BUFX4.lef
+++ b/cells/lef/OR2X1.lef
@@ -2,9 +2,9 @@
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
-MACRO BUFX4
+MACRO OR2X1
CLASS CORE ;
- FOREIGN BUFX4 ;
+ FOREIGN OR2X1 ;
ORIGIN 0.000 0.000 ;
SIZE 5.760 BY 3.330 ;
SYMMETRY X Y R90 ;
@@ -33,17 +33,20 @@
SHAPE ABUTMENT ;
PORT
LAYER met1 ;
- RECT 3.220 2.370 3.510 2.440 ;
- RECT 3.700 2.370 3.990 2.440 ;
- RECT 3.220 2.230 4.870 2.370 ;
- RECT 3.220 2.150 3.510 2.230 ;
- RECT 3.700 2.150 3.990 2.230 ;
- RECT 3.700 0.610 3.990 0.690 ;
- RECT 4.730 0.610 4.870 2.230 ;
- RECT 3.700 0.470 4.870 0.610 ;
- RECT 3.700 0.400 3.990 0.470 ;
+ RECT 4.660 2.150 4.950 2.440 ;
+ RECT 4.730 0.690 4.870 2.150 ;
+ RECT 4.660 0.400 4.950 0.690 ;
END
END Y
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 2.740 1.750 3.030 2.040 ;
+ END
+ END B
PIN A
DIRECTION INOUT ;
USE SIGNAL ;
@@ -51,8 +54,10 @@
PORT
LAYER met1 ;
RECT 1.300 1.750 1.590 2.040 ;
+ RECT 1.370 1.090 1.510 1.750 ;
+ RECT 1.300 0.800 1.590 1.090 ;
END
END A
-END BUFX4
+END OR2X1
END LIBRARY
diff --git a/cells/lef/XNOR2X1.lef b/cells/lef/XNOR2X1.lef
new file mode 100644
index 0000000..42c5e52
--- /dev/null
+++ b/cells/lef/XNOR2X1.lef
@@ -0,0 +1,75 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO XNOR2X1
+ CLASS CORE ;
+ FOREIGN XNOR2X1 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 10.080 BY 3.330 ;
+ SYMMETRY X Y R90 ;
+ SITE unit ;
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 3.090 10.080 3.570 ;
+ END
+ END vdd
+ PIN gnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000 -0.240 10.080 0.240 ;
+ END
+ END gnd
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 4.660 2.150 4.950 2.440 ;
+ RECT 4.730 2.040 4.870 2.150 ;
+ RECT 4.660 1.750 4.950 2.040 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 8.500 1.750 8.790 2.040 ;
+ RECT 8.570 1.090 8.710 1.750 ;
+ RECT 8.500 0.800 8.790 1.090 ;
+ RECT 3.700 0.610 3.990 0.690 ;
+ RECT 5.620 0.610 5.910 0.690 ;
+ RECT 8.570 0.610 8.710 0.800 ;
+ RECT 3.700 0.470 8.710 0.610 ;
+ RECT 3.700 0.400 3.990 0.470 ;
+ RECT 5.620 0.400 5.910 0.470 ;
+ END
+ END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met1 ;
+ RECT 1.300 1.960 1.590 2.040 ;
+ RECT 2.740 1.960 3.030 2.040 ;
+ RECT 1.300 1.820 3.030 1.960 ;
+ RECT 1.300 1.750 1.590 1.820 ;
+ RECT 2.740 1.750 3.030 1.820 ;
+ RECT 1.370 1.500 1.510 1.750 ;
+ RECT 1.300 1.210 1.590 1.500 ;
+ END
+ END B
+END XNOR2X1
+END LIBRARY
+
diff --git a/cells/lef/orig/AND2X1.lef b/cells/lef/orig/AND2X1.lef
index 388c359..f707f1e 100644
--- a/cells/lef/orig/AND2X1.lef
+++ b/cells/lef/orig/AND2X1.lef
@@ -39,19 +39,6 @@
END
END Y
- PIN A
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
- END
- END A
-
PIN B
DIRECTION INOUT ;
USE SIGNAL ;
@@ -65,5 +52,18 @@
END
END B
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
END AND2X1
diff --git a/cells/lef/orig/AND2X2.lef b/cells/lef/orig/AND2X2.lef
index 50a86fc..562e2c4 100644
--- a/cells/lef/orig/AND2X2.lef
+++ b/cells/lef/orig/AND2X2.lef
@@ -39,19 +39,6 @@
END
END Y
- PIN B
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
- RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
- RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
- END
- END B
-
PIN A
DIRECTION INOUT ;
USE SIGNAL ;
@@ -65,5 +52,18 @@
END
END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
END AND2X2
diff --git a/cells/lef/orig/AOI21X1.lef b/cells/lef/orig/AOI21X1.lef
index 48b73d2..829b58c 100644
--- a/cells/lef/orig/AOI21X1.lef
+++ b/cells/lef/orig/AOI21X1.lef
@@ -38,8 +38,8 @@
RECT 0.81500000 0.47000000 4.94500000 0.61000000 ;
RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
RECT 4.65500000 0.61000000 4.94500000 0.68500000 ;
- RECT 4.73000000 0.68500000 4.87000000 2.15000000 ;
- RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ RECT 0.89000000 0.68500000 1.03000000 2.15000000 ;
+ RECT 0.81500000 2.15000000 1.10500000 2.44000000 ;
END
END Y
@@ -50,9 +50,9 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
END
END B
@@ -76,9 +76,9 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
- RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
- RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
END
END C
diff --git a/cells/lef/orig/AOI22X1.lef b/cells/lef/orig/AOI22X1.lef
index a357ec9..d3e5da7 100644
--- a/cells/lef/orig/AOI22X1.lef
+++ b/cells/lef/orig/AOI22X1.lef
@@ -38,8 +38,8 @@
RECT 0.81500000 0.47000000 6.38500000 0.61000000 ;
RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
RECT 6.09500000 0.61000000 6.38500000 0.68500000 ;
- RECT 2.09000000 0.61000000 2.23000000 2.15000000 ;
- RECT 1.77500000 2.15000000 2.30500000 2.44000000 ;
+ RECT 4.73000000 0.61000000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
END
END Y
@@ -50,13 +50,13 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
- RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
- RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
END
END B
- PIN C
+ PIN A
DIRECTION INOUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
@@ -67,9 +67,9 @@
RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
END
- END C
+ END A
- PIN A
+ PIN C
DIRECTION INOUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
@@ -80,7 +80,7 @@
RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
END
- END A
+ END C
PIN D
DIRECTION INOUT ;
@@ -89,9 +89,9 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
+ RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
+ RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
END
END D
diff --git a/cells/lef/orig/BUFX2.lef b/cells/lef/orig/BUFX2.lef
index 14c37e0..1be3adb 100644
--- a/cells/lef/orig/BUFX2.lef
+++ b/cells/lef/orig/BUFX2.lef
@@ -47,6 +47,8 @@
CLASS CORE ;
LAYER metal2 ;
RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.34000000 ;
+ RECT 1.29500000 1.34000000 1.58500000 1.63000000 ;
END
END A
diff --git a/cells/lef/orig/BUFX4.lef b/cells/lef/orig/BUFX4.lef
deleted file mode 100644
index 2080399..0000000
--- a/cells/lef/orig/BUFX4.lef
+++ /dev/null
@@ -1,60 +0,0 @@
-MACRO BUFX4
- CLASS CORE ;
- FOREIGN BUFX4 0 0 ;
- ORIGIN 0 0 ;
- SYMMETRY X Y R90 ;
- SITE CORE ;
- PIN VDD
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
- END
- END VDD
-
- PIN GND
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
- END
- END GND
-
- PIN Y
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 3.69500000 0.39500000 3.98500000 0.47000000 ;
- RECT 3.69500000 0.47000000 4.87000000 0.61000000 ;
- RECT 3.69500000 0.61000000 3.98500000 0.68500000 ;
- RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
- RECT 3.69500000 2.15000000 3.98500000 2.22500000 ;
- RECT 4.73000000 0.61000000 4.87000000 2.22500000 ;
- RECT 3.21500000 2.22500000 4.87000000 2.36500000 ;
- RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
- RECT 3.69500000 2.36500000 3.98500000 2.44000000 ;
- END
- END Y
-
- PIN A
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
- END
- END A
-
-
-END BUFX4
diff --git a/cells/lef/orig/CLKBUF1.lef b/cells/lef/orig/CLKBUF1.lef
deleted file mode 100644
index 7e92c30..0000000
--- a/cells/lef/orig/CLKBUF1.lef
+++ /dev/null
@@ -1,66 +0,0 @@
-MACRO CLKBUF1
- CLASS CORE ;
- FOREIGN CLKBUF1 0 0 ;
- ORIGIN 0 0 ;
- SYMMETRY X Y R90 ;
- SITE CORE ;
- PIN VDD
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 3.09000000 12.96000000 3.57000000 ;
- END
- END VDD
-
- PIN GND
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 -0.24000000 12.96000000 0.24000000 ;
- END
- END GND
-
- PIN Y
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 10.89500000 0.39500000 11.18500000 0.47000000 ;
- RECT 10.89500000 0.47000000 11.83000000 0.60500000 ;
- RECT 10.89500000 0.60500000 12.07000000 0.61000000 ;
- RECT 10.89500000 0.61000000 11.18500000 0.68500000 ;
- RECT 11.69000000 0.61000000 12.07000000 0.74500000 ;
- RECT 10.65500000 2.15000000 11.18500000 2.22500000 ;
- RECT 11.93000000 0.74500000 12.07000000 2.22500000 ;
- RECT 10.65500000 2.22500000 12.07000000 2.36500000 ;
- RECT 10.65500000 2.36500000 11.18500000 2.44000000 ;
- END
- END Y
-
- PIN A
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
- RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
- RECT 1.37000000 2.03500000 1.51000000 2.63000000 ;
- RECT 2.81000000 2.03500000 2.95000000 2.63000000 ;
- RECT 1.37000000 2.63000000 2.95000000 2.77000000 ;
- END
- END A
-
-
-END CLKBUF1
diff --git a/cells/lef/orig/HAX1.lef b/cells/lef/orig/HAX1.lef
index 19db246..b2ba2c1 100644
--- a/cells/lef/orig/HAX1.lef
+++ b/cells/lef/orig/HAX1.lef
@@ -46,33 +46,12 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.77500000 0.39500000 2.06500000 0.47000000 ;
- RECT 0.89000000 0.47000000 2.06500000 0.61000000 ;
- RECT 1.77500000 0.61000000 2.06500000 0.68500000 ;
- RECT 0.89000000 0.61000000 1.03000000 2.22500000 ;
- RECT 1.77500000 2.15000000 2.06500000 2.22500000 ;
- RECT 0.89000000 2.22500000 2.06500000 2.36500000 ;
- RECT 1.77500000 2.36500000 2.06500000 2.44000000 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.44000000 ;
END
END YC
- PIN B
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 4.25000000 0.47000000 9.19000000 0.53000000 ;
- RECT 4.25000000 0.53000000 9.26500000 0.61000000 ;
- RECT 4.25000000 0.61000000 4.39000000 0.80000000 ;
- RECT 8.97500000 0.61000000 9.26500000 0.82000000 ;
- RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
- RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
- RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
- END
- END B
-
PIN A
DIRECTION INOUT ;
USE SIGNAL ;
@@ -80,16 +59,30 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 5.61500000 0.80000000 5.90500000 1.01000000 ;
- RECT 11.37500000 0.80000000 11.66500000 1.01000000 ;
- RECT 5.61500000 1.01000000 11.66500000 1.09000000 ;
- RECT 5.69000000 1.09000000 11.59000000 1.15000000 ;
- RECT 5.69000000 1.15000000 5.83000000 1.74500000 ;
- RECT 11.45000000 1.15000000 11.59000000 1.74500000 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
+ RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
- RECT 11.37500000 1.74500000 11.66500000 2.03500000 ;
END
END A
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.25000000 0.47000000 10.15000000 0.61000000 ;
+ RECT 4.25000000 0.61000000 4.39000000 0.80000000 ;
+ RECT 10.01000000 0.61000000 10.15000000 0.80000000 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 9.93500000 0.80000000 10.22500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 10.01000000 1.09000000 10.15000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ RECT 9.93500000 1.74500000 10.22500000 2.03500000 ;
+ END
+ END B
+
END HAX1
diff --git a/cells/lef/orig/INVX1.lef b/cells/lef/orig/INVX1.lef
index 1088e65..23e588f 100644
--- a/cells/lef/orig/INVX1.lef
+++ b/cells/lef/orig/INVX1.lef
@@ -33,9 +33,9 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.77500000 0.39500000 2.06500000 0.68500000 ;
- RECT 1.85000000 0.68500000 1.99000000 2.15000000 ;
- RECT 1.77500000 2.15000000 2.06500000 2.44000000 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.44000000 ;
END
END Y
diff --git a/cells/lef/orig/INVX4.lef b/cells/lef/orig/INVX4.lef
index d1077c8..726fd78 100644
--- a/cells/lef/orig/INVX4.lef
+++ b/cells/lef/orig/INVX4.lef
@@ -52,15 +52,15 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
+ RECT 2.73500000 0.80000000 3.02500000 0.87500000 ;
+ RECT 1.29500000 0.87500000 3.02500000 1.01500000 ;
+ RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
+ RECT 2.73500000 1.01500000 3.02500000 1.09000000 ;
RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 1.82000000 ;
- RECT 2.73500000 1.74500000 3.02500000 1.82000000 ;
- RECT 1.29500000 1.82000000 3.02500000 1.96000000 ;
- RECT 1.29500000 1.96000000 1.58500000 2.03500000 ;
- RECT 2.73500000 1.96000000 3.02500000 2.03500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
END
END A
diff --git a/cells/lef/orig/INVX8.lef b/cells/lef/orig/INVX8.lef
index 98c78c1..28aff50 100644
--- a/cells/lef/orig/INVX8.lef
+++ b/cells/lef/orig/INVX8.lef
@@ -33,23 +33,21 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 0.81500000 0.39500000 1.10500000 0.47000000 ;
- RECT 3.21500000 0.39500000 3.74500000 0.47000000 ;
- RECT 0.81500000 0.47000000 3.74500000 0.61000000 ;
- RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
- RECT 3.21500000 0.61000000 3.74500000 0.68500000 ;
- RECT 6.09500000 0.39500000 6.38500000 0.68500000 ;
- RECT 0.89000000 0.68500000 1.03000000 2.15000000 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.47000000 ;
+ RECT 3.21500000 0.39500000 3.50500000 0.47000000 ;
+ RECT 6.09500000 0.39500000 6.38500000 0.47000000 ;
+ RECT 0.57500000 0.47000000 6.38500000 0.61000000 ;
+ RECT 0.57500000 0.61000000 0.86500000 0.68500000 ;
+ RECT 3.21500000 0.61000000 3.50500000 0.68500000 ;
+ RECT 6.09500000 0.61000000 6.38500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
RECT 6.17000000 0.68500000 6.31000000 2.15000000 ;
- RECT 0.81500000 2.15000000 1.10500000 2.22500000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.22500000 ;
RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
- RECT 3.69500000 2.15000000 3.98500000 2.22500000 ;
- RECT 6.09500000 2.15000000 6.38500000 2.22500000 ;
- RECT 0.81500000 2.22500000 6.38500000 2.36500000 ;
- RECT 0.81500000 2.36500000 1.10500000 2.44000000 ;
+ RECT 0.57500000 2.22500000 3.50500000 2.36500000 ;
+ RECT 0.57500000 2.36500000 0.86500000 2.44000000 ;
RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
- RECT 3.69500000 2.36500000 3.98500000 2.44000000 ;
- RECT 6.09500000 2.36500000 6.38500000 2.44000000 ;
+ RECT 6.09500000 2.15000000 6.38500000 2.44000000 ;
END
END Y
@@ -60,23 +58,23 @@
PORT
CLASS CORE ;
LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
- RECT 2.73500000 0.80000000 3.02500000 0.87500000 ;
- RECT 4.17500000 0.80000000 4.46500000 0.87500000 ;
- RECT 5.61500000 0.80000000 5.90500000 0.87500000 ;
- RECT 1.29500000 0.87500000 5.90500000 1.01500000 ;
- RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
- RECT 2.73500000 1.01500000 3.02500000 1.09000000 ;
- RECT 4.17500000 1.01500000 4.46500000 1.09000000 ;
- RECT 5.61500000 1.01500000 5.90500000 1.09000000 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
- RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
- RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
- RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 1.82000000 ;
+ RECT 2.73500000 1.74500000 3.02500000 1.82000000 ;
+ RECT 4.17500000 1.74500000 4.46500000 1.82000000 ;
+ RECT 5.61500000 1.74500000 5.90500000 1.82000000 ;
+ RECT 1.29500000 1.82000000 5.90500000 1.96000000 ;
+ RECT 1.29500000 1.96000000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.96000000 3.02500000 2.03500000 ;
+ RECT 4.17500000 1.96000000 4.46500000 2.03500000 ;
+ RECT 5.61500000 1.96000000 5.90500000 2.03500000 ;
END
END A
diff --git a/cells/lef/orig/LATCH.lef b/cells/lef/orig/LATCH.lef
deleted file mode 100644
index a278e3d..0000000
--- a/cells/lef/orig/LATCH.lef
+++ /dev/null
@@ -1,73 +0,0 @@
-MACRO LATCH
- CLASS CORE ;
- FOREIGN LATCH 0 0 ;
- ORIGIN 0 0 ;
- SYMMETRY X Y R90 ;
- SITE CORE ;
- PIN VDD
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 3.09000000 10.08000000 3.57000000 ;
- END
- END VDD
-
- PIN GND
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 -0.24000000 10.08000000 0.24000000 ;
- END
- END GND
-
- PIN Q
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 8.97500000 0.39500000 9.26500000 0.68500000 ;
- RECT 7.05500000 1.74500000 7.34500000 2.03500000 ;
- RECT 9.05000000 0.68500000 9.19000000 2.15000000 ;
- RECT 7.13000000 2.03500000 7.27000000 2.22500000 ;
- RECT 8.97500000 2.15000000 9.26500000 2.22500000 ;
- RECT 7.13000000 2.22500000 9.26500000 2.36500000 ;
- RECT 8.97500000 2.36500000 9.26500000 2.44000000 ;
- END
- END Q
-
- PIN D
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 2.73500000 1.20500000 3.02500000 1.49500000 ;
- END
- END D
-
- PIN CLK
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
- RECT 4.17500000 0.80000000 4.46500000 0.87500000 ;
- RECT 1.29500000 0.87500000 4.46500000 1.01500000 ;
- RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
- RECT 4.17500000 1.01500000 4.46500000 1.09000000 ;
- END
- END CLK
-
-
-END LATCH
diff --git a/cells/lef/orig/LOFTY.lef b/cells/lef/orig/LOFTY.lef
deleted file mode 100644
index f66e02a..0000000
--- a/cells/lef/orig/LOFTY.lef
+++ /dev/null
@@ -1,209 +0,0 @@
-MACRO LOFTY
- CLASS CORE ;
- FOREIGN LOFTY 0 0 ;
- ORIGIN 0 0 ;
- SYMMETRY X Y R90 ;
- SITE CORE ;
- PIN VDD
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 3.09000000 21.60000000 3.57000000 ;
- END
- END VDD
-
- PIN GND
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.00000000 -0.24000000 21.60000000 0.24000000 ;
- END
- END GND
-
- PIN Q
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 2.01500000 0.39500000 2.30500000 0.68500000 ;
- RECT 2.09000000 0.68500000 2.23000000 2.28500000 ;
- RECT 2.01500000 2.28500000 2.54500000 2.57500000 ;
- END
- END Q
-
- PIN ASEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
- RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
- RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
- END
- END ASEL_P
-
- PIN USEXOR_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 15.69500000 0.53000000 15.98500000 0.60500000 ;
- RECT 20.01500000 0.53000000 20.30500000 0.60500000 ;
- RECT 15.69500000 0.60500000 20.30500000 0.74500000 ;
- RECT 15.69500000 0.74500000 15.98500000 0.82000000 ;
- RECT 20.01500000 0.74500000 20.30500000 0.82000000 ;
- END
- END USEXOR_N
-
- PIN USEMUX_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 0.81500000 0.39500000 1.10500000 0.68500000 ;
- RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
- RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
- RECT 1.29500000 1.74500000 1.58500000 1.88000000 ;
- RECT 1.29500000 1.88000000 1.82500000 2.03500000 ;
- RECT 1.53500000 2.03500000 1.82500000 2.17000000 ;
- RECT 0.89000000 0.68500000 1.03000000 2.22500000 ;
- RECT 1.53500000 2.17000000 1.75000000 2.22500000 ;
- RECT 0.89000000 2.22500000 1.75000000 2.36500000 ;
- END
- END USEMUX_N
-
- PIN USEXOR_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 8.49500000 1.74500000 8.78500000 2.03500000 ;
- LAYER metal2 ;
- RECT 17.13500000 1.74500000 17.42500000 2.03500000 ;
- END
- END USEXOR_P
-
- PIN ASEL_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 7.05500000 0.80000000 7.34500000 1.09000000 ;
- RECT 7.13000000 1.09000000 7.27000000 1.34000000 ;
- RECT 7.05500000 1.34000000 7.34500000 1.63000000 ;
- END
- END ASEL_N
-
- PIN BSEL_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 18.57500000 1.34000000 18.86500000 2.03500000 ;
- END
- END BSEL_N
-
- PIN BSEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 14.25500000 1.34000000 14.54500000 1.63000000 ;
- END
- END BSEL_P
-
- PIN MUXSEL_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 10.65500000 1.74500000 10.94500000 1.82000000 ;
- RECT 10.65500000 1.82000000 11.11000000 2.01500000 ;
- RECT 11.85500000 1.74500000 12.14500000 2.01500000 ;
- RECT 11.61500000 2.01500000 12.14500000 2.03500000 ;
- RECT 10.41500000 2.01500000 11.11000000 2.03500000 ;
- RECT 10.41500000 2.03500000 10.70500000 2.09000000 ;
- RECT 10.97000000 2.03500000 11.11000000 2.09000000 ;
- RECT 11.61500000 2.03500000 11.90500000 2.09000000 ;
- RECT 10.97000000 2.09000000 11.90500000 2.23000000 ;
- RECT 9.05000000 2.09000000 10.70500000 2.23000000 ;
- RECT 10.41500000 2.23000000 10.70500000 2.30500000 ;
- RECT 11.61500000 2.23000000 11.90500000 2.30500000 ;
- RECT 7.53500000 2.28500000 7.82500000 2.36000000 ;
- RECT 9.05000000 2.23000000 9.19000000 2.36000000 ;
- RECT 7.53500000 2.36000000 9.19000000 2.50000000 ;
- RECT 7.53500000 2.50000000 7.82500000 2.57500000 ;
- END
- END MUXSEL_P
-
- PIN USEMUX_P
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
- RECT 3.21500000 1.20500000 3.50500000 1.49500000 ;
- RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
- RECT 2.73500000 1.74500000 3.02500000 1.88000000 ;
- RECT 2.49500000 1.88000000 3.02500000 2.03500000 ;
- RECT 2.49500000 2.03500000 2.78500000 2.17000000 ;
- RECT 2.57000000 2.17000000 2.78500000 2.22500000 ;
- RECT 3.29000000 1.49500000 3.43000000 2.22500000 ;
- RECT 2.57000000 2.22500000 3.43000000 2.36500000 ;
- END
- END USEMUX_P
-
- PIN MUXSEL_N
- DIRECTION INOUT ;
- USE SIGNAL ;
- SHAPE ABUTMENT ;
- PORT
- CLASS CORE ;
- LAYER metal2 ;
- RECT 10.65500000 1.74500000 10.94500000 1.82000000 ;
- RECT 10.65500000 1.82000000 11.11000000 2.01500000 ;
- RECT 11.85500000 1.74500000 12.14500000 2.01500000 ;
- RECT 11.61500000 2.01500000 12.14500000 2.03500000 ;
- RECT 10.41500000 2.01500000 11.11000000 2.03500000 ;
- RECT 10.41500000 2.03500000 10.70500000 2.09000000 ;
- RECT 10.97000000 2.03500000 11.11000000 2.09000000 ;
- RECT 11.61500000 2.03500000 11.90500000 2.09000000 ;
- RECT 10.97000000 2.09000000 11.90500000 2.23000000 ;
- RECT 9.05000000 2.09000000 10.70500000 2.23000000 ;
- RECT 10.41500000 2.23000000 10.70500000 2.30500000 ;
- RECT 11.61500000 2.23000000 11.90500000 2.30500000 ;
- RECT 7.53500000 2.28500000 7.82500000 2.36000000 ;
- RECT 9.05000000 2.23000000 9.19000000 2.36000000 ;
- RECT 7.53500000 2.36000000 9.19000000 2.50000000 ;
- RECT 7.53500000 2.50000000 7.82500000 2.57500000 ;
- END
- END MUXSEL_N
-
-
-END LOFTY
diff --git a/cells/lef/orig/MUX2X1.lef b/cells/lef/orig/MUX2X1.lef
new file mode 100644
index 0000000..22989f0
--- /dev/null
+++ b/cells/lef/orig/MUX2X1.lef
@@ -0,0 +1,88 @@
+MACRO MUX2X1
+ CLASS CORE ;
+ FOREIGN MUX2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 8.64000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 8.64000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 5.13500000 1.20500000 5.42500000 1.49500000 ;
+ RECT 5.21000000 1.49500000 5.35000000 2.15000000 ;
+ RECT 5.13500000 2.15000000 5.42500000 2.44000000 ;
+ END
+ END Y
+
+ PIN S
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.25000000 0.47000000 6.31000000 0.61000000 ;
+ RECT 4.25000000 0.61000000 4.39000000 0.80000000 ;
+ RECT 1.29500000 0.80000000 1.58500000 0.87500000 ;
+ RECT 4.17500000 0.80000000 4.46500000 0.87500000 ;
+ RECT 1.29500000 0.87500000 4.46500000 1.01500000 ;
+ RECT 1.29500000 1.01500000 1.58500000 1.09000000 ;
+ RECT 4.17500000 1.01500000 4.46500000 1.09000000 ;
+ RECT 5.61500000 1.74500000 5.90500000 1.82000000 ;
+ RECT 6.17000000 0.61000000 6.31000000 1.82000000 ;
+ RECT 5.61500000 1.82000000 6.31000000 1.96000000 ;
+ RECT 5.61500000 1.96000000 5.90500000 2.03500000 ;
+ END
+ END S
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 7.05500000 0.80000000 7.34500000 1.09000000 ;
+ RECT 7.13000000 1.09000000 7.27000000 1.74500000 ;
+ RECT 7.05500000 1.74500000 7.34500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 1.20500000 3.02500000 1.49500000 ;
+ END
+ END A
+
+
+END MUX2X1
diff --git a/cells/lef/orig/NAND2X1.lef b/cells/lef/orig/NAND2X1.lef
new file mode 100644
index 0000000..b61443a
--- /dev/null
+++ b/cells/lef/orig/NAND2X1.lef
@@ -0,0 +1,73 @@
+MACRO NAND2X1
+ CLASS CORE ;
+ FOREIGN NAND2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 4.32000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 4.32000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.22500000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
+ RECT 0.57500000 2.22500000 3.50500000 2.36500000 ;
+ RECT 0.57500000 2.36500000 0.86500000 2.44000000 ;
+ RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END A
+
+
+END NAND2X1
diff --git a/cells/lef/orig/NAND3X1.lef b/cells/lef/orig/NAND3X1.lef
new file mode 100644
index 0000000..2d5d3f3
--- /dev/null
+++ b/cells/lef/orig/NAND3X1.lef
@@ -0,0 +1,86 @@
+MACRO NAND3X1
+ CLASS CORE ;
+ FOREIGN NAND3X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.22500000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.22500000 ;
+ RECT 0.57500000 2.22500000 3.50500000 2.36500000 ;
+ RECT 0.57500000 2.36500000 0.86500000 2.44000000 ;
+ RECT 3.21500000 2.36500000 3.50500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END A
+
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END C
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
+
+END NAND3X1
diff --git a/cells/lef/orig/NOR2X1.lef b/cells/lef/orig/NOR2X1.lef
new file mode 100644
index 0000000..436721c
--- /dev/null
+++ b/cells/lef/orig/NOR2X1.lef
@@ -0,0 +1,73 @@
+MACRO NOR2X1
+ CLASS CORE ;
+ FOREIGN NOR2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 4.32000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 4.32000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.81500000 0.39500000 1.10500000 0.47000000 ;
+ RECT 3.21500000 0.39500000 3.50500000 0.47000000 ;
+ RECT 0.81500000 0.47000000 3.50500000 0.61000000 ;
+ RECT 0.81500000 0.61000000 1.10500000 0.68500000 ;
+ RECT 3.21500000 0.61000000 3.50500000 0.68500000 ;
+ RECT 3.29000000 0.68500000 3.43000000 2.15000000 ;
+ RECT 3.21500000 2.15000000 3.50500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
+
+END NOR2X1
diff --git a/cells/lef/orig/OAI21X1.lef b/cells/lef/orig/OAI21X1.lef
new file mode 100644
index 0000000..c4be5e1
--- /dev/null
+++ b/cells/lef/orig/OAI21X1.lef
@@ -0,0 +1,86 @@
+MACRO OAI21X1
+ CLASS CORE ;
+ FOREIGN OAI21X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.57500000 0.39500000 0.86500000 0.68500000 ;
+ RECT 0.65000000 0.68500000 0.79000000 2.15000000 ;
+ RECT 0.57500000 2.15000000 0.86500000 2.22500000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.22500000 ;
+ RECT 0.57500000 2.22500000 4.94500000 2.36500000 ;
+ RECT 0.57500000 2.36500000 0.86500000 2.44000000 ;
+ RECT 4.65500000 2.36500000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END A
+
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END C
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END B
+
+
+END OAI21X1
diff --git a/cells/lef/orig/OAI22X1.lef b/cells/lef/orig/OAI22X1.lef
new file mode 100644
index 0000000..2d4e7bb
--- /dev/null
+++ b/cells/lef/orig/OAI22X1.lef
@@ -0,0 +1,99 @@
+MACRO OAI22X1
+ CLASS CORE ;
+ FOREIGN OAI22X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 7.20000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 7.20000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 5.13500000 0.80000000 5.42500000 1.09000000 ;
+ RECT 0.81500000 2.15000000 1.10500000 2.22500000 ;
+ RECT 5.21000000 1.09000000 5.35000000 2.22500000 ;
+ RECT 6.09500000 2.15000000 6.38500000 2.22500000 ;
+ RECT 0.81500000 2.22500000 6.38500000 2.36500000 ;
+ RECT 0.81500000 2.36500000 1.10500000 2.44000000 ;
+ RECT 6.09500000 2.36500000 6.38500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END B
+
+ PIN D
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 5.61500000 0.80000000 5.90500000 1.09000000 ;
+ RECT 5.69000000 1.09000000 5.83000000 1.74500000 ;
+ RECT 5.61500000 1.74500000 5.90500000 2.03500000 ;
+ END
+ END D
+
+ PIN C
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.17500000 0.80000000 4.46500000 1.09000000 ;
+ RECT 4.25000000 1.09000000 4.39000000 1.74500000 ;
+ RECT 4.17500000 1.74500000 4.46500000 2.03500000 ;
+ END
+ END C
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 0.80000000 3.02500000 1.09000000 ;
+ RECT 2.81000000 1.09000000 2.95000000 1.74500000 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END A
+
+
+END OAI22X1
diff --git a/cells/lef/orig/OR2X1.lef b/cells/lef/orig/OR2X1.lef
new file mode 100644
index 0000000..133efee
--- /dev/null
+++ b/cells/lef/orig/OR2X1.lef
@@ -0,0 +1,67 @@
+MACRO OR2X1
+ CLASS CORE ;
+ FOREIGN OR2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 5.76000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 5.76000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.65500000 0.39500000 4.94500000 0.68500000 ;
+ RECT 4.73000000 0.68500000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 2.73500000 1.74500000 3.02500000 2.03500000 ;
+ END
+ END B
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 0.80000000 1.58500000 1.09000000 ;
+ RECT 1.37000000 1.09000000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 2.03500000 ;
+ END
+ END A
+
+
+END OR2X1
diff --git a/cells/lef/orig/XNOR2X1.lef b/cells/lef/orig/XNOR2X1.lef
new file mode 100644
index 0000000..9e38b57
--- /dev/null
+++ b/cells/lef/orig/XNOR2X1.lef
@@ -0,0 +1,79 @@
+MACRO XNOR2X1
+ CLASS CORE ;
+ FOREIGN XNOR2X1 0 0 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ SITE CORE ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 3.09000000 10.08000000 3.57000000 ;
+ END
+ END VDD
+
+ PIN GND
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 0.00000000 -0.24000000 10.08000000 0.24000000 ;
+ END
+ END GND
+
+ PIN Y
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 4.65500000 1.74500000 4.94500000 2.03500000 ;
+ RECT 4.73000000 2.03500000 4.87000000 2.15000000 ;
+ RECT 4.65500000 2.15000000 4.94500000 2.44000000 ;
+ END
+ END Y
+
+ PIN A
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 3.69500000 0.39500000 3.98500000 0.47000000 ;
+ RECT 5.61500000 0.39500000 5.90500000 0.47000000 ;
+ RECT 3.69500000 0.47000000 8.71000000 0.61000000 ;
+ RECT 3.69500000 0.61000000 3.98500000 0.68500000 ;
+ RECT 5.61500000 0.61000000 5.90500000 0.68500000 ;
+ RECT 8.57000000 0.61000000 8.71000000 0.80000000 ;
+ RECT 8.49500000 0.80000000 8.78500000 1.09000000 ;
+ RECT 8.57000000 1.09000000 8.71000000 1.74500000 ;
+ RECT 8.49500000 1.74500000 8.78500000 2.03500000 ;
+ END
+ END A
+
+ PIN B
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ SHAPE ABUTMENT ;
+ PORT
+ CLASS CORE ;
+ LAYER metal2 ;
+ RECT 1.29500000 1.20500000 1.58500000 1.49500000 ;
+ RECT 1.37000000 1.49500000 1.51000000 1.74500000 ;
+ RECT 1.29500000 1.74500000 1.58500000 1.82000000 ;
+ RECT 2.73500000 1.74500000 3.02500000 1.82000000 ;
+ RECT 1.29500000 1.82000000 3.02500000 1.96000000 ;
+ RECT 1.29500000 1.96000000 1.58500000 2.03500000 ;
+ RECT 2.73500000 1.96000000 3.02500000 2.03500000 ;
+ END
+ END B
+
+
+END XNOR2X1
diff --git a/cells/lib/BUFX4.lib b/cells/lib/BUFX4.lib
deleted file mode 100644
index 89862e0..0000000
--- a/cells/lib/BUFX4.lib
+++ /dev/null
@@ -1,259 +0,0 @@
-library (ls05_stdcells) {
- capacitive_load_unit (1.0, pf);
- current_unit: "1uA";
- default_operating_conditions: typical;
- delay_model: table_lookup;
- in_place_swap_mode: match_footprint;
- input_threshold_pct_fall: 50.0;
- input_threshold_pct_rise: 50.0;
- leakage_power_unit: "1nW";
- nom_process: 1.0;
- nom_temperature: 25.0;
- nom_voltage: 5.0;
- output_threshold_pct_fall: 50.0;
- output_threshold_pct_rise: 50.0;
- pulling_resistance_unit: "1kohm";
- slew_lower_threshold_pct_fall: 20.0;
- slew_lower_threshold_pct_rise: 20.0;
- slew_upper_threshold_pct_fall: 80.0;
- slew_upper_threshold_pct_rise: 80.0;
- time_unit: "1ns";
- voltage_unit: "1V";
- operating_conditions (typical) {
- process: 1.0;
- temperature: 25.0;
- voltage: 5.0;
- }
- lu_table_template (delay_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- power_lut_template (energy_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- lu_table_template (hold_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (hold_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- power_lut_template (passive_energy_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_transition_time;
- }
- power_lut_template (passive_energy_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_transition_time;
- }
- lu_table_template (recovery_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (recovery_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (removal_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- cell (BUFX4) {
- area: 219456.0;
- cell_leakage_power: 0.1173;
- pin (A) {
- capacitance: 0.007514333929026605;
- direction: input;
- fall_capacitance: 0.008837539393571521;
- rise_capacitance: 0.006191128464481691;
- }
- pin (Y) {
- direction: output;
- function: "(A)";
- timing () {
- related_pin: "A";
- timing_sense: positive_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "-0.003332, 0.021337, 0.029037, 0.036252, 0.091507", \
- "0.026238, 0.039009, 0.047800, 0.055261, 0.134399", \
- "0.045194, 0.053749, 0.061884, 0.072100, 0.164091", \
- "0.086136, 0.087693, 0.092336, 0.105084, 0.211761", \
- "0.435031, 0.421027, 0.413172, 0.405020, 0.529945"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.019917, 0.023446, 0.028145, 0.031913, 0.009760", \
- "0.039765, 0.042820, 0.048616, 0.054117, 0.051193", \
- "0.059723, 0.061229, 0.065465, 0.075300, 0.085196", \
- "0.102990, 0.102455, 0.103727, 0.112733, 0.147808", \
- "0.457776, 0.455343, 0.452374, 0.448140, 0.530074"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.022555, 0.060932, 0.100046, 0.120529, 0.838717", \
- "0.048081, 0.083216, 0.116400, 0.133925, 0.836505", \
- "0.079669, 0.106770, 0.139757, 0.152647, 0.829964", \
- "0.149638, 0.158594, 0.172524, 0.201707, 0.830249", \
- "0.712717, 0.712642, 0.712987, 0.713842, 1.090806"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.022354, 0.035611, 0.057295, 0.109654, 0.837625", \
- "0.053183, 0.062016, 0.081775, 0.123534, 0.838808", \
- "0.097215, 0.099197, 0.113296, 0.150874, 0.837898", \
- "0.178609, 0.180128, 0.185695, 0.216266, 0.850702", \
- "0.864323, 0.864161, 0.864217, 0.865032, 1.209812"
- );
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/cells/lib/CLKBUF1.lib b/cells/lib/CLKBUF1.lib
deleted file mode 100644
index 52c66ce..0000000
--- a/cells/lib/CLKBUF1.lib
+++ /dev/null
@@ -1,259 +0,0 @@
-library (ls05_stdcells) {
- capacitive_load_unit (1.0, pf);
- current_unit: "1uA";
- default_operating_conditions: typical;
- delay_model: table_lookup;
- in_place_swap_mode: match_footprint;
- input_threshold_pct_fall: 50.0;
- input_threshold_pct_rise: 50.0;
- leakage_power_unit: "1nW";
- nom_process: 1.0;
- nom_temperature: 25.0;
- nom_voltage: 5.0;
- output_threshold_pct_fall: 50.0;
- output_threshold_pct_rise: 50.0;
- pulling_resistance_unit: "1kohm";
- slew_lower_threshold_pct_fall: 20.0;
- slew_lower_threshold_pct_rise: 20.0;
- slew_upper_threshold_pct_fall: 80.0;
- slew_upper_threshold_pct_rise: 80.0;
- time_unit: "1ns";
- voltage_unit: "1V";
- operating_conditions (typical) {
- process: 1.0;
- temperature: 25.0;
- voltage: 5.0;
- }
- lu_table_template (delay_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- power_lut_template (energy_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- lu_table_template (hold_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (hold_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- power_lut_template (passive_energy_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_transition_time;
- }
- power_lut_template (passive_energy_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_transition_time;
- }
- lu_table_template (recovery_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (recovery_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (removal_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- cell (CLKBUF1) {
- area: 493776.0;
- cell_leakage_power: 0.1173;
- pin (A) {
- capacitance: 0.013425801072809228;
- direction: input;
- fall_capacitance: 0.014473574566389579;
- rise_capacitance: 0.01237802757922888;
- }
- pin (Y) {
- direction: output;
- function: "(A)";
- timing () {
- related_pin: "A";
- timing_sense: positive_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "-0.003460, 0.039164, 0.046896, 0.050449, 0.120253", \
- "0.039198, 0.055206, 0.064662, 0.077056, 0.156283", \
- "0.055272, 0.068058, 0.076746, 0.094215, 0.181108", \
- "0.092867, 0.100270, 0.106720, 0.122551, 0.218136", \
- "0.435146, 0.428670, 0.424456, 0.422460, 0.537852"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.032184, 0.039672, 0.044147, 0.047413, 0.021510", \
- "0.050419, 0.056995, 0.062609, 0.075229, 0.055087", \
- "0.068541, 0.073865, 0.078930, 0.093698, 0.083981", \
- "0.108988, 0.112336, 0.115801, 0.127951, 0.133757", \
- "0.460979, 0.460184, 0.458832, 0.460220, 0.520187"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.038133, 0.073651, 0.108037, 0.109667, 0.728970", \
- "0.059918, 0.097402, 0.131852, 0.121421, 0.731671", \
- "0.090369, 0.121037, 0.155826, 0.147609, 0.732523", \
- "0.151770, 0.167602, 0.178904, 0.194858, 0.737833", \
- "0.712055, 0.712016, 0.712316, 0.712828, 0.976108"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.041321, 0.069345, 0.055441, 0.094793, 0.734070", \
- "0.070699, 0.097312, 0.082033, 0.118518, 0.740459", \
- "0.104261, 0.111495, 0.116574, 0.147708, 0.740016", \
- "0.178901, 0.182855, 0.190726, 0.213201, 0.744041", \
- "0.862866, 0.864337, 0.864426, 0.865268, 1.090174"
- );
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/cells/lib/MUX2X1.lib b/cells/lib/MUX2X1.lib
index 8e6ba75..3baab38 100644
--- a/cells/lib/MUX2X1.lib
+++ b/cells/lib/MUX2X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (MUX2X1) {
- area: 1.0;
+ area: 329184.0;
cell_leakage_power: 0.1173;
pin (S) {
capacitance: 0.009256673995156848;
diff --git a/cells/lib/NAND2X1.lib b/cells/lib/NAND2X1.lib
index 19e69a6..3a083f6 100644
--- a/cells/lib/NAND2X1.lib
+++ b/cells/lib/NAND2X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (NAND2X1) {
- area: 1.0;
+ area: 164592.0;
cell_leakage_power: 0.1173;
pin (B) {
capacitance: 0.00495623189256475;
diff --git a/cells/lib/NAND3X1.lib b/cells/lib/NAND3X1.lib
index 8ae0b0a..9c3f8e6 100644
--- a/cells/lib/NAND3X1.lib
+++ b/cells/lib/NAND3X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (NAND3X1) {
- area: 1.0;
+ area: 219456.0;
cell_leakage_power: 0.1173;
pin (C) {
capacitance: 0.0049475602037443766;
diff --git a/cells/lib/NOR2X1.lib b/cells/lib/NOR2X1.lib
index 9d13318..09cb458 100644
--- a/cells/lib/NOR2X1.lib
+++ b/cells/lib/NOR2X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (NOR2X1) {
- area: 1.0;
+ area: 164592.0;
cell_leakage_power: 0.1173;
pin (B) {
capacitance: 0.006303448359239213;
diff --git a/cells/lib/NOR3X1.lib b/cells/lib/NOR3X1.lib
deleted file mode 100644
index 753b07e..0000000
--- a/cells/lib/NOR3X1.lib
+++ /dev/null
@@ -1,399 +0,0 @@
-library (ls05_stdcells) {
- capacitive_load_unit (1.0, pf);
- current_unit: "1uA";
- default_operating_conditions: typical;
- delay_model: table_lookup;
- in_place_swap_mode: match_footprint;
- input_threshold_pct_fall: 50.0;
- input_threshold_pct_rise: 50.0;
- leakage_power_unit: "1nW";
- nom_process: 1.0;
- nom_temperature: 25.0;
- nom_voltage: 5.0;
- output_threshold_pct_fall: 50.0;
- output_threshold_pct_rise: 50.0;
- pulling_resistance_unit: "1kohm";
- slew_lower_threshold_pct_fall: 20.0;
- slew_lower_threshold_pct_rise: 20.0;
- slew_upper_threshold_pct_fall: 80.0;
- slew_upper_threshold_pct_rise: 80.0;
- time_unit: "1ns";
- voltage_unit: "1V";
- operating_conditions (typical) {
- process: 1.0;
- temperature: 25.0;
- voltage: 5.0;
- }
- lu_table_template (delay_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- power_lut_template (energy_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- lu_table_template (hold_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (hold_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- power_lut_template (passive_energy_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_transition_time;
- }
- power_lut_template (passive_energy_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_transition_time;
- }
- lu_table_template (recovery_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (recovery_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (removal_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- cell (NOR3X1) {
- area: 1.0;
- cell_leakage_power: 0.1173;
- pin (C) {
- capacitance: 0.008851268942232223;
- direction: input;
- fall_capacitance: 0.007192740516108539;
- rise_capacitance: 0.01050979736835591;
- }
- pin (B) {
- capacitance: 0.008467308012434688;
- direction: input;
- fall_capacitance: 0.006491035832102533;
- rise_capacitance: 0.010443580192766843;
- }
- pin (A) {
- capacitance: 0.011319336983488502;
- direction: input;
- fall_capacitance: 0.012153813915844755;
- rise_capacitance: 0.010484860051132246;
- }
- pin (Y) {
- direction: output;
- function: "(!A & !B & !C)";
- timing () {
- related_pin: "C";
- timing_sense: negative_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.019861, 0.013951, 0.010393, 0.010614, -0.095224", \
- "0.073806, 0.065433, 0.065471, 0.070741, 0.031362", \
- "0.126961, 0.116836, 0.114849, 0.117995, 0.121232", \
- "0.229374, 0.218604, 0.214181, 0.213278, 0.265478", \
- "1.052068, 1.040930, 1.032640, 1.022067, 1.050983"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.007431, 0.014436, 0.021041, 0.026061, 0.147747", \
- "0.048089, 0.051199, 0.058718, 0.073619, 0.235306", \
- "0.092679, 0.092234, 0.095807, 0.109560, 0.295852", \
- "0.181227, 0.178365, 0.178683, 0.184095, 0.391655", \
- "0.896652, 0.891924, 0.887935, 0.881387, 0.953533"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.017662, 0.024101, 0.048536, 0.089682, 0.758844", \
- "0.096073, 0.094132, 0.101399, 0.124739, 0.723967", \
- "0.170991, 0.170809, 0.171462, 0.183197, 0.697268", \
- "0.322446, 0.322746, 0.321943, 0.324630, 0.702708", \
- "1.546214, 1.546427, 1.546374, 1.546212, 1.604669"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.016377, 0.048611, 0.062895, 0.114022, 0.768870", \
- "0.097096, 0.107288, 0.124463, 0.164913, 0.849231", \
- "0.182999, 0.185111, 0.195260, 0.230117, 0.915649", \
- "0.353304, 0.352681, 0.357067, 0.377842, 1.011080", \
- "1.730018, 1.729723, 1.730358, 1.730359, 2.006705"
- );
- }
- }
- timing () {
- related_pin: "B";
- timing_sense: negative_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.021404, 0.018148, 0.016999, 0.012352, -0.116477", \
- "0.073113, 0.069999, 0.071591, 0.077030, 0.012719", \
- "0.125310, 0.121160, 0.121831, 0.125821, 0.106267", \
- "0.228280, 0.223844, 0.223033, 0.224372, 0.254111", \
- "1.050975, 1.046727, 1.044059, 1.040846, 1.071937"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.009259, 0.023322, 0.030630, 0.037613, 0.214445", \
- "0.054518, 0.059015, 0.066642, 0.084249, 0.290662", \
- "0.099361, 0.100171, 0.103972, 0.118556, 0.346076", \
- "0.188116, 0.185793, 0.186314, 0.192750, 0.434451", \
- "0.903486, 0.899552, 0.895434, 0.889058, 0.974970"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.018177, 0.025953, 0.042317, 0.080707, 0.708600", \
- "0.095725, 0.094902, 0.100379, 0.117184, 0.657595", \
- "0.169936, 0.168818, 0.169550, 0.178176, 0.623126", \
- "0.322532, 0.321898, 0.322594, 0.323057, 0.620469", \
- "1.546325, 1.546425, 1.546433, 1.546433, 1.575338"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.027725, 0.061597, 0.100203, 0.128616, 0.760467", \
- "0.111045, 0.120997, 0.139653, 0.183957, 0.880925", \
- "0.197036, 0.200197, 0.212478, 0.247249, 0.949581", \
- "0.368936, 0.368337, 0.372047, 0.394425, 1.042426", \
- "1.745637, 1.745218, 1.745426, 1.745645, 2.034164"
- );
- }
- }
- timing () {
- related_pin: "A";
- timing_sense: negative_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.021535, 0.020687, 0.018209, 0.011098, -0.159177", \
- "0.073633, 0.071954, 0.071241, 0.072771, -0.039713", \
- "0.126395, 0.123666, 0.122260, 0.121428, 0.047912", \
- "0.228694, 0.226313, 0.223648, 0.220474, 0.190997", \
- "1.051376, 1.049091, 1.044628, 1.037782, 1.009584"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.006124, 0.029256, 0.038292, 0.053214, 0.282467", \
- "0.059066, 0.066388, 0.074590, 0.095077, 0.348409", \
- "0.104913, 0.107511, 0.112061, 0.127680, 0.398783", \
- "0.193938, 0.193305, 0.193982, 0.201534, 0.479599", \
- "0.910076, 0.906960, 0.902862, 0.896691, 0.998792"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.018579, 0.025146, 0.039182, 0.078947, 0.732260", \
- "0.095594, 0.095225, 0.095216, 0.111960, 0.683970", \
- "0.171029, 0.169347, 0.171096, 0.178076, 0.654431", \
- "0.322754, 0.321497, 0.322026, 0.323327, 0.642474", \
- "1.546326, 1.546372, 1.546374, 1.546417, 1.579783"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.032924, 0.073273, 0.111837, 0.141861, 0.820044", \
- "0.127458, 0.138303, 0.154962, 0.200434, 0.924242", \
- "0.212672, 0.215586, 0.228733, 0.265521, 0.987165", \
- "0.383595, 0.383606, 0.388604, 0.411154, 1.077362", \
- "1.760289, 1.760204, 1.760698, 1.760729, 2.064944"
- );
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/cells/lib/OAI21X1.lib b/cells/lib/OAI21X1.lib
index 7cfea33..8795016 100644
--- a/cells/lib/OAI21X1.lib
+++ b/cells/lib/OAI21X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (OAI21X1) {
- area: 1.0;
+ area: 219456.0;
cell_leakage_power: 0.1173;
pin (C) {
capacitance: 0.0049685503383930275;
diff --git a/cells/lib/OAI22X1.lib b/cells/lib/OAI22X1.lib
index 6c9ec6b..d9c16d2 100644
--- a/cells/lib/OAI22X1.lib
+++ b/cells/lib/OAI22X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (OAI22X1) {
- area: 1.0;
+ area: 274320.0;
cell_leakage_power: 0.1173;
pin (D) {
capacitance: 0.0021453532257938264;
diff --git a/cells/lib/OR2X1.lib b/cells/lib/OR2X1.lib
index 116bb16..95a99d8 100644
--- a/cells/lib/OR2X1.lib
+++ b/cells/lib/OR2X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (OR2X1) {
- area: 1.0;
+ area: 219456.0;
cell_leakage_power: 0.1173;
pin (B) {
capacitance: 0.007576401997672222;
diff --git a/cells/lib/OR2X2.lib b/cells/lib/OR2X2.lib
deleted file mode 100644
index d818b4d..0000000
--- a/cells/lib/OR2X2.lib
+++ /dev/null
@@ -1,329 +0,0 @@
-library (ls05_stdcells) {
- capacitive_load_unit (1.0, pf);
- current_unit: "1uA";
- default_operating_conditions: typical;
- delay_model: table_lookup;
- in_place_swap_mode: match_footprint;
- input_threshold_pct_fall: 50.0;
- input_threshold_pct_rise: 50.0;
- leakage_power_unit: "1nW";
- nom_process: 1.0;
- nom_temperature: 25.0;
- nom_voltage: 5.0;
- output_threshold_pct_fall: 50.0;
- output_threshold_pct_rise: 50.0;
- pulling_resistance_unit: "1kohm";
- slew_lower_threshold_pct_fall: 20.0;
- slew_lower_threshold_pct_rise: 20.0;
- slew_upper_threshold_pct_fall: 80.0;
- slew_upper_threshold_pct_rise: 80.0;
- time_unit: "1ns";
- voltage_unit: "1V";
- operating_conditions (typical) {
- process: 1.0;
- temperature: 25.0;
- voltage: 5.0;
- }
- lu_table_template (delay_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- power_lut_template (energy_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- lu_table_template (hold_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (hold_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- power_lut_template (passive_energy_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_transition_time;
- }
- power_lut_template (passive_energy_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_transition_time;
- }
- lu_table_template (recovery_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (recovery_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (removal_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- cell (OR2X2) {
- area: 1.0;
- cell_leakage_power: 0.1173;
- pin (B) {
- capacitance: 0.007576401997672222;
- direction: input;
- fall_capacitance: 0.008853042755779209;
- rise_capacitance: 0.006299761239565236;
- }
- pin (A) {
- capacitance: 0.006280956134443613;
- direction: input;
- fall_capacitance: 0.006252202564509515;
- rise_capacitance: 0.006309709704377711;
- }
- pin (Y) {
- direction: output;
- function: "(!!A & !B)";
- timing () {
- related_pin: "B";
- timing_sense: positive_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "-0.002737, 0.013249, 0.024740, 0.030135, 0.058150", \
- "0.042967, 0.048920, 0.058700, 0.066027, 0.128620", \
- "0.085691, 0.083076, 0.088849, 0.098329, 0.169802", \
- "0.172823, 0.161427, 0.160431, 0.161812, 0.229754", \
- "0.876988, 0.854756, 0.839524, 0.814610, 0.732242"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.029512, 0.033910, 0.037914, 0.050330, 0.052929", \
- "0.070267, 0.072997, 0.078009, 0.091347, 0.135739", \
- "0.112746, 0.114735, 0.118673, 0.130593, 0.209389", \
- "0.200112, 0.201924, 0.204703, 0.213815, 0.340853", \
- "0.914821, 0.916103, 0.917764, 0.922353, 1.006921"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.016092, 0.057938, 0.095965, 0.165885, 0.705458", \
- "0.078905, 0.104180, 0.138126, 0.202710, 0.704503", \
- "0.148545, 0.161533, 0.188973, 0.232451, 0.725913", \
- "0.289045, 0.288648, 0.297219, 0.323752, 0.788330", \
- "1.420575, 1.420547, 1.420296, 1.420209, 1.575305"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.024665, 0.028188, 0.037838, 0.067587, 0.608216", \
- "0.097377, 0.097071, 0.100693, 0.117571, 0.616589", \
- "0.178290, 0.178809, 0.181589, 0.191054, 0.624945", \
- "0.348706, 0.349016, 0.349686, 0.352764, 0.697194", \
- "1.725555, 1.725371, 1.726655, 1.725685, 1.854607"
- );
- }
- }
- timing () {
- related_pin: "A";
- timing_sense: positive_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "-0.002786, -0.022525, 0.019015, 0.011670, -0.014214", \
- "0.041859, 0.043298, 0.052130, 0.057857, 0.058886", \
- "0.085034, 0.078556, 0.083166, 0.090278, 0.102558", \
- "0.172887, 0.158458, 0.155718, 0.154087, 0.173297", \
- "0.877505, 0.854378, 0.837626, 0.810046, 0.720442"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.028690, 0.031248, 0.037463, 0.044487, 0.100482", \
- "0.069107, 0.069828, 0.076360, 0.091636, 0.185145", \
- "0.112034, 0.111088, 0.115798, 0.129197, 0.254233", \
- "0.199087, 0.197989, 0.201090, 0.209121, 0.374419", \
- "0.914050, 0.911951, 0.913051, 0.915105, 1.007909"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.013392, 0.052206, 0.087689, 0.154666, 0.691395", \
- "0.076707, 0.097805, 0.133251, 0.196593, 0.689662", \
- "0.148818, 0.159357, 0.181649, 0.221635, 0.720108", \
- "0.288045, 0.289252, 0.294522, 0.318177, 0.791961", \
- "1.420335, 1.420191, 1.420219, 1.420439, 1.583354"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.024973, 0.029481, 0.044119, 0.082711, 0.664635", \
- "0.097225, 0.099096, 0.107079, 0.133341, 0.664451", \
- "0.179958, 0.178788, 0.182955, 0.202839, 0.677564", \
- "0.347947, 0.348719, 0.349929, 0.358002, 0.742083", \
- "1.725186, 1.725383, 1.725427, 1.725691, 1.862987"
- );
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/cells/lib/XNOR2X1.lib b/cells/lib/XNOR2X1.lib
index 90b0b93..0ae60ea 100644
--- a/cells/lib/XNOR2X1.lib
+++ b/cells/lib/XNOR2X1.lib
@@ -179,7 +179,7 @@
variable_2: constrained_pin_transition;
}
cell (XNOR2X1) {
- area: 1.0;
+ area: 384048.0;
cell_leakage_power: 0.1173;
pin (B) {
capacitance: 0.013514822660098;
diff --git a/cells/lib/XOR2X1.lib b/cells/lib/XOR2X1.lib
deleted file mode 100644
index d941f1f..0000000
--- a/cells/lib/XOR2X1.lib
+++ /dev/null
@@ -1,329 +0,0 @@
-library (ls05_stdcells) {
- capacitive_load_unit (1.0, pf);
- current_unit: "1uA";
- default_operating_conditions: typical;
- delay_model: table_lookup;
- in_place_swap_mode: match_footprint;
- input_threshold_pct_fall: 50.0;
- input_threshold_pct_rise: 50.0;
- leakage_power_unit: "1nW";
- nom_process: 1.0;
- nom_temperature: 25.0;
- nom_voltage: 5.0;
- output_threshold_pct_fall: 50.0;
- output_threshold_pct_rise: 50.0;
- pulling_resistance_unit: "1kohm";
- slew_lower_threshold_pct_fall: 20.0;
- slew_lower_threshold_pct_rise: 20.0;
- slew_upper_threshold_pct_fall: 80.0;
- slew_upper_threshold_pct_rise: 80.0;
- time_unit: "1ns";
- voltage_unit: "1V";
- operating_conditions (typical) {
- process: 1.0;
- temperature: 25.0;
- voltage: 5.0;
- }
- lu_table_template (delay_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- lu_table_template (delay_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_net_transition;
- }
- lu_table_template (delay_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_net_transition;
- }
- power_lut_template (energy_template_5x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_5x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- power_lut_template (energy_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: total_output_net_capacitance;
- variable_2: input_transition_time;
- }
- lu_table_template (hold_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (hold_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- power_lut_template (passive_energy_template_5x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: input_transition_time;
- }
- power_lut_template (passive_energy_template_6x1) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: input_transition_time;
- }
- lu_table_template (recovery_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (recovery_template_6x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (removal_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x5) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- lu_table_template (setup_template_3x6) {
- index_1 (
- "1000.0, 1001.0, 1002.0"
- );
- index_2 (
- "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0"
- );
- variable_1: related_pin_transition;
- variable_2: constrained_pin_transition;
- }
- cell (XOR2X1) {
- area: 1.0;
- cell_leakage_power: 0.1173;
- pin (B) {
- capacitance: 0.012276358158465816;
- direction: input;
- fall_capacitance: 0.013427310434186409;
- rise_capacitance: 0.011125405882745222;
- }
- pin (A) {
- capacitance: 0.00749442073476893;
- direction: input;
- fall_capacitance: 0.009072357734937673;
- rise_capacitance: 0.005916483734600188;
- }
- pin (Y) {
- direction: output;
- function: "(!(A & B + !A & !B))";
- timing () {
- related_pin: "B";
- timing_sense: non_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.014892, 0.026098, 0.032153, 0.035628, 0.047318", \
- "0.092224, 0.096655, 0.101443, 0.112719, 0.182767", \
- "0.169673, 0.171668, 0.175532, 0.183060, 0.283111", \
- "0.324128, 0.324946, 0.326965, 0.330982, 0.455128", \
- "1.563499, 1.563195, 1.562797, 1.561380, 1.609543"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.024062, 0.032769, 0.038614, 0.047550, 0.088606", \
- "0.116083, 0.118915, 0.123597, 0.135586, 0.246157", \
- "0.209677, 0.211048, 0.214246, 0.222844, 0.363632", \
- "0.398099, 0.398428, 0.399744, 0.404595, 0.555144", \
- "1.909496, 1.908653, 1.907693, 1.906646, 1.962945"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.025254, 0.046375, 0.039294, 0.072021, 0.273173", \
- "0.133780, 0.132393, 0.135503, 0.147696, 0.398969", \
- "0.244610, 0.245358, 0.245256, 0.247565, 0.499327", \
- "0.469332, 0.469791, 0.469256, 0.469907, 0.636792", \
- "2.271962, 2.271926, 2.271949, 2.271912, 2.273340"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.030994, 0.031460, 0.039808, 0.071119, 0.265648", \
- "0.158547, 0.158367, 0.159273, 0.166528, 0.433196", \
- "0.288225, 0.287669, 0.287878, 0.288591, 0.539227", \
- "0.548600, 0.548684, 0.548694, 0.548722, 0.704892", \
- "2.640937, 2.640941, 2.640938, 2.640974, 2.640919"
- );
- }
- }
- timing () {
- related_pin: "A";
- timing_sense: non_unate;
- cell_rise (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.012892, 0.017730, 0.023813, 0.027360, 0.044820", \
- "0.088467, 0.084827, 0.087953, 0.101073, 0.177048", \
- "0.165423, 0.159431, 0.159037, 0.166450, 0.271959", \
- "0.319577, 0.311467, 0.307870, 0.308677, 0.436355", \
- "1.558626, 1.548309, 1.540221, 1.529215, 1.518702"
- );
- }
- cell_fall (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.016957, 0.021051, 0.026086, 0.031933, 0.049325", \
- "0.105617, 0.101524, 0.101659, 0.109154, 0.189216", \
- "0.199262, 0.192615, 0.189350, 0.188747, 0.294117", \
- "0.387542, 0.379182, 0.372626, 0.364699, 0.471910", \
- "1.898845, 1.888610, 1.878187, 1.859516, 1.755959"
- );
- }
- rise_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.023742, 0.042643, 0.072286, 0.090530, 0.566724", \
- "0.132629, 0.134268, 0.137045, 0.160242, 0.603489", \
- "0.244817, 0.245637, 0.244852, 0.253117, 0.662530", \
- "0.469395, 0.469226, 0.469550, 0.469622, 0.758597", \
- "2.271920, 2.272019, 2.271961, 2.271949, 2.283313"
- );
- }
- fall_transition (delay_template_5x5) {
- index_1 (
- "0.000500, 0.050000, 0.100000, 0.200000, 1.000000"
- );
- index_2 (
- "0.010000, 0.050000, 0.100000, 0.200000, 1.500000"
- );
- values (
- "0.029158, 0.032762, 0.049130, 0.090068, 0.563023", \
- "0.158384, 0.157282, 0.158756, 0.175473, 0.633346", \
- "0.287824, 0.288245, 0.288387, 0.291586, 0.711223", \
- "0.548431, 0.548524, 0.548547, 0.548816, 0.844417", \
- "2.640867, 2.640887, 2.640922, 2.640988, 2.646707"
- );
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/cells/lib/libresilicon.lib b/cells/lib/libresilicon.lib
index 27a2e79..2bedd49 100644
--- a/cells/lib/libresilicon.lib
+++ b/cells/lib/libresilicon.lib
@@ -1 +1 @@
-library (ls05_stdcells) { capacitive_load_unit (1.0, pf); current_unit: "1uA"; default_operating_conditions: typical; delay_model: table_lookup; in_place_swap_mode: match_footprint; input_threshold_pct_fall: 50.0; input_threshold_pct_rise: 50.0; leakage_power_unit: "1nW"; nom_process: 1.0; nom_temperature: 25.0; nom_voltage: 5.0; output_threshold_pct_fall: 50.0; output_threshold_pct_rise: 50.0; pulling_resistance_unit: "1kohm"; slew_lower_threshold_pct_fall: 20.0; slew_lower_threshold_pct_rise: 20.0; slew_upper_threshold_pct_fall: 80.0; slew_upper_threshold_pct_rise: 80.0; time_unit: "1ns"; voltage_unit: "1V"; operating_conditions (typical) { process: 1.0; temperature: 25.0; voltage: 5.0; } lu_table_template (delay_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } power_lut_template (energy_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } lu_table_template (hold_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (hold_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } power_lut_template (passive_energy_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_transition_time; } power_lut_template (passive_energy_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_transition_time; } lu_table_template (recovery_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (recovery_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (removal_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } cell (INVX1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 109728.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007547126607243736; direction: input; fall_capacitance: 0.008904762554228705; rise_capacitance: 0.0061894906602587675; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", "0.881893, 0.869050, 0.853857, 0.827782, 0.824694" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", "0.895275, 0.891758, 0.887322, 0.880070, 0.928854" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", "1.419778, 1.420153, 1.419732, 1.419717, 1.673889" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", "1.725267, 1.725008, 1.725609, 1.725893, 1.975591" ); } } } }}
\ No newline at end of file
+library (ls05_stdcells) { capacitive_load_unit (1.0, pf); current_unit: "1uA"; default_operating_conditions: typical; delay_model: table_lookup; in_place_swap_mode: match_footprint; input_threshold_pct_fall: 50.0; input_threshold_pct_rise: 50.0; leakage_power_unit: "1nW"; nom_process: 1.0; nom_temperature: 25.0; nom_voltage: 5.0; output_threshold_pct_fall: 50.0; output_threshold_pct_rise: 50.0; pulling_resistance_unit: "1kohm"; slew_lower_threshold_pct_fall: 20.0; slew_lower_threshold_pct_rise: 20.0; slew_upper_threshold_pct_fall: 80.0; slew_upper_threshold_pct_rise: 80.0; time_unit: "1ns"; voltage_unit: "1V"; operating_conditions (typical) { process: 1.0; temperature: 25.0; voltage: 5.0; } lu_table_template (delay_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } lu_table_template (delay_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_net_transition; } lu_table_template (delay_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_net_transition; } power_lut_template (energy_template_5x5) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_5x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } power_lut_template (energy_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: total_output_net_capacitance; variable_2: input_transition_time; } lu_table_template (hold_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (hold_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } power_lut_template (passive_energy_template_5x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: input_transition_time; } power_lut_template (passive_energy_template_6x1) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: input_transition_time; } lu_table_template (recovery_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (recovery_template_6x6) { index_1 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (removal_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x5) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } lu_table_template (setup_template_3x6) { index_1 ( "1000.0, 1001.0, 1002.0" ); index_2 ( "1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0" ); variable_1: related_pin_transition; variable_2: constrained_pin_transition; } cell (AND2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.006376640566539888; direction: input; fall_capacitance: 0.007817866144461614; rise_capacitance: 0.004935414988618162; } pin (A) { capacitance: 0.004934912141017381; direction: input; fall_capacitance: 0.005718976233108118; rise_capacitance: 0.004150848048926644; } pin (Y) { direction: output; function: "(A & B)"; timing () { related_pin: "B"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002948, 0.031940, 0.041541, 0.057971, 0.167270", "0.046740, 0.066340, 0.080659, 0.100026, 0.234969", "0.087186, 0.100322, 0.115691, 0.131365, 0.287516", "0.172387, 0.177799, 0.194182, 0.207143, 0.391362", "0.875090, 0.868452, 0.882814, 0.885407, 1.014582" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018337, 0.021491, 0.024061, 0.022400, -0.034178", "0.057356, 0.058976, 0.061060, 0.061598, 0.018699", "0.101068, 0.100276, 0.099697, 0.099202, 0.056903", "0.189356, 0.187013, 0.183889, 0.178499, 0.123050", "0.904340, 0.900488, 0.894961, 0.882939, 0.736675" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023782, 0.069362, 0.036426, 0.060782, 0.451813", "0.082213, 0.120065, 0.087665, 0.099865, 0.447412", "0.148581, 0.153464, 0.150834, 0.158504, 0.456107", "0.288739, 0.289793, 0.288655, 0.291280, 0.521942", "1.420537, 1.420621, 1.420499, 1.420615, 1.490972" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020393, 0.034829, 0.056096, 0.100019, 0.517345", "0.095190, 0.099481, 0.112772, 0.142410, 0.561271", "0.177215, 0.179045, 0.186734, 0.209104, 0.606400", "0.348536, 0.348577, 0.350362, 0.361641, 0.706589", "1.724982, 1.724975, 1.726148, 1.725949, 1.797117" ); } } timing () { related_pin: "A"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.003054, 0.030756, 0.036895, 0.053450, 0.189178", "0.048196, 0.064408, 0.074956, 0.091763, 0.252273", "0.087882, 0.098714, 0.108728, 0.124797, 0.301834", "0.172911, 0.177390, 0.184992, 0.194729, 0.394941", "0.874950, 0.870127, 0.872743, 0.868968, 0.975510" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015977, 0.018578, 0.018625, 0.016540, -0.078601", "0.056110, 0.056571, 0.057910, 0.059432, -0.014766", "0.100103, 0.098361, 0.096720, 0.097022, 0.031993", "0.188179, 0.185369, 0.181269, 0.175611, 0.117769", "0.903173, 0.899107, 0.892661, 0.880044, 0.755676" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026432, 0.041227, 0.045227, 0.082731, 0.591445", "0.081271, 0.098565, 0.094743, 0.114263, 0.587890", "0.150173, 0.152420, 0.156118, 0.171333, 0.591808", "0.288387, 0.289298, 0.289941, 0.296010, 0.641073", "1.420770, 1.420848, 1.420544, 1.420583, 1.523188" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017097, 0.032096, 0.052471, 0.097966, 0.610977", "0.094380, 0.097484, 0.111245, 0.144180, 0.624946", "0.178566, 0.178965, 0.185471, 0.210040, 0.674274", "0.348822, 0.348770, 0.350494, 0.361953, 0.778001", "1.726209, 1.725209, 1.724995, 1.725568, 1.841959" ); } } } } cell (AND2X2) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.006376640566539888; direction: input; fall_capacitance: 0.007817866144461614; rise_capacitance: 0.004935414988618162; } pin (A) { capacitance: 0.004934912141017381; direction: input; fall_capacitance: 0.005718976233108118; rise_capacitance: 0.004150848048926644; } pin (Y) { direction: output; function: "(A & B)"; timing () { related_pin: "B"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002948, 0.031940, 0.041541, 0.057971, 0.167270", "0.046740, 0.066340, 0.080659, 0.100026, 0.234969", "0.087186, 0.100322, 0.115691, 0.131365, 0.287516", "0.172387, 0.177799, 0.194182, 0.207143, 0.391362", "0.875090, 0.868452, 0.882814, 0.885407, 1.014582" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018337, 0.021491, 0.024061, 0.022400, -0.034178", "0.057356, 0.058976, 0.061060, 0.061598, 0.018699", "0.101068, 0.100276, 0.099697, 0.099202, 0.056903", "0.189356, 0.187013, 0.183889, 0.178499, 0.123050", "0.904340, 0.900488, 0.894961, 0.882939, 0.736675" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023782, 0.069362, 0.036426, 0.060782, 0.451813", "0.082213, 0.120065, 0.087665, 0.099865, 0.447412", "0.148581, 0.153464, 0.150834, 0.158504, 0.456107", "0.288739, 0.289793, 0.288655, 0.291280, 0.521942", "1.420537, 1.420621, 1.420499, 1.420615, 1.490972" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020393, 0.034829, 0.056096, 0.100019, 0.517345", "0.095190, 0.099481, 0.112772, 0.142410, 0.561271", "0.177215, 0.179045, 0.186734, 0.209104, 0.606400", "0.348536, 0.348577, 0.350362, 0.361641, 0.706589", "1.724982, 1.724975, 1.726148, 1.725949, 1.797117" ); } } timing () { related_pin: "A"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.003054, 0.030756, 0.036895, 0.053450, 0.189178", "0.048196, 0.064408, 0.074956, 0.091763, 0.252273", "0.087882, 0.098714, 0.108728, 0.124797, 0.301834", "0.172911, 0.177390, 0.184992, 0.194729, 0.394941", "0.874950, 0.870127, 0.872743, 0.868968, 0.975510" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015977, 0.018578, 0.018625, 0.016540, -0.078601", "0.056110, 0.056571, 0.057910, 0.059432, -0.014766", "0.100103, 0.098361, 0.096720, 0.097022, 0.031993", "0.188179, 0.185369, 0.181269, 0.175611, 0.117769", "0.903173, 0.899107, 0.892661, 0.880044, 0.755676" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026432, 0.041227, 0.045227, 0.082731, 0.591445", "0.081271, 0.098565, 0.094743, 0.114263, 0.587890", "0.150173, 0.152420, 0.156118, 0.171333, 0.591808", "0.288387, 0.289298, 0.289941, 0.296010, 0.641073", "1.420770, 1.420848, 1.420544, 1.420583, 1.523188" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017097, 0.032096, 0.052471, 0.097966, 0.610977", "0.094380, 0.097484, 0.111245, 0.144180, 0.624946", "0.178566, 0.178965, 0.185471, 0.210040, 0.674274", "0.348822, 0.348770, 0.350494, 0.361953, 0.778001", "1.726209, 1.725209, 1.724995, 1.725568, 1.841959" ); } } } } cell (AOI21X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (C) { capacitance: 0.006189667947317773; direction: input; fall_capacitance: 0.00608282711442158; rise_capacitance: 0.006296508780213967; } pin (B) { capacitance: 0.004946001600705809; direction: input; fall_capacitance: 0.005741143923488236; rise_capacitance: 0.004150859277923382; } pin (A) { capacitance: 0.0063768651510662175; direction: input; fall_capacitance: 0.007818310946312182; rise_capacitance: 0.0049354193558202525; } pin (Y) { direction: output; function: "((A & !B & !C + B & !A & !C + !A & !B & !C))"; timing () { related_pin: "C"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012884, 0.013814, 0.016718, 0.021870, 0.028833", "0.086107, 0.080864, 0.082497, 0.093433, 0.172718", "0.157907, 0.150075, 0.149039, 0.154342, 0.270928", "0.301166, 0.291665, 0.287163, 0.285601, 0.427419", "1.448480, 1.437527, 1.428051, 1.413899, 1.417674" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005708, 0.008603, 0.010605, 0.008342, 0.014912", "0.046767, 0.047758, 0.052811, 0.059897, 0.111616", "0.091313, 0.089826, 0.091015, 0.099539, 0.178409", "0.180111, 0.176982, 0.175277, 0.175888, 0.287227", "0.895506, 0.891449, 0.886851, 0.878783, 0.902515" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012972, 0.024876, 0.045576, 0.092382, 0.730301", "0.117670, 0.118582, 0.124112, 0.144342, 0.702744", "0.221586, 0.221908, 0.222072, 0.232193, 0.694310", "0.430244, 0.430091, 0.430239, 0.430802, 0.761045", "2.104719, 2.104806, 2.104636, 2.104737, 2.138480" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013144, 0.040328, 0.065020, 0.111186, 0.739334", "0.095171, 0.101388, 0.116357, 0.159575, 0.811404", "0.180158, 0.181007, 0.191810, 0.223783, 0.880144", "0.350588, 0.350580, 0.354001, 0.371311, 0.983014", "1.727889, 1.727581, 1.728170, 1.727705, 1.982896" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015335, 0.016982, 0.017673, 0.018219, -0.069608", "0.094019, 0.093932, 0.095770, 0.102779, 0.105301", "0.171502, 0.171151, 0.171863, 0.175258, 0.222703", "0.326268, 0.325524, 0.325280, 0.326346, 0.409421", "1.565887, 1.565044, 1.563580, 1.561246, 1.585994" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013287, 0.024880, 0.031685, 0.037498, 0.167659", "0.107124, 0.105845, 0.107193, 0.117896, 0.299712", "0.201357, 0.197038, 0.194436, 0.196480, 0.391707", "0.390085, 0.383995, 0.377751, 0.370715, 0.543155", "1.901754, 1.893671, 1.883505, 1.864991, 1.785557" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013701, 0.021239, 0.037128, 0.074532, 0.517052", "0.124145, 0.126554, 0.127481, 0.138597, 0.502699", "0.236289, 0.237521, 0.237587, 0.239899, 0.557716", "0.461681, 0.461011, 0.461333, 0.461741, 0.666948", "2.263739, 2.263875, 2.263871, 2.263837, 2.266936" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.030160, 0.038814, 0.058225, 0.102917, 0.553894", "0.158458, 0.157631, 0.161617, 0.182586, 0.706485", "0.287898, 0.286716, 0.287445, 0.295747, 0.780606", "0.548485, 0.548526, 0.548522, 0.548250, 0.902420", "2.640741, 2.640742, 2.640727, 2.640745, 2.647561" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018081, 0.020472, 0.022446, 0.023825, -0.023691", "0.096239, 0.096537, 0.098721, 0.106326, 0.139254", "0.173813, 0.173358, 0.174228, 0.178403, 0.251687", "0.328514, 0.327676, 0.327494, 0.329061, 0.431351", "1.568114, 1.567133, 1.565660, 1.563413, 1.593357" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011083, 0.026784, 0.035062, 0.040835, 0.137110", "0.106329, 0.111405, 0.118093, 0.132531, 0.298206", "0.200961, 0.203504, 0.207727, 0.219147, 0.408186", "0.389721, 0.390740, 0.393162, 0.400718, 0.586451", "1.901421, 1.900917, 1.900632, 1.901495, 1.980436" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017574, 0.025241, 0.039240, 0.074436, 0.320255", "0.130209, 0.130934, 0.131571, 0.144964, 0.452202", "0.240805, 0.242496, 0.242369, 0.244406, 0.548288", "0.466498, 0.466251, 0.466522, 0.466774, 0.675363", "2.268774, 2.268830, 2.268824, 2.268768, 2.271727" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.029014, 0.034924, 0.042010, 0.073728, 0.327469", "0.158673, 0.158762, 0.158147, 0.170170, 0.467645", "0.287787, 0.287911, 0.287075, 0.288882, 0.551159", "0.548458, 0.548226, 0.548509, 0.548657, 0.704977", "2.640715, 2.640671, 2.640748, 2.640738, 2.640639" ); } } } } cell (AOI22X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 274320.0; cell_leakage_power: 0.1173; pin (D) { capacitance: 0.0020974613531819556; direction: input; fall_capacitance: 4.4104117800871274e-05; rise_capacitance: 0.004150818588563039; } pin (C) { capacitance: 0.004812606268016478; direction: input; fall_capacitance: 0.004689865191387634; rise_capacitance: 0.0049353473446453215; } pin (B) { capacitance: 0.004946165373579888; direction: input; fall_capacitance: 0.005741463237564304; rise_capacitance: 0.0041508675095954725; } pin (A) { capacitance: 0.006371776083769734; direction: input; fall_capacitance: 0.007808127096433607; rise_capacitance: 0.004935425071105862; } pin (Y) { direction: output; function: "(!(A & B & C & D + A & B & C & !D + A & B & D & !C + A & C & D & !B + B & C & D & !A + A & B & !C & !D + C & D & !A & !B))"; timing () { related_pin: "D"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.016935, 0.014883, 0.015703, 0.012454, -0.033501", "0.090542, 0.082772, 0.082614, 0.090524, 0.114504", "0.162325, 0.152911, 0.149501, 0.151692, 0.215638", "0.305626, 0.294845, 0.288283, 0.283584, 0.379358", "1.452827, 1.441115, 1.430562, 1.414232, 1.385088" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011131, 0.018803, 0.024733, 0.032496, 0.108096", "0.102250, 0.099676, 0.101552, 0.112143, 0.253101", "0.196075, 0.190340, 0.188422, 0.190760, 0.352663", "0.384766, 0.377069, 0.371270, 0.364996, 0.516099", "1.896343, 1.886398, 1.876274, 1.858129, 1.777799" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.016765, 0.027275, 0.049942, 0.091821, 0.629255", "0.121167, 0.122670, 0.127043, 0.150833, 0.656506", "0.224824, 0.225478, 0.225444, 0.237122, 0.716205", "0.433527, 0.433720, 0.433798, 0.434581, 0.814040", "2.108310, 2.108361, 2.108226, 2.108327, 2.151506" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019540, 0.037485, 0.048144, 0.090862, 0.624895", "0.148113, 0.148658, 0.152486, 0.173373, 0.676277", "0.277916, 0.277395, 0.278530, 0.285802, 0.738740", "0.538822, 0.539108, 0.538745, 0.539142, 0.865875", "2.631103, 2.631167, 2.631060, 2.631158, 2.638378" ); } } timing () { related_pin: "C"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020369, 0.018428, 0.021368, 0.020061, 0.016757", "0.092490, 0.085158, 0.085310, 0.094546, 0.156465", "0.164627, 0.154984, 0.151976, 0.154901, 0.251955", "0.307751, 0.296984, 0.290533, 0.286397, 0.406843", "1.454952, 1.443103, 1.432571, 1.416364, 1.394708" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.010498, 0.021560, 0.028514, 0.037495, 0.082368", "0.101825, 0.105130, 0.112161, 0.127308, 0.261185", "0.195561, 0.196794, 0.201635, 0.213814, 0.379961", "0.384369, 0.383935, 0.386589, 0.394605, 0.568320", "1.895945, 1.893647, 1.893375, 1.894401, 1.975233" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.021236, 0.031459, 0.054625, 0.095131, 0.470508", "0.126934, 0.126375, 0.131675, 0.156729, 0.627474", "0.229762, 0.229630, 0.230077, 0.241674, 0.716118", "0.438091, 0.438482, 0.438252, 0.439405, 0.825499", "2.112964, 2.112929, 2.112863, 2.112978, 2.155164" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.021627, 0.035591, 0.035070, 0.070098, 0.433450", "0.147776, 0.149177, 0.150009, 0.161817, 0.458917", "0.277709, 0.277366, 0.277596, 0.280531, 0.527096", "0.539065, 0.539093, 0.539109, 0.538946, 0.684263", "2.631099, 2.631149, 2.631170, 2.631100, 2.631114" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019809, 0.021467, 0.022993, 0.023258, -0.058701", "0.092131, 0.092348, 0.095145, 0.101841, 0.098557", "0.164877, 0.164124, 0.165065, 0.169626, 0.210368", "0.308029, 0.307392, 0.307470, 0.309169, 0.390164", "1.457169, 1.456286, 1.455144, 1.453124, 1.488193" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013313, 0.029532, 0.038717, 0.047945, 0.188158", "0.107990, 0.110195, 0.113203, 0.124738, 0.313534", "0.202371, 0.200606, 0.199392, 0.203099, 0.404174", "0.391167, 0.386925, 0.382011, 0.376561, 0.554823", "1.902931, 1.895987, 1.886227, 1.868549, 1.797821" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019429, 0.026568, 0.042468, 0.080756, 0.516753", "0.124108, 0.123505, 0.123820, 0.139390, 0.517896", "0.226304, 0.226453, 0.226121, 0.229413, 0.571103", "0.432605, 0.432992, 0.433334, 0.433130, 0.669772", "2.096546, 2.096500, 2.096504, 2.096401, 2.104903" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.036963, 0.064663, 0.063261, 0.104268, 0.557323", "0.169060, 0.168178, 0.170874, 0.190953, 0.690517", "0.298594, 0.298892, 0.298450, 0.305039, 0.761400", "0.559542, 0.559072, 0.559520, 0.559454, 0.890958", "2.651812, 2.651739, 2.651820, 2.651765, 2.658183" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.022678, 0.024602, 0.027657, 0.027746, -0.014253", "0.094425, 0.094825, 0.097714, 0.105256, 0.133288", "0.166876, 0.166299, 0.167299, 0.172465, 0.239654", "0.310022, 0.309359, 0.309537, 0.311595, 0.412132", "1.459221, 1.458255, 1.457052, 1.455130, 1.495355" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.010762, 0.031615, 0.042726, 0.054379, 0.162255", "0.107178, 0.114877, 0.123673, 0.140333, 0.314762", "0.201740, 0.206695, 0.212432, 0.225560, 0.423426", "0.390675, 0.393589, 0.396909, 0.405745, 0.599731", "1.902538, 1.903226, 1.903241, 1.904537, 1.991568" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023953, 0.030647, 0.045679, 0.081384, 0.352989", "0.128243, 0.127626, 0.127724, 0.144629, 0.476733", "0.230700, 0.231079, 0.230551, 0.233540, 0.563234", "0.437513, 0.437483, 0.437930, 0.437603, 0.677229", "2.101139, 2.101103, 2.101049, 2.100995, 2.109091" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.035078, 0.066496, 0.049387, 0.080483, 0.340869", "0.168775, 0.168226, 0.168846, 0.179604, 0.463584", "0.298761, 0.298598, 0.298932, 0.300297, 0.541365", "0.559293, 0.559471, 0.559155, 0.559533, 0.704149", "2.651791, 2.651807, 2.651756, 2.651826, 2.651827" ); } } } } cell (BUFX2) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 164592.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007524621021778557; direction: input; fall_capacitance: 0.00885894979294924; rise_capacitance: 0.006190292250607873; } pin (Y) { direction: output; function: "(A)"; timing () { related_pin: "A"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.003161, 0.017829, 0.022268, 0.021768, 0.079308", "0.045055, 0.050063, 0.057136, 0.070246, 0.151768", "0.086221, 0.085910, 0.089124, 0.100838, 0.199664", "0.172654, 0.166239, 0.164336, 0.168034, 0.284850", "0.876097, 0.863347, 0.851849, 0.832547, 0.852986" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.014482, 0.017268, 0.019923, 0.023667, -0.011126", "0.054563, 0.055999, 0.060204, 0.069455, 0.072439", "0.098790, 0.098063, 0.098828, 0.107532, 0.136737", "0.187149, 0.184801, 0.183271, 0.184852, 0.249296", "0.902112, 0.898842, 0.894592, 0.887713, 0.887222" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.021141, 0.053260, 0.060446, 0.114111, 0.839043", "0.078233, 0.096018, 0.107000, 0.143602, 0.829526", "0.148965, 0.150631, 0.162142, 0.191631, 0.827817", "0.288402, 0.288541, 0.290092, 0.306795, 0.865517", "1.420305, 1.420150, 1.420683, 1.420175, 1.615594" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015821, 0.030737, 0.052343, 0.106785, 0.838213", "0.092115, 0.097031, 0.110737, 0.149525, 0.839377", "0.177675, 0.179318, 0.186569, 0.215056, 0.850611", "0.349011, 0.348267, 0.350542, 0.364446, 0.905444", "1.725400, 1.725176, 1.725220, 1.725574, 1.913061" ); } } } } cell (HAX1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 603504.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.009565996302413171; direction: input; fall_capacitance: 0.008432988155991751; rise_capacitance: 0.010699004448834593; } pin (A) { capacitance: 0.012290968093010312; direction: input; fall_capacitance: 0.013216336710577052; rise_capacitance: 0.01136559947544357; } pin (YS) { direction: output; function: "(!(A & B + !A & !B))"; timing () { related_pin: "B"; timing_sense: non_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.004033, 0.032150, 0.044845, 0.050474, 0.051335", "0.055892, 0.068037, 0.080785, 0.093045, 0.114132", "0.094044, 0.101015, 0.112537, 0.126712, 0.158920", "0.175648, 0.176204, 0.184990, 0.197179, 0.244777", "0.873435, 0.863339, 0.864298, 0.866078, 0.855109" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017244, 0.032461, 0.048132, 0.062118, 0.137542", "0.058835, 0.069633, 0.084719, 0.104232, 0.192012", "0.100970, 0.106394, 0.118870, 0.138651, 0.235211", "0.187793, 0.189005, 0.197350, 0.213800, 0.316894", "0.902163, 0.898308, 0.900032, 0.906364, 0.948955" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.040974, 0.074951, 0.060349, 0.076555, 0.409013", "0.091957, 0.122622, 0.111250, 0.115255, 0.415747", "0.154170, 0.166605, 0.165996, 0.172579, 0.465956", "0.289870, 0.292343, 0.293138, 0.299508, 0.559512", "1.420665, 1.420862, 1.420515, 1.421028, 1.493654" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.028737, 0.067929, 0.109033, 0.090482, 0.482822", "0.100377, 0.125774, 0.164469, 0.180526, 0.509483", "0.180975, 0.197032, 0.211922, 0.221778, 0.555289", "0.348738, 0.353197, 0.357789, 0.370377, 0.658930", "1.725367, 1.725946, 1.725663, 1.725932, 1.793771" ); } } timing () { related_pin: "A"; timing_sense: non_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002915, 0.042398, 0.052176, 0.055423, 0.107987", "0.062544, 0.079393, 0.088727, 0.101216, 0.163975", "0.098867, 0.112677, 0.121587, 0.133731, 0.204781", "0.178683, 0.187584, 0.195187, 0.205349, 0.275393", "0.873877, 0.874214, 0.876238, 0.875094, 0.864245" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018517, 0.033815, 0.052985, 0.063145, 0.108475", "0.059426, 0.069693, 0.089732, 0.106611, 0.160828", "0.101430, 0.106262, 0.124529, 0.143828, 0.205452", "0.188322, 0.188871, 0.203005, 0.222224, 0.292784", "0.902655, 0.898231, 0.905344, 0.918863, 0.964905" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.048575, 0.056963, 0.055452, 0.077660, 0.348951", "0.097387, 0.109829, 0.107257, 0.116455, 0.374171", "0.157790, 0.160813, 0.162764, 0.173185, 0.415244", "0.289541, 0.291335, 0.292385, 0.299387, 0.509268", "1.420940, 1.420534, 1.420747, 1.420655, 1.464278" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.029875, 0.067731, 0.077584, 0.067492, 0.350562", "0.099533, 0.125664, 0.168623, 0.123478, 0.376209", "0.180545, 0.196321, 0.205234, 0.198481, 0.424205", "0.348869, 0.353115, 0.356059, 0.358578, 0.546504", "1.725470, 1.725570, 1.725963, 1.725775, 1.781596" ); } } } pin (YC) { direction: output; function: "(A & B)"; timing () { related_pin: "B"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002932, 0.031845, 0.046203, 0.059680, 0.206545", "0.049948, 0.068231, 0.085039, 0.104520, 0.274220", "0.089788, 0.101410, 0.117157, 0.136354, 0.323085", "0.173455, 0.176265, 0.188945, 0.205397, 0.412891", "0.873808, 0.861079, 0.865149, 0.869380, 0.984923" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020712, 0.024396, 0.025178, 0.022025, -0.060067", "0.060435, 0.061372, 0.064388, 0.066859, 0.006598", "0.103540, 0.102168, 0.102489, 0.103050, 0.053408", "0.191891, 0.188927, 0.186482, 0.180921, 0.136742", "0.906360, 0.902330, 0.897105, 0.883862, 0.767023" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.029065, 0.076707, 0.058814, 0.085996, 0.589693", "0.084308, 0.124052, 0.114916, 0.121842, 0.582858", "0.150913, 0.169854, 0.170202, 0.177980, 0.592114", "0.289080, 0.293361, 0.294671, 0.299955, 0.642962", "1.420626, 1.420601, 1.420595, 1.420438, 1.521560" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023168, 0.037493, 0.061782, 0.104667, 0.614021", "0.093949, 0.101336, 0.115157, 0.147186, 0.632991", "0.178031, 0.179618, 0.188053, 0.212969, 0.683615", "0.349299, 0.349430, 0.351228, 0.362707, 0.786505", "1.724877, 1.725713, 1.726013, 1.726067, 1.845083" ); } } timing () { related_pin: "A"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002877, 0.029610, 0.051114, 0.071379, 0.191002", "0.048630, 0.065299, 0.090272, 0.109498, 0.261067", "0.088953, 0.098443, 0.122749, 0.144721, 0.312452", "0.173170, 0.173273, 0.195093, 0.217717, 0.411821", "0.874061, 0.858051, 0.871543, 0.889533, 1.026567" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.022256, 0.026455, 0.029553, 0.031901, -0.015917", "0.062541, 0.063639, 0.067746, 0.071999, 0.041159", "0.104940, 0.104109, 0.105543, 0.107246, 0.080735", "0.192752, 0.190680, 0.189057, 0.184951, 0.147242", "0.907257, 0.903593, 0.899162, 0.887044, 0.752494" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026048, 0.073817, 0.050978, 0.065940, 0.443696", "0.083033, 0.121825, 0.103425, 0.102000, 0.436305", "0.150571, 0.172361, 0.163617, 0.164690, 0.449813", "0.288981, 0.293984, 0.293415, 0.294741, 0.517577", "1.420646, 1.420437, 1.420500, 1.420898, 1.486892" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.025591, 0.040492, 0.065936, 0.108105, 0.550325", "0.095286, 0.101971, 0.117506, 0.150589, 0.584408", "0.179426, 0.180898, 0.189227, 0.214201, 0.625356", "0.348855, 0.349403, 0.351841, 0.363528, 0.724101", "1.724988, 1.724959, 1.726109, 1.725779, 1.806215" ); } } } } cell (INV) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 109728.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007547126607243736; direction: input; fall_capacitance: 0.008904762554228705; rise_capacitance: 0.0061894906602587675; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", "0.881893, 0.869050, 0.853857, 0.827782, 0.824694" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", "0.895275, 0.891758, 0.887322, 0.880070, 0.928854" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", "1.419778, 1.420153, 1.419732, 1.419717, 1.673889" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", "1.725267, 1.725008, 1.725609, 1.725893, 1.975591" ); } } } } cell (INVX1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 109728.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007547126607243736; direction: input; fall_capacitance: 0.008904762554228705; rise_capacitance: 0.0061894906602587675; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", "0.881893, 0.869050, 0.853857, 0.827782, 0.824694" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", "0.895275, 0.891758, 0.887322, 0.880070, 0.928854" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", "1.419778, 1.420153, 1.419732, 1.419717, 1.673889" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", "1.725267, 1.725008, 1.725609, 1.725893, 1.975591" ); } } } } cell (INVX2) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 109728.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.007547126607243736; direction: input; fall_capacitance: 0.008904762554228705; rise_capacitance: 0.0061894906602587675; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005045, 0.004666, 0.003429, -0.000859, -0.065505", "0.044989, 0.042725, 0.047543, 0.051692, 0.040256", "0.088909, 0.082182, 0.082392, 0.089237, 0.111465", "0.176860, 0.166922, 0.160768, 0.159204, 0.223911", "0.881893, 0.869050, 0.853857, 0.827782, 0.824694" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005563, 0.008612, 0.012339, 0.017358, 0.087849", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.179772, 0.177219, 0.176091, 0.179128, 0.343479", "0.895275, 0.891758, 0.887322, 0.880070, 0.928854" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008037, 0.028704, 0.054668, 0.109521, 0.869966", "0.076055, 0.081921, 0.097573, 0.140257, 0.863906", "0.147843, 0.149496, 0.158979, 0.188238, 0.862306", "0.288563, 0.287255, 0.290237, 0.307382, 0.902900", "1.419778, 1.420153, 1.419732, 1.419717, 1.673889" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008767, 0.031084, 0.058052, 0.115960, 0.868417", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.347603, 0.347624, 0.351003, 0.368838, 0.971602", "1.725267, 1.725008, 1.725609, 1.725893, 1.975591" ); } } } } cell (INVX4) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 164592.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.013438478664617209; direction: input; fall_capacitance: 0.014499779614899311; rise_capacitance: 0.012377177714335106; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.004836, 0.004170, 0.002946, -0.001907, -0.066292", "0.023946, 0.025031, 0.028842, 0.029915, -0.004484", "0.044976, 0.042290, 0.047609, 0.052305, 0.040052", "0.088868, 0.082479, 0.082214, 0.089172, 0.111518", "0.440751, 0.428400, 0.415953, 0.398459, 0.482872" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005423, 0.008336, 0.011970, 0.017170, 0.086980", "0.025140, 0.028622, 0.035186, 0.044099, 0.141159", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.090922, 0.089928, 0.091895, 0.103197, 0.242872", "0.447493, 0.444138, 0.440746, 0.435821, 0.578747" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.007775, 0.028100, 0.055227, 0.108927, 0.869985", "0.039255, 0.049723, 0.072334, 0.124573, 0.866617", "0.075493, 0.083261, 0.096610, 0.140261, 0.863292", "0.146557, 0.148054, 0.158526, 0.188166, 0.862332", "0.712012, 0.711126, 0.711929, 0.712879, 1.131106" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008278, 0.030935, 0.057869, 0.115738, 0.868418", "0.047073, 0.058001, 0.079823, 0.131936, 0.871905", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.176967, 0.177851, 0.188412, 0.219917, 0.899333", "0.863260, 0.862553, 0.864134, 0.865563, 1.291606" ); } } } } cell (INVX8) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 274320.0; cell_leakage_power: 0.1173; pin (A) { capacitance: 0.0252218232768479; direction: input; fall_capacitance: 0.02568994035979349; rise_capacitance: 0.024753706193902308; } pin (Y) { direction: output; function: "(!A)"; timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.004711, 0.004036, 0.002690, -0.002338, -0.066683", "0.013476, 0.015921, 0.017776, 0.016979, -0.030765", "0.023708, 0.025226, 0.028773, 0.029840, -0.004496", "0.044997, 0.042811, 0.047615, 0.051364, 0.040057", "0.220573, 0.210103, 0.201918, 0.196471, 0.273011" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005356, 0.008195, 0.011786, 0.017076, 0.086545", "0.014445, 0.019292, 0.024680, 0.028468, 0.116656", "0.025140, 0.028622, 0.035186, 0.044099, 0.141159", "0.046446, 0.047702, 0.053516, 0.064252, 0.179451", "0.224189, 0.221188, 0.219510, 0.220049, 0.387314" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.007647, 0.027974, 0.055611, 0.108999, 0.869977", "0.022594, 0.037470, 0.063051, 0.115180, 0.867738", "0.039486, 0.049806, 0.072127, 0.121312, 0.866717", "0.076785, 0.082234, 0.096608, 0.138992, 0.863329", "0.358088, 0.358712, 0.359243, 0.372101, 0.930596" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008160, 0.030855, 0.057683, 0.115626, 0.868400", "0.027538, 0.041822, 0.066894, 0.123555, 0.870026", "0.047073, 0.058001, 0.079823, 0.131936, 0.871905", "0.090912, 0.096720, 0.111536, 0.155787, 0.875627", "0.433842, 0.432463, 0.434875, 0.448234, 1.015267" ); } } } } cell (MUX2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 329184.0; cell_leakage_power: 0.1173; pin (S) { capacitance: 0.009256673995156848; direction: input; fall_capacitance: 0.008174605299069488; rise_capacitance: 0.01033874269124421; } pin (B) { capacitance: 0.007621740826129985; direction: input; fall_capacitance: 0.008845710726223829; rise_capacitance: 0.0063977709260361415; } pin (A) { capacitance: 0.006381443680226534; direction: input; fall_capacitance: 0.007825475707159937; rise_capacitance: 0.00493741165329313; } pin (Y) { direction: output; function: "(!(A & B & S + A & B & !S + A & S & !B + B & !A & !S))"; timing () { related_pin: "S"; timing_sense: non_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015477, 0.019600, 0.024190, 0.025747, 0.046287", "0.090314, 0.087100, 0.090495, 0.101960, 0.176908", "0.167236, 0.162506, 0.162337, 0.167647, 0.271944", "0.321537, 0.315074, 0.311756, 0.311149, 0.436391", "1.560714, 1.552503, 1.545002, 1.533689, 1.520599" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.009379, 0.017036, 0.023092, 0.027221, 0.047575", "0.098648, 0.096570, 0.098493, 0.106357, 0.189094", "0.192045, 0.187310, 0.185345, 0.186620, 0.293971", "0.380085, 0.373558, 0.368111, 0.361746, 0.471469", "1.891180, 1.882519, 1.872679, 1.854529, 1.753166" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.025354, 0.032783, 0.050461, 0.087201, 0.566081", "0.133109, 0.134458, 0.135941, 0.157612, 0.603315", "0.244639, 0.245101, 0.245522, 0.253219, 0.662135", "0.469661, 0.469241, 0.469216, 0.469325, 0.758422", "2.271840, 2.271929, 2.271941, 2.271927, 2.283161" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.022515, 0.036555, 0.054175, 0.094241, 0.572428", "0.157940, 0.158368, 0.159664, 0.178650, 0.640716", "0.288080, 0.288326, 0.288348, 0.292800, 0.713717", "0.548431, 0.548597, 0.548599, 0.548675, 0.846377", "2.640854, 2.640882, 2.640837, 2.640903, 2.646773" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012479, 0.020703, 0.023751, 0.026480, -0.020258", "0.088791, 0.092407, 0.096269, 0.106017, 0.140677", "0.166519, 0.167928, 0.170594, 0.176829, 0.252652", "0.321088, 0.321765, 0.322714, 0.325872, 0.431855", "1.560825, 1.560508, 1.559318, 1.557534, 1.590909" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.024075, 0.029303, 0.036113, 0.042909, 0.139365", "0.116212, 0.118239, 0.123057, 0.135164, 0.298599", "0.209808, 0.210879, 0.213787, 0.223211, 0.408707", "0.398464, 0.398636, 0.399777, 0.405563, 0.586820", "1.910071, 1.909315, 1.908318, 1.908149, 1.983973" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.021856, 0.029483, 0.041747, 0.075580, 0.318538", "0.133491, 0.132145, 0.135514, 0.149421, 0.455212", "0.245429, 0.244447, 0.244614, 0.249182, 0.551752", "0.469502, 0.469644, 0.469460, 0.469734, 0.678108", "2.271768, 2.271699, 2.271790, 2.271724, 2.274762" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026927, 0.031637, 0.041603, 0.073132, 0.327601", "0.157522, 0.158503, 0.158749, 0.168029, 0.467796", "0.288182, 0.288023, 0.288247, 0.289518, 0.550457", "0.548628, 0.548713, 0.548726, 0.548715, 0.704382", "2.641050, 2.641120, 2.641079, 2.641124, 2.641113" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019428, 0.021891, 0.024080, 0.024293, -0.020282", "0.097729, 0.098072, 0.099347, 0.107474, 0.140891", "0.174738, 0.174194, 0.175185, 0.179883, 0.252844", "0.329664, 0.328818, 0.328461, 0.330406, 0.432450", "1.569311, 1.568266, 1.566635, 1.564341, 1.594321" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015958, 0.028273, 0.035331, 0.042097, 0.139507", "0.109992, 0.113793, 0.120225, 0.134598, 0.298772", "0.203874, 0.205671, 0.209819, 0.221705, 0.408455", "0.392495, 0.393164, 0.395366, 0.402419, 0.586497", "1.904233, 1.903472, 1.903098, 1.903613, 1.981673" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020684, 0.027469, 0.040684, 0.075372, 0.321139", "0.131690, 0.132092, 0.134409, 0.147611, 0.454546", "0.244572, 0.244857, 0.245585, 0.248273, 0.551845", "0.469953, 0.470028, 0.469684, 0.470070, 0.677392", "2.272005, 2.271976, 2.272124, 2.272035, 2.274938" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.034906, 0.034011, 0.041604, 0.074407, 0.329883", "0.157071, 0.157736, 0.156957, 0.168367, 0.468419", "0.288086, 0.287766, 0.287721, 0.290181, 0.550707", "0.548081, 0.548418, 0.548486, 0.548470, 0.704390", "2.640667, 2.640718, 2.640731, 2.640752, 2.640649" ); } } } } cell (NAND2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 164592.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.00495623189256475; direction: input; fall_capacitance: 0.005761587126333127; rise_capacitance: 0.004150876658796372; } pin (A) { capacitance: 0.00639318508707538; direction: input; fall_capacitance: 0.007850955022359487; rise_capacitance: 0.004935415151791272; } pin (Y) { direction: output; function: "(!A & B)"; timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005849, 0.004437, 0.002225, -0.008486, -0.130057", "0.046388, 0.043249, 0.046999, 0.048115, -0.018501", "0.090291, 0.082811, 0.082216, 0.086712, 0.056313", "0.178331, 0.167829, 0.160916, 0.157445, 0.175397", "0.883390, 0.870337, 0.854738, 0.827352, 0.802406" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013792, 0.016361, 0.025056, 0.033074, 0.175602", "0.108490, 0.103780, 0.105147, 0.117790, 0.315278", "0.202467, 0.196392, 0.193875, 0.197687, 0.411516", "0.391201, 0.384138, 0.378135, 0.373850, 0.567320", "1.903046, 1.894605, 1.884531, 1.867051, 1.824897" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.009695, 0.029312, 0.048608, 0.093281, 0.629805", "0.078056, 0.082987, 0.099284, 0.142653, 0.690195", "0.150388, 0.151272, 0.161350, 0.191067, 0.765186", "0.290688, 0.289222, 0.292426, 0.310086, 0.876476", "1.422106, 1.422288, 1.421889, 1.421871, 1.682533" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.014730, 0.023408, 0.040311, 0.078487, 0.617549", "0.143671, 0.145673, 0.147214, 0.163072, 0.604300", "0.274318, 0.273786, 0.274511, 0.279238, 0.636700", "0.534800, 0.535162, 0.534899, 0.535215, 0.783182", "2.627058, 2.627242, 2.627155, 2.627074, 2.630378" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.007196, 0.006952, 0.007019, 0.002025, -0.085579", "0.048073, 0.045085, 0.049525, 0.053219, 0.022142", "0.092047, 0.084523, 0.084238, 0.090031, 0.092503", "0.180017, 0.169497, 0.162833, 0.159983, 0.207124", "0.885060, 0.872012, 0.856446, 0.829185, 0.814262" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015633, 0.021506, 0.028394, 0.039572, 0.149899", "0.108272, 0.110667, 0.117688, 0.132659, 0.322650", "0.202415, 0.203429, 0.208041, 0.220813, 0.436827", "0.390997, 0.391221, 0.393703, 0.402725, 0.616168", "1.902658, 1.901593, 1.901395, 1.902809, 2.012938" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012945, 0.031804, 0.051562, 0.097848, 0.530404", "0.082605, 0.085877, 0.102513, 0.146986, 0.675477", "0.153507, 0.154155, 0.164693, 0.195301, 0.762310", "0.293780, 0.292627, 0.295499, 0.313420, 0.886530", "1.425247, 1.425396, 1.425085, 1.425078, 1.692913" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.014326, 0.019054, 0.029916, 0.064625, 0.487291", "0.145515, 0.145739, 0.144059, 0.152642, 0.440611", "0.274715, 0.273489, 0.274007, 0.274498, 0.467583", "0.534478, 0.535194, 0.535121, 0.535184, 0.639625", "2.627046, 2.627208, 2.627161, 2.627179, 2.627235" ); } } } } cell (NAND3X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (C) { capacitance: 0.0049475602037443766; direction: input; fall_capacitance: 0.00574550349282349; rise_capacitance: 0.004149616914665264; } pin (B) { capacitance: 0.0056720092179016355; direction: input; fall_capacitance: 0.006513434336879236; rise_capacitance: 0.0048305840989240345; } pin (A) { capacitance: 0.00639281784839878; direction: input; fall_capacitance: 0.00785033270340369; rise_capacitance: 0.0049353029933938706; } pin (Y) { direction: output; function: "(!A & B & C)"; timing () { related_pin: "C"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.006743, 0.005016, 0.001565, -0.011749, -0.174318", "0.047706, 0.044014, 0.046942, 0.046061, -0.062176", "0.091627, 0.083788, 0.082464, 0.085303, 0.015523", "0.179686, 0.168911, 0.161469, 0.156671, 0.140314", "0.884745, 0.871646, 0.855834, 0.827730, 0.787692" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.021450, 0.026780, 0.036138, 0.051156, 0.240752", "0.141321, 0.138431, 0.140867, 0.154160, 0.407189", "0.261734, 0.256641, 0.255261, 0.261805, 0.519595", "0.501953, 0.495945, 0.491598, 0.490071, 0.706700", "2.425213, 2.418226, 2.409901, 2.395913, 2.391369" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011465, 0.029932, 0.047360, 0.089549, 0.523956", "0.080202, 0.084521, 0.100586, 0.143486, 0.643649", "0.152614, 0.153064, 0.163285, 0.192620, 0.727829", "0.292789, 0.291706, 0.294483, 0.312038, 0.856442", "1.424319, 1.424428, 1.424111, 1.424077, 1.684916" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023400, 0.030385, 0.036793, 0.077633, 0.501790", "0.190321, 0.189918, 0.190315, 0.199221, 0.487718", "0.356855, 0.356030, 0.356029, 0.356551, 0.562588", "0.690022, 0.690543, 0.690506, 0.690555, 0.811600", "3.365843, 3.365797, 3.365863, 3.365868, 3.365810" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008334, 0.007216, 0.005700, -0.003192, -0.138009", "0.049525, 0.045812, 0.049273, 0.049818, -0.030773", "0.093522, 0.085734, 0.084386, 0.088138, 0.042191", "0.181477, 0.170617, 0.163356, 0.158916, 0.163222", "0.886560, 0.873387, 0.857606, 0.829593, 0.796379" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023842, 0.028921, 0.038612, 0.052716, 0.222042", "0.141887, 0.143909, 0.149119, 0.164220, 0.404600", "0.261324, 0.261760, 0.265215, 0.276500, 0.527421", "0.501628, 0.500687, 0.501928, 0.509042, 0.732336", "2.424686, 2.422462, 2.420742, 2.419460, 2.508042" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.014708, 0.032599, 0.052399, 0.096681, 0.513554", "0.084340, 0.087175, 0.104373, 0.147370, 0.652229", "0.155755, 0.155756, 0.166557, 0.196533, 0.737741", "0.295954, 0.295123, 0.297528, 0.315324, 0.869188", "1.427488, 1.427517, 1.427300, 1.427279, 1.694092" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023791, 0.028479, 0.033736, 0.068750, 0.456314", "0.190317, 0.190047, 0.189241, 0.193568, 0.414810", "0.356056, 0.356011, 0.356369, 0.355755, 0.487881", "0.690508, 0.690541, 0.690522, 0.690519, 0.753026", "3.365855, 3.365789, 3.365799, 3.365867, 3.365823" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008972, 0.008268, 0.008643, 0.001970, -0.101488", "0.051257, 0.047583, 0.051333, 0.053538, -0.001472", "0.095356, 0.087565, 0.086323, 0.091056, 0.070441", "0.183312, 0.172348, 0.165227, 0.161181, 0.187191", "0.888366, 0.875180, 0.859388, 0.831456, 0.805980" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020795, 0.029793, 0.038560, 0.050262, 0.188785", "0.138390, 0.142029, 0.147535, 0.160844, 0.367966", "0.257617, 0.259067, 0.261812, 0.272019, 0.491794", "0.497805, 0.497186, 0.497402, 0.502803, 0.696298", "2.420816, 2.418080, 2.414398, 2.409953, 2.462120" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017292, 0.034566, 0.057624, 0.100464, 0.554013", "0.086449, 0.091297, 0.109325, 0.151351, 0.684952", "0.158837, 0.158653, 0.169957, 0.201757, 0.763039", "0.298884, 0.298357, 0.300621, 0.319480, 0.888696", "1.430569, 1.430607, 1.430474, 1.430460, 1.704460" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.024001, 0.027232, 0.035786, 0.067592, 0.495578", "0.190876, 0.191071, 0.189818, 0.194805, 0.453280", "0.356122, 0.356782, 0.355698, 0.356058, 0.506856", "0.690537, 0.690105, 0.690542, 0.690408, 0.762544", "3.365836, 3.365860, 3.365857, 3.365836, 3.365849" ); } } } } cell (NOR2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 164592.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.006303448359239213; direction: input; fall_capacitance: 0.006299461029458945; rise_capacitance: 0.0063074356890194805; } pin (A) { capacitance: 0.007595806558045583; direction: input; fall_capacitance: 0.008891411713164614; rise_capacitance: 0.0063002014029265516; } pin (Y) { direction: output; function: "(!A & !B)"; timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011806, 0.013869, 0.017728, 0.018913, 0.043152", "0.090701, 0.085913, 0.088689, 0.100157, 0.196930", "0.168953, 0.162029, 0.161187, 0.166322, 0.300875", "0.323595, 0.315317, 0.311154, 0.310040, 0.465699", "1.563273, 1.553700, 1.544833, 1.531939, 1.541900" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.005936, 0.007846, 0.008974, 0.004744, -0.003026", "0.046711, 0.047264, 0.052185, 0.058295, 0.096068", "0.091147, 0.089514, 0.090542, 0.098390, 0.165025", "0.180055, 0.176882, 0.175000, 0.175107, 0.275546", "0.895253, 0.891498, 0.886774, 0.878409, 0.897352" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011999, 0.022379, 0.043415, 0.084297, 0.702241", "0.125846, 0.126296, 0.129026, 0.143562, 0.670887", "0.236273, 0.236852, 0.235333, 0.245157, 0.662164", "0.460758, 0.460362, 0.461218, 0.460426, 0.741521", "2.263379, 2.263387, 2.263261, 2.263270, 2.274816" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011676, 0.032976, 0.056268, 0.109537, 0.710905", "0.092517, 0.100885, 0.113823, 0.157999, 0.799871", "0.178759, 0.179128, 0.190132, 0.222605, 0.875172", "0.349115, 0.349295, 0.352632, 0.369786, 0.981780", "1.725874, 1.726029, 1.727042, 1.726377, 1.981658" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012986, 0.016763, 0.019649, 0.026720, -0.007723", "0.091508, 0.092784, 0.095177, 0.106380, 0.166698", "0.168932, 0.168743, 0.171095, 0.177886, 0.281195", "0.323606, 0.323192, 0.323918, 0.327812, 0.460072", "1.563504, 1.562605, 1.561243, 1.560037, 1.617792" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.008571, 0.012259, 0.016219, 0.019628, 0.069884", "0.050623, 0.051267, 0.056425, 0.066606, 0.159854", "0.095165, 0.093119, 0.094604, 0.103938, 0.223425", "0.183791, 0.180470, 0.178804, 0.179941, 0.324263", "0.898914, 0.895013, 0.890412, 0.882094, 0.915185" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011911, 0.020658, 0.034736, 0.070430, 0.635528", "0.125379, 0.123991, 0.127246, 0.137364, 0.573702", "0.237050, 0.236795, 0.237035, 0.239467, 0.551121", "0.461112, 0.461207, 0.460365, 0.461268, 0.627986", "2.263335, 2.263310, 2.263383, 2.263356, 2.265017" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019230, 0.039782, 0.064283, 0.115340, 0.682539", "0.099372, 0.109056, 0.124310, 0.167393, 0.824099", "0.186034, 0.187618, 0.197839, 0.231703, 0.904179", "0.357146, 0.356648, 0.360384, 0.378918, 1.012930", "1.733504, 1.733696, 1.734753, 1.734098, 2.001564" ); } } } } cell (OAI21X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (C) { capacitance: 0.0049685503383930275; direction: input; fall_capacitance: 0.0057337054132807755; rise_capacitance: 0.004203395263505281; } pin (B) { capacitance: 0.004817269329420684; direction: input; fall_capacitance: 0.0046993715663027884; rise_capacitance: 0.004935167092538579; } pin (A) { capacitance: 0.006365887451121313; direction: input; fall_capacitance: 0.007796116485619777; rise_capacitance: 0.004935658416622851; } pin (Y) { direction: output; function: "(!(A & B & C + A & C & !B + B & C & !A))"; timing () { related_pin: "C"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.006353, 0.006873, 0.004977, -0.002571, -0.112220", "0.047648, 0.044522, 0.048480, 0.050680, -0.005504", "0.091575, 0.084317, 0.083496, 0.088598, 0.067928", "0.179609, 0.168970, 0.162303, 0.158976, 0.185631", "0.884619, 0.871536, 0.855984, 0.828850, 0.807127" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012322, 0.018627, 0.025819, 0.036380, 0.166985", "0.097230, 0.095251, 0.097606, 0.110133, 0.295266", "0.182685, 0.178288, 0.176909, 0.181932, 0.384599", "0.354450, 0.348364, 0.343303, 0.339898, 0.530677", "1.731053, 1.722975, 1.713352, 1.696916, 1.662491" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011924, 0.030898, 0.053284, 0.100971, 0.670100", "0.080583, 0.085685, 0.102082, 0.143609, 0.716365", "0.152800, 0.152883, 0.163222, 0.193150, 0.778215", "0.292893, 0.292086, 0.294393, 0.311669, 0.881950", "1.424263, 1.424245, 1.424087, 1.424045, 1.683357" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017139, 0.026739, 0.044276, 0.087758, 0.660076", "0.138283, 0.139729, 0.142997, 0.162743, 0.650333", "0.260560, 0.259671, 0.260078, 0.269467, 0.681289", "0.503775, 0.503479, 0.503665, 0.504685, 0.808692", "2.459384, 2.459439, 2.459425, 2.459497, 2.482154" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018084, 0.018785, 0.021524, 0.021254, 0.031017", "0.096634, 0.090653, 0.091567, 0.101191, 0.181020", "0.173780, 0.166489, 0.164402, 0.167176, 0.281781", "0.328645, 0.320024, 0.314801, 0.311087, 0.444609", "1.568475, 1.558747, 1.549393, 1.535231, 1.517075" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011853, 0.020828, 0.025802, 0.032296, 0.061131", "0.103764, 0.107281, 0.113180, 0.125736, 0.245046", "0.197462, 0.198933, 0.202960, 0.213251, 0.366132", "0.386134, 0.386285, 0.388197, 0.395136, 0.557258", "1.897752, 1.896544, 1.895986, 1.896513, 1.969418" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.020867, 0.029939, 0.052329, 0.091938, 0.451438", "0.133406, 0.133983, 0.137806, 0.156667, 0.613530", "0.245013, 0.245383, 0.244613, 0.254696, 0.705512", "0.469706, 0.469327, 0.469422, 0.469157, 0.813809", "2.271618, 2.271785, 2.271663, 2.271774, 2.288526" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015697, 0.022510, 0.033468, 0.066107, 0.425032", "0.144870, 0.144572, 0.145000, 0.157604, 0.462980", "0.274162, 0.274051, 0.273949, 0.276993, 0.536593", "0.535317, 0.535340, 0.535460, 0.535384, 0.689730", "2.627338, 2.627345, 2.627342, 2.627355, 2.627455" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018803, 0.021401, 0.023344, 0.023872, -0.022124", "0.097043, 0.097462, 0.098807, 0.107122, 0.140271", "0.174167, 0.173694, 0.174835, 0.179375, 0.252462", "0.329045, 0.328268, 0.328060, 0.330094, 0.432085", "1.568689, 1.567669, 1.566082, 1.563994, 1.593864" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.014567, 0.027648, 0.035349, 0.041047, 0.137832", "0.108453, 0.112569, 0.119206, 0.133016, 0.297203", "0.202396, 0.204223, 0.208700, 0.219958, 0.407822", "0.391026, 0.391383, 0.393600, 0.400955, 0.585908", "1.902735, 1.901651, 1.901085, 1.901740, 1.980348" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019300, 0.027658, 0.041698, 0.074827, 0.320959", "0.131626, 0.131992, 0.134734, 0.149048, 0.454028", "0.244112, 0.244371, 0.245398, 0.247897, 0.550953", "0.469602, 0.469661, 0.469275, 0.469732, 0.677618", "2.271672, 2.271613, 2.271813, 2.271710, 2.274668" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.031706, 0.032612, 0.040602, 0.073394, 0.328383", "0.155420, 0.155629, 0.156550, 0.167050, 0.465518", "0.286331, 0.286147, 0.286318, 0.287490, 0.548717", "0.546344, 0.546313, 0.546743, 0.546937, 0.703383", "2.638909, 2.638879, 2.638882, 2.638975, 2.638890" ); } } } } cell (OAI22X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 274320.0; cell_leakage_power: 0.1173; pin (D) { capacitance: 0.0021453532257938264; direction: input; fall_capacitance: 6.164254229978021e-05; rise_capacitance: 0.004229063909287872; } pin (C) { capacitance: 0.004976915596377423; direction: input; fall_capacitance: 0.0057238940867746484; rise_capacitance: 0.004229937105980198; } pin (B) { capacitance: 0.004810999172966173; direction: input; fall_capacitance: 0.004686782002117296; rise_capacitance: 0.00493521634381505; } pin (A) { capacitance: 0.006365536753506552; direction: input; fall_capacitance: 0.007795205171653458; rise_capacitance: 0.004935868335359646; } pin (Y) { direction: output; function: "((A & B & !C & !D + C & D & !A & !B + A & !B & !C & !D + B & !A & !C & !D + C & !A & !B & !D + D & !A & !B & !C + !A & !B & !C & !D))"; timing () { related_pin: "D"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.016262, 0.017741, 0.020452, 0.019420, -0.001499", "0.095678, 0.090075, 0.091093, 0.099982, 0.152775", "0.173776, 0.166259, 0.163962, 0.166726, 0.258406", "0.328418, 0.319872, 0.314598, 0.311147, 0.428538", "1.568201, 1.558608, 1.549384, 1.535559, 1.515136" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.011023, 0.018232, 0.023273, 0.028038, 0.082251", "0.094341, 0.092670, 0.094113, 0.103646, 0.217383", "0.179868, 0.175244, 0.173130, 0.174945, 0.311623", "0.351607, 0.345183, 0.339617, 0.333200, 0.467646", "1.728098, 1.719804, 1.710141, 1.692568, 1.611799" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.018975, 0.028562, 0.049415, 0.089237, 0.641577", "0.132997, 0.132685, 0.135462, 0.153560, 0.651633", "0.243979, 0.244016, 0.242906, 0.252668, 0.698762", "0.467681, 0.467640, 0.468098, 0.467574, 0.795527", "2.270165, 2.270194, 2.270075, 2.270158, 2.286886" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019197, 0.039255, 0.052110, 0.097009, 0.642401", "0.140956, 0.141396, 0.146191, 0.171523, 0.712509", "0.262540, 0.262555, 0.262471, 0.273651, 0.778925", "0.505956, 0.505722, 0.505888, 0.507033, 0.894213", "2.461475, 2.461430, 2.461494, 2.461469, 2.493082" ); } } timing () { related_pin: "C"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.017359, 0.020602, 0.022466, 0.024654, -0.046754", "0.096705, 0.096946, 0.098584, 0.106282, 0.121532", "0.173777, 0.173577, 0.174431, 0.178939, 0.237315", "0.328617, 0.328111, 0.327825, 0.329774, 0.421297", "1.568418, 1.567576, 1.565970, 1.563848, 1.593553" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.015022, 0.024347, 0.031623, 0.040631, 0.158538", "0.099036, 0.097739, 0.100219, 0.111280, 0.279679", "0.184670, 0.180259, 0.178658, 0.181740, 0.365006", "0.356322, 0.350056, 0.344803, 0.339143, 0.507264", "1.732880, 1.724663, 1.714991, 1.697579, 1.627329" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.019084, 0.026776, 0.039823, 0.075672, 0.535237", "0.131377, 0.131261, 0.132692, 0.145125, 0.516016", "0.243564, 0.243531, 0.243534, 0.246588, 0.558890", "0.468225, 0.468179, 0.468042, 0.468205, 0.664320", "2.270088, 2.270095, 2.270133, 2.270106, 2.272980" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.031510, 0.049989, 0.062355, 0.106040, 0.586348", "0.151694, 0.152790, 0.156527, 0.182644, 0.731793", "0.273221, 0.273269, 0.273901, 0.284371, 0.805125", "0.516486, 0.516519, 0.516581, 0.517538, 0.918731", "2.472286, 2.472287, 2.472233, 2.472242, 2.503889" ); } } timing () { related_pin: "B"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.022460, 0.023823, 0.028185, 0.032725, 0.048628", "0.101758, 0.095743, 0.096537, 0.106002, 0.192478", "0.178737, 0.171298, 0.169438, 0.172294, 0.292379", "0.333714, 0.324980, 0.319961, 0.316508, 0.454253", "1.573522, 1.563797, 1.554566, 1.540634, 1.526335" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.009970, 0.022403, 0.029546, 0.034700, 0.068167", "0.096913, 0.101219, 0.107825, 0.121609, 0.232622", "0.185623, 0.187325, 0.191482, 0.202034, 0.347414", "0.363642, 0.363571, 0.365553, 0.371659, 0.531408", "1.789848, 1.787982, 1.786798, 1.785978, 1.851027" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.027669, 0.035784, 0.054151, 0.092799, 0.482183", "0.140384, 0.141035, 0.144045, 0.162603, 0.615320", "0.251926, 0.252443, 0.252459, 0.260421, 0.699195", "0.477068, 0.477037, 0.476614, 0.476926, 0.805486", "2.279001, 2.279001, 2.279030, 2.279108, 2.294719" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026136, 0.039819, 0.039716, 0.074663, 0.449468", "0.141886, 0.142241, 0.143245, 0.158332, 0.500963", "0.262746, 0.262952, 0.263172, 0.266752, 0.568096", "0.505553, 0.505524, 0.505320, 0.505778, 0.700928", "2.453307, 2.453357, 2.453377, 2.453355, 2.454709" ); } } timing () { related_pin: "A"; timing_sense: negative_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.023283, 0.026391, 0.030097, 0.032328, -0.001253", "0.101980, 0.102170, 0.104068, 0.112129, 0.154938", "0.179362, 0.178895, 0.179701, 0.184772, 0.265473", "0.334131, 0.333374, 0.333035, 0.335245, 0.443256", "1.573764, 1.572736, 1.571134, 1.569023, 1.603107" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.012521, 0.028199, 0.037706, 0.047850, 0.141476", "0.101182, 0.106075, 0.113456, 0.128856, 0.286674", "0.190018, 0.192261, 0.196376, 0.207802, 0.390952", "0.368057, 0.368351, 0.370519, 0.377256, 0.561629", "1.794406, 1.792708, 1.791509, 1.790815, 1.862031" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.027862, 0.033354, 0.044936, 0.077255, 0.353604", "0.140814, 0.140720, 0.141271, 0.155440, 0.462296", "0.251891, 0.251950, 0.252170, 0.254649, 0.552226", "0.476737, 0.476901, 0.476974, 0.476945, 0.673929", "2.279056, 2.278996, 2.279039, 2.278966, 2.281603" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.033370, 0.057996, 0.048428, 0.083327, 0.382049", "0.151938, 0.153699, 0.154923, 0.169228, 0.507796", "0.273900, 0.273102, 0.273602, 0.276988, 0.582041", "0.516030, 0.516117, 0.516125, 0.516348, 0.713735", "2.464090, 2.464052, 2.464047, 2.464139, 2.465296" ); } } } } cell (OR2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 219456.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.007576401997672222; direction: input; fall_capacitance: 0.008853042755779209; rise_capacitance: 0.006299761239565236; } pin (A) { capacitance: 0.006280956134443613; direction: input; fall_capacitance: 0.006252202564509515; rise_capacitance: 0.006309709704377711; } pin (Y) { direction: output; function: "(!!A & !B)"; timing () { related_pin: "B"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002737, 0.013249, 0.024740, 0.030135, 0.058150", "0.042967, 0.048920, 0.058700, 0.066027, 0.128620", "0.085691, 0.083076, 0.088849, 0.098329, 0.169802", "0.172823, 0.161427, 0.160431, 0.161812, 0.229754", "0.876988, 0.854756, 0.839524, 0.814610, 0.732242" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.029512, 0.033910, 0.037914, 0.050330, 0.052929", "0.070267, 0.072997, 0.078009, 0.091347, 0.135739", "0.112746, 0.114735, 0.118673, 0.130593, 0.209389", "0.200112, 0.201924, 0.204703, 0.213815, 0.340853", "0.914821, 0.916103, 0.917764, 0.922353, 1.006921" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.016092, 0.057938, 0.095965, 0.165885, 0.705458", "0.078905, 0.104180, 0.138126, 0.202710, 0.704503", "0.148545, 0.161533, 0.188973, 0.232451, 0.725913", "0.289045, 0.288648, 0.297219, 0.323752, 0.788330", "1.420575, 1.420547, 1.420296, 1.420209, 1.575305" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.024665, 0.028188, 0.037838, 0.067587, 0.608216", "0.097377, 0.097071, 0.100693, 0.117571, 0.616589", "0.178290, 0.178809, 0.181589, 0.191054, 0.624945", "0.348706, 0.349016, 0.349686, 0.352764, 0.697194", "1.725555, 1.725371, 1.726655, 1.725685, 1.854607" ); } } timing () { related_pin: "A"; timing_sense: positive_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "-0.002786, -0.022525, 0.019015, 0.011670, -0.014214", "0.041859, 0.043298, 0.052130, 0.057857, 0.058886", "0.085034, 0.078556, 0.083166, 0.090278, 0.102558", "0.172887, 0.158458, 0.155718, 0.154087, 0.173297", "0.877505, 0.854378, 0.837626, 0.810046, 0.720442" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.028690, 0.031248, 0.037463, 0.044487, 0.100482", "0.069107, 0.069828, 0.076360, 0.091636, 0.185145", "0.112034, 0.111088, 0.115798, 0.129197, 0.254233", "0.199087, 0.197989, 0.201090, 0.209121, 0.374419", "0.914050, 0.911951, 0.913051, 0.915105, 1.007909" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013392, 0.052206, 0.087689, 0.154666, 0.691395", "0.076707, 0.097805, 0.133251, 0.196593, 0.689662", "0.148818, 0.159357, 0.181649, 0.221635, 0.720108", "0.288045, 0.289252, 0.294522, 0.318177, 0.791961", "1.420335, 1.420191, 1.420219, 1.420439, 1.583354" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.024973, 0.029481, 0.044119, 0.082711, 0.664635", "0.097225, 0.099096, 0.107079, 0.133341, 0.664451", "0.179958, 0.178788, 0.182955, 0.202839, 0.677564", "0.347947, 0.348719, 0.349929, 0.358002, 0.742083", "1.725186, 1.725383, 1.725427, 1.725691, 1.862987" ); } } } } cell (XNOR2X1) { pg_pin (vdd) { voltage_name : "vdd"; pg_type : "primary_power"; } pg_pin (gnd) { voltage_name : "gnd"; pg_type : "primary_ground"; } area: 384048.0; cell_leakage_power: 0.1173; pin (B) { capacitance: 0.013514822660098; direction: input; fall_capacitance: 0.01444352653236194; rise_capacitance: 0.012586118787834062; } pin (A) { capacitance: 0.01216821188263561; direction: input; fall_capacitance: 0.01160051626672843; rise_capacitance: 0.01273590749854279; } pin (Y) { direction: output; function: "(!(A & !B + B & !A))"; timing () { related_pin: "B"; timing_sense: non_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.016692, 0.026466, 0.032210, 0.035327, 0.047236", "0.091623, 0.096157, 0.101268, 0.112236, 0.182896", "0.168714, 0.171487, 0.175299, 0.184006, 0.283106", "0.323178, 0.324836, 0.326819, 0.332014, 0.455088", "1.562758, 1.563072, 1.562761, 1.562230, 1.609484" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.026885, 0.032485, 0.038933, 0.047083, 0.088356", "0.117931, 0.120641, 0.124872, 0.135278, 0.246294", "0.211363, 0.213025, 0.215480, 0.223412, 0.363623", "0.399691, 0.400466, 0.401437, 0.406163, 0.555052", "1.911060, 1.910782, 1.909790, 1.909219, 1.963747" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.025286, 0.030976, 0.039578, 0.069148, 0.271887", "0.132863, 0.133148, 0.134699, 0.146335, 0.398431", "0.245392, 0.244781, 0.245027, 0.248852, 0.500046", "0.469752, 0.469734, 0.469539, 0.469707, 0.636982", "2.271914, 2.271860, 2.271907, 2.271883, 2.273532" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.028424, 0.032113, 0.039714, 0.069558, 0.259508", "0.158149, 0.158097, 0.158297, 0.165758, 0.432914", "0.288248, 0.287926, 0.287602, 0.288201, 0.539323", "0.548453, 0.548729, 0.548771, 0.548859, 0.704675", "2.640916, 2.640957, 2.640961, 2.640975, 2.640935" ); } } timing () { related_pin: "A"; timing_sense: non_unate; cell_rise (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013989, 0.017922, 0.023819, 0.023910, 0.045077", "0.087124, 0.084574, 0.088506, 0.101490, 0.176795", "0.164482, 0.158794, 0.159586, 0.166358, 0.271935", "0.318605, 0.311099, 0.308187, 0.308499, 0.436242", "1.557737, 1.548082, 1.540255, 1.529227, 1.518552" ); } cell_fall (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.013397, 0.017881, 0.023473, 0.028401, 0.048333", "0.105060, 0.099768, 0.099684, 0.107137, 0.189063", "0.198273, 0.190917, 0.187291, 0.187394, 0.294003", "0.386416, 0.377286, 0.370618, 0.362674, 0.471656", "1.897499, 1.886493, 1.875774, 1.856923, 1.754103" ); } rise_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.024118, 0.038502, 0.063416, 0.087635, 0.566949", "0.133840, 0.133055, 0.136674, 0.159516, 0.603141", "0.245168, 0.244344, 0.245288, 0.252595, 0.662450", "0.469128, 0.469774, 0.469389, 0.469661, 0.759403", "2.272025, 2.271869, 2.271945, 2.272010, 2.283692" ); } fall_transition (delay_template_5x5) { index_1 ( "0.000500, 0.050000, 0.100000, 0.200000, 1.000000" ); index_2 ( "0.010000, 0.050000, 0.100000, 0.200000, 1.500000" ); values ( "0.025980, 0.033978, 0.052062, 0.093692, 0.572048", "0.158104, 0.158727, 0.159581, 0.178242, 0.640536", "0.287711, 0.288211, 0.287992, 0.293228, 0.713557", "0.548627, 0.548574, 0.548857, 0.548865, 0.845995", "2.640933, 2.640942, 2.640979, 2.640983, 2.646792" ); } } } }}
\ No newline at end of file
diff --git a/cells/mag/AND2X1.mag b/cells/mag/AND2X1.mag
index 31270cf..f2c642a 100644
--- a/cells/mag/AND2X1.mag
+++ b/cells/mag/AND2X1.mag
@@ -1,156 +1,270 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621171374
+timestamp 1623602809
<< nwell >>
rect 0 179 576 333
-rect 27 333 550 340
-<< viali >>
-rect 328 19 345 36
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-rect 88 46 105 63
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-<< poly >>
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-<< properties >>
-string FIXED_BBOX 0 0 576 333
-<< li1 >>
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-<< met1 >>
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-rect 0 309 576 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
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-rect 0 309 576 357
-<< ndiffusion >>
-rect 202 13 255 24
-rect 322 13 375 24
-rect 58 24 519 66
+<< nmos >>
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+<< pmos >>
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+<< ndiff >>
rect 82 66 111 69
rect 466 66 495 69
-<< pdiffusion >>
-rect 178 215 207 225
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-rect 58 225 519 309
+rect 58 63 137 66
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rect 58 309 87 312
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+<< pdiffc >>
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+<< poly >>
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<< polycont >>
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rect 136 181 153 198
rect 280 181 297 198
rect 424 181 441 198
-<< pdiffc >>
-rect 184 221 201 238
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+<< viali >>
rect 64 289 81 306
rect 328 289 345 306
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-<< ndiffc >>
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-rect 352 19 369 36
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rect 88 46 105 63
rect 472 46 489 63
-<< nplus >>
-<< pplus >>
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+<< metal1 >>
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+rect 0 -24 576 19
<< labels >>
-rlabel met1 0 309 576 357 0 VDD
+rlabel metal1 0 309 576 357 0 VDD
port 1 se
-rlabel met1 0 -24 576 24 0 GND
+rlabel metal1 0 -24 576 24 0 GND
port 2 se
-rlabel met1 466 40 495 69 0 Y
+rlabel metal1 466 40 495 69 0 Y
port 3 se
-rlabel met1 473 69 487 215 0 Y
+rlabel metal1 473 69 487 215 0 Y
port 4 se
-rlabel met1 466 215 495 244 0 Y
+rlabel metal1 466 215 495 244 0 Y
port 5 se
-rlabel met1 130 80 159 109 0 A
+rlabel metal1 274 80 303 109 0 B
port 6 se
-rlabel met1 137 109 151 175 0 A
+rlabel metal1 281 109 295 175 0 B
port 7 se
-rlabel met1 130 175 159 204 0 A
+rlabel metal1 274 175 303 204 0 B
port 8 se
-rlabel met1 274 80 303 109 0 B
+rlabel metal1 130 80 159 109 0 A
port 9 se
-rlabel met1 281 109 295 175 0 B
+rlabel metal1 137 109 151 175 0 A
port 10 se
-rlabel met1 274 175 303 204 0 B
+rlabel metal1 130 175 159 204 0 A
port 11 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/AND2X2.mag b/cells/mag/AND2X2.mag
index 8e5ff77..b915062 100644
--- a/cells/mag/AND2X2.mag
+++ b/cells/mag/AND2X2.mag
@@ -1,158 +1,270 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621171631
+timestamp 1623602813
<< nwell >>
rect 0 179 576 333
-rect 27 333 550 340
-<< viali >>
-rect 328 19 345 36
-rect 376 19 393 36
-rect 88 46 105 63
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-rect 64 289 81 306
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-<< poly >>
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-rect 416 78 449 111
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-rect 137 206 152 330
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-rect 416 173 449 206
-rect 425 206 440 330
-<< properties >>
-string FIXED_BBOX 0 0 576 333
-<< li1 >>
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-rect 368 11 401 44
-rect 80 38 113 71
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-rect 176 213 233 246
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-rect 56 281 89 314
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-<< met1 >>
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-rect 0 309 576 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 576 24
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-rect 274 175 303 204
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-rect 466 215 495 244
-rect 0 309 576 357
-<< ndiffusion >>
-rect 178 13 231 24
-rect 322 13 351 24
-rect 370 13 399 24
-rect 58 24 519 66
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+<< ndiff >>
rect 82 66 111 69
rect 466 66 495 69
-<< pdiffusion >>
-rect 178 215 231 225
-rect 466 215 495 225
-rect 58 225 519 309
+rect 58 63 137 66
+rect 58 46 88 63
+rect 105 46 137 63
+rect 58 24 137 46
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+rect 345 24 425 36
+rect 440 63 519 66
+rect 440 46 472 63
+rect 489 46 519 63
+rect 440 24 519 46
+rect 345 19 351 24
+rect 322 13 351 19
+<< pdiff >>
rect 58 309 87 312
rect 322 309 351 312
-rect 370 309 399 312
+rect 58 306 137 309
+rect 58 289 64 306
+rect 81 289 137 306
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+rect 152 238 281 309
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+rect 296 225 425 289
+rect 440 238 519 309
+rect 440 225 472 238
+rect 201 221 207 225
+rect 178 215 207 221
+rect 466 221 472 225
+rect 489 225 519 238
+rect 489 221 495 225
+rect 466 215 495 221
+<< ndiffc >>
+rect 88 46 105 63
+rect 328 19 345 36
+rect 472 46 489 63
+<< pdiffc >>
+rect 64 289 81 306
+rect 184 221 201 238
+rect 328 289 345 306
+rect 472 221 489 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 425 206 440 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 425 66 440 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
rect 136 181 153 198
rect 280 181 297 198
rect 424 181 441 198
-<< pdiffc >>
-rect 184 221 201 238
-rect 208 221 225 238
-rect 472 221 489 238
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+<< locali >>
+rect 56 306 89 314
+rect 56 289 64 306
+rect 81 289 89 306
+rect 56 281 89 289
+rect 320 306 353 314
+rect 320 289 328 306
+rect 345 289 353 306
+rect 320 281 353 289
+rect 176 238 209 246
+rect 176 223 184 238
+rect 178 221 184 223
+rect 201 221 209 238
+rect 464 238 497 246
+rect 464 223 472 238
+rect 178 213 209 221
+rect 466 221 472 223
+rect 489 221 497 238
+rect 466 213 497 221
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 128 103 161 111
+rect 128 88 136 103
+rect 130 86 136 88
+rect 153 86 161 103
+rect 130 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 80 63 113 71
+rect 80 46 88 63
+rect 105 46 113 63
+rect 466 63 497 71
+rect 466 61 472 63
+rect 80 38 113 46
+rect 464 46 472 61
+rect 489 46 497 63
+rect 320 36 353 44
+rect 464 38 497 46
+rect 320 19 328 36
+rect 345 19 353 36
+rect 320 11 353 19
+<< viali >>
rect 64 289 81 306
rect 328 289 345 306
-rect 376 289 393 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 208 19 225 36
-rect 328 19 345 36
-rect 376 19 393 36
+rect 184 221 201 238
+rect 472 221 489 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
rect 88 46 105 63
rect 472 46 489 63
-<< nplus >>
-<< pplus >>
+rect 328 19 345 36
+<< metal1 >>
+rect 0 309 576 357
+rect 58 306 87 309
+rect 58 289 64 306
+rect 81 289 87 306
+rect 58 283 87 289
+rect 322 306 351 309
+rect 322 289 328 306
+rect 345 289 351 306
+rect 322 283 351 289
+rect 178 238 207 244
+rect 178 237 184 238
+rect 89 223 184 237
+rect 89 69 103 223
+rect 178 221 184 223
+rect 201 237 207 238
+rect 466 238 495 244
+rect 201 223 439 237
+rect 201 221 207 223
+rect 178 215 207 221
+rect 425 204 439 223
+rect 466 221 472 238
+rect 489 221 495 238
+rect 466 215 495 221
+rect 130 198 159 204
+rect 130 181 136 198
+rect 153 181 159 198
+rect 130 175 159 181
+rect 274 198 303 204
+rect 274 181 280 198
+rect 297 181 303 198
+rect 274 175 303 181
+rect 418 198 447 204
+rect 418 181 424 198
+rect 441 181 447 198
+rect 418 175 447 181
+rect 137 109 151 175
+rect 281 109 295 175
+rect 425 109 439 175
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 86 159 103
+rect 130 80 159 86
+rect 274 103 303 109
+rect 274 86 280 103
+rect 297 86 303 103
+rect 274 80 303 86
+rect 418 103 447 109
+rect 418 86 424 103
+rect 441 86 447 103
+rect 418 80 447 86
+rect 473 69 487 215
+rect 82 63 111 69
+rect 82 46 88 63
+rect 105 46 111 63
+rect 82 40 111 46
+rect 466 63 495 69
+rect 466 46 472 63
+rect 489 46 495 63
+rect 322 36 351 42
+rect 466 40 495 46
+rect 322 24 328 36
+rect 0 19 328 24
+rect 345 24 351 36
+rect 345 19 576 24
+rect 0 -24 576 19
<< labels >>
-rlabel met1 0 309 576 357 0 VDD
+rlabel metal1 0 309 576 357 0 VDD
port 1 se
-rlabel met1 0 -24 576 24 0 GND
+rlabel metal1 0 -24 576 24 0 GND
port 2 se
-rlabel met1 466 40 495 69 0 Y
+rlabel metal1 466 40 495 69 0 Y
port 3 se
-rlabel met1 473 69 487 215 0 Y
+rlabel metal1 473 69 487 215 0 Y
port 4 se
-rlabel met1 466 215 495 244 0 Y
+rlabel metal1 466 215 495 244 0 Y
port 5 se
-rlabel met1 274 80 303 109 0 B
+rlabel metal1 130 80 159 109 0 A
port 6 se
-rlabel met1 281 109 295 175 0 B
+rlabel metal1 137 109 151 175 0 A
port 7 se
-rlabel met1 274 175 303 204 0 B
+rlabel metal1 130 175 159 204 0 A
port 8 se
-rlabel met1 130 80 159 109 0 A
+rlabel metal1 274 80 303 109 0 B
port 9 se
-rlabel met1 137 109 151 175 0 A
+rlabel metal1 281 109 295 175 0 B
port 10 se
-rlabel met1 130 175 159 204 0 A
+rlabel metal1 274 175 303 204 0 B
port 11 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/AOI21X1.mag b/cells/mag/AOI21X1.mag
index a7e24e6..846899b 100644
--- a/cells/mag/AOI21X1.mag
+++ b/cells/mag/AOI21X1.mag
@@ -1,182 +1,285 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621171877
+timestamp 1623602818
<< nwell >>
rect 0 179 576 333
-rect 27 333 550 340
-<< viali >>
-rect 328 5 345 22
-rect 88 46 105 63
-rect 472 46 489 63
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 88 221 105 238
-rect 328 221 345 238
-rect 376 221 393 238
-rect 472 221 489 238
-rect 184 289 201 306
-rect 232 289 249 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-<< properties >>
-string FIXED_BBOX 0 0 576 333
-<< li1 >>
-rect 200 11 257 44
-rect 328 5 345 11
-rect 320 11 377 44
-rect 80 38 113 71
-rect 464 38 497 71
-rect 128 78 161 111
-rect 272 78 305 111
-rect 416 78 449 111
-rect 128 173 161 206
-rect 272 173 305 206
-rect 416 173 449 206
-rect 80 213 113 246
-rect 320 213 353 246
-rect 368 213 401 246
-rect 464 213 497 246
-rect 176 281 209 314
-rect 224 281 257 314
-<< met1 >>
-rect 0 -24 576 24
-rect 322 24 351 28
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 80 303 109
-rect 281 109 295 175
-rect 274 175 303 204
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 82 215 111 223
-rect 322 215 351 223
-rect 370 215 399 223
-rect 82 223 399 237
-rect 82 237 111 244
-rect 322 237 351 244
-rect 370 237 399 244
-rect 82 40 111 47
-rect 466 40 495 47
-rect 82 47 495 61
-rect 82 61 111 69
-rect 466 61 495 69
-rect 473 69 487 215
-rect 466 215 495 244
-rect 178 283 207 309
-rect 226 283 255 309
-rect 0 309 576 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 576 24
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 80 303 109
-rect 281 109 295 175
-rect 274 175 303 204
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 82 40 111 47
-rect 466 40 495 47
-rect 82 47 495 61
-rect 82 61 111 69
-rect 466 61 495 69
-rect 473 69 487 215
-rect 466 215 495 244
-rect 0 309 576 357
-<< ndiffusion >>
-rect 202 13 255 24
-rect 322 13 375 24
-rect 58 24 519 66
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+<< ndiff >>
rect 82 66 111 69
rect 466 66 495 69
-<< pdiffusion >>
-rect 82 215 111 225
-rect 322 215 351 225
-rect 370 215 399 225
-rect 466 215 495 225
-rect 58 225 519 309
-rect 178 309 207 312
-rect 226 309 255 312
+rect 58 63 137 66
+rect 58 46 88 63
+rect 105 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 281 36
+rect 296 24 425 66
+rect 440 63 519 66
+rect 440 46 472 63
+rect 489 46 519 63
+rect 440 24 519 46
+rect 201 19 207 24
+rect 178 13 207 19
+<< pdiff >>
+rect 322 309 351 312
+rect 58 238 137 309
+rect 58 225 88 238
+rect 82 221 88 225
+rect 105 225 137 238
+rect 152 238 281 309
+rect 152 225 232 238
+rect 105 221 111 225
+rect 82 215 111 221
+rect 226 221 232 225
+rect 249 225 281 238
+rect 296 306 425 309
+rect 296 289 328 306
+rect 345 289 425 306
+rect 296 225 425 289
+rect 440 238 519 309
+rect 440 225 472 238
+rect 249 221 255 225
+rect 226 215 255 221
+rect 466 221 472 225
+rect 489 225 519 238
+rect 489 221 495 225
+rect 466 215 495 221
+<< ndiffc >>
+rect 88 46 105 63
+rect 184 19 201 36
+rect 472 46 489 63
+<< pdiffc >>
+rect 88 221 105 238
+rect 232 221 249 238
+rect 328 289 345 306
+rect 472 221 489 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 425 206 440 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 425 66 440 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
rect 136 181 153 198
rect 280 181 297 198
rect 424 181 441 198
-<< pdiffc >>
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+<< locali >>
+rect 320 306 353 314
+rect 320 289 328 306
+rect 345 289 353 306
+rect 320 281 353 289
+rect 80 238 113 246
+rect 80 221 88 238
+rect 105 221 113 238
+rect 80 213 113 221
+rect 224 238 257 246
+rect 224 221 232 238
+rect 249 223 257 238
+rect 464 238 497 246
+rect 464 223 472 238
+rect 249 221 255 223
+rect 224 213 255 221
+rect 466 221 472 223
+rect 489 221 497 238
+rect 466 213 497 221
+rect 130 198 161 206
+rect 130 196 136 198
+rect 128 181 136 196
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 88 449 103
+rect 441 86 447 88
+rect 416 78 447 86
+rect 80 63 111 71
+rect 80 46 88 63
+rect 105 61 111 63
+rect 464 63 497 71
+rect 105 46 113 61
+rect 80 38 113 46
+rect 464 46 472 63
+rect 489 46 497 63
+rect 176 36 209 44
+rect 464 38 497 46
+rect 176 11 184 36
+rect 201 11 209 36
+<< viali >>
+rect 328 289 345 306
rect 88 221 105 238
-rect 328 221 345 238
-rect 376 221 393 238
+rect 232 221 249 238
rect 472 221 489 238
-rect 184 289 201 306
-rect 232 289 249 306
-<< ndiffc >>
-rect 208 19 225 36
-rect 232 19 249 36
-rect 328 19 345 36
-rect 352 19 369 36
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
rect 88 46 105 63
rect 472 46 489 63
-<< nplus >>
-<< pplus >>
+rect 184 19 201 22
+rect 184 5 201 19
+<< metal1 >>
+rect 0 309 576 357
+rect 322 306 351 309
+rect 322 289 328 306
+rect 345 289 351 306
+rect 322 283 351 289
+rect 82 238 111 244
+rect 82 221 88 238
+rect 105 221 111 238
+rect 82 215 111 221
+rect 226 238 255 244
+rect 226 221 232 238
+rect 249 237 255 238
+rect 466 238 495 244
+rect 466 237 472 238
+rect 249 223 472 237
+rect 249 221 255 223
+rect 226 215 255 221
+rect 466 221 472 223
+rect 489 221 495 238
+rect 466 215 495 221
+rect 89 69 103 215
+rect 130 198 159 204
+rect 130 181 136 198
+rect 153 181 159 198
+rect 130 175 159 181
+rect 274 198 303 204
+rect 274 181 280 198
+rect 297 181 303 198
+rect 274 175 303 181
+rect 418 198 447 204
+rect 418 181 424 198
+rect 441 181 447 198
+rect 418 175 447 181
+rect 137 109 151 175
+rect 281 109 295 175
+rect 425 109 439 175
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 86 159 103
+rect 130 80 159 86
+rect 274 103 303 109
+rect 274 86 280 103
+rect 297 86 303 103
+rect 274 80 303 86
+rect 418 103 447 109
+rect 418 86 424 103
+rect 441 86 447 103
+rect 418 80 447 86
+rect 82 63 111 69
+rect 82 46 88 63
+rect 105 61 111 63
+rect 466 63 495 69
+rect 466 61 472 63
+rect 105 47 472 61
+rect 105 46 111 47
+rect 82 40 111 46
+rect 466 46 472 47
+rect 489 46 495 63
+rect 466 40 495 46
+rect 178 24 207 28
+rect 0 22 576 24
+rect 0 5 184 22
+rect 201 5 576 22
+rect 0 -24 576 5
<< labels >>
-rlabel met1 0 309 576 357 0 VDD
+rlabel metal1 0 309 576 357 0 VDD
port 1 se
-rlabel met1 0 -24 576 24 0 GND
+rlabel metal1 0 -24 576 24 0 GND
port 2 se
-rlabel met1 82 40 111 47 0 Y
+rlabel metal1 82 40 111 47 0 Y
port 3 se
-rlabel met1 466 40 495 47 0 Y
+rlabel metal1 466 40 495 47 0 Y
port 4 se
-rlabel met1 82 47 495 61 0 Y
+rlabel metal1 82 47 495 61 0 Y
port 5 se
-rlabel met1 82 61 111 69 0 Y
+rlabel metal1 82 61 111 69 0 Y
port 6 se
-rlabel met1 466 61 495 69 0 Y
+rlabel metal1 466 61 495 69 0 Y
port 7 se
-rlabel met1 473 69 487 215 0 Y
+rlabel metal1 89 69 103 215 0 Y
port 8 se
-rlabel met1 466 215 495 244 0 Y
+rlabel metal1 82 215 111 244 0 Y
port 9 se
-rlabel met1 130 80 159 109 0 B
+rlabel metal1 418 80 447 109 0 B
port 10 se
-rlabel met1 137 109 151 175 0 B
+rlabel metal1 425 109 439 175 0 B
port 11 se
-rlabel met1 130 175 159 204 0 B
+rlabel metal1 418 175 447 204 0 B
port 12 se
-rlabel met1 274 80 303 109 0 A
+rlabel metal1 274 80 303 109 0 A
port 13 se
-rlabel met1 281 109 295 175 0 A
+rlabel metal1 281 109 295 175 0 A
port 14 se
-rlabel met1 274 175 303 204 0 A
+rlabel metal1 274 175 303 204 0 A
port 15 se
-rlabel met1 418 80 447 109 0 C
+rlabel metal1 130 80 159 109 0 C
port 16 se
-rlabel met1 425 109 439 175 0 C
+rlabel metal1 137 109 151 175 0 C
port 17 se
-rlabel met1 418 175 447 204 0 C
+rlabel metal1 130 175 159 204 0 C
port 18 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/AOI22X1.mag b/cells/mag/AOI22X1.mag
index 7758a0b..dbaeb44 100644
--- a/cells/mag/AOI22X1.mag
+++ b/cells/mag/AOI22X1.mag
@@ -1,210 +1,344 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621172355
+timestamp 1623602822
<< nwell >>
rect 0 179 720 333
-rect 27 333 694 340
-<< viali >>
-rect 352 5 369 22
-rect 88 46 105 63
-rect 616 46 633 63
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 568 181 585 198
-rect 184 221 201 238
-rect 208 221 225 238
-rect 352 221 369 238
-rect 376 221 393 238
-rect 616 221 633 238
-rect 88 262 105 279
-rect 472 289 489 306
-rect 496 289 513 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 569 11 584 78
-rect 560 78 593 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-rect 560 173 593 206
-rect 569 206 584 330
-<< properties >>
-string FIXED_BBOX 0 0 720 333
-<< li1 >>
-rect 176 11 233 44
-rect 352 5 369 11
-rect 344 11 401 44
-rect 464 11 521 44
-rect 80 38 113 71
-rect 608 38 641 71
-rect 128 78 161 111
-rect 272 78 305 111
-rect 416 78 449 111
-rect 560 78 593 111
-rect 128 173 161 206
-rect 272 173 305 206
-rect 416 173 449 206
-rect 560 173 593 206
-rect 176 213 233 246
-rect 344 213 401 246
-rect 608 213 641 246
-rect 80 254 113 287
-rect 464 281 521 314
-<< met1 >>
-rect 0 -24 720 24
-rect 346 24 375 28
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 80 303 109
-rect 281 109 295 175
-rect 274 175 303 204
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 562 80 591 109
-rect 569 109 583 175
-rect 562 175 591 204
-rect 82 40 111 47
-rect 610 40 639 47
-rect 82 47 639 61
-rect 82 61 111 69
-rect 610 61 639 69
-rect 209 61 223 215
-rect 178 215 231 244
-rect 346 215 399 223
-rect 610 215 639 223
-rect 346 223 639 237
-rect 346 237 399 244
-rect 610 237 639 244
-rect 82 256 111 263
-rect 353 244 367 263
-rect 82 263 367 277
-rect 82 277 111 285
-rect 466 283 519 309
-rect 0 309 720 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 720 24
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 80 303 109
-rect 281 109 295 175
-rect 274 175 303 204
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 562 80 591 109
-rect 569 109 583 175
-rect 562 175 591 204
-rect 82 40 111 47
-rect 610 40 639 47
-rect 82 47 639 61
-rect 82 61 111 69
-rect 610 61 639 69
-rect 209 61 223 215
-rect 178 215 231 244
-rect 0 309 720 357
-<< ndiffusion >>
-rect 178 13 231 24
-rect 346 13 399 24
-rect 466 13 519 24
-rect 58 24 663 66
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+rect 569 24 584 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+rect 569 225 584 309
+<< ndiff >>
rect 82 66 111 69
rect 610 66 639 69
-<< pdiffusion >>
-rect 178 215 231 225
-rect 346 215 399 225
-rect 610 215 639 225
-rect 58 225 663 309
-rect 466 309 519 312
+rect 58 63 137 66
+rect 58 46 88 63
+rect 105 46 137 63
+rect 58 24 137 46
+rect 152 24 281 66
+rect 296 36 425 66
+rect 296 24 328 36
+rect 322 19 328 24
+rect 345 24 425 36
+rect 440 24 569 66
+rect 584 63 663 66
+rect 584 46 616 63
+rect 633 46 663 63
+rect 584 24 663 46
+rect 345 19 351 24
+rect 322 13 351 19
+<< pdiff >>
+rect 178 309 207 312
+rect 58 238 137 309
+rect 58 225 88 238
+rect 82 221 88 225
+rect 105 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 238 425 309
+rect 296 225 328 238
+rect 105 221 111 225
+rect 82 215 111 221
+rect 322 221 328 225
+rect 345 225 425 238
+rect 440 238 569 309
+rect 440 225 472 238
+rect 345 221 351 225
+rect 322 215 351 221
+rect 466 221 472 225
+rect 489 225 569 238
+rect 584 279 663 309
+rect 584 262 616 279
+rect 633 262 663 279
+rect 584 225 663 262
+rect 489 221 495 225
+rect 466 215 495 221
+<< ndiffc >>
+rect 88 46 105 63
+rect 328 19 345 36
+rect 616 46 633 63
+<< pdiffc >>
+rect 88 221 105 238
+rect 184 289 201 306
+rect 328 221 345 238
+rect 472 221 489 238
+rect 616 262 633 279
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 569 309 584 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 425 206 440 225
+rect 569 206 584 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 593 206
+rect 560 181 568 198
+rect 585 181 593 198
+rect 560 173 593 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 425 66 440 78
+rect 569 66 584 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
+rect 569 11 584 24
<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
rect 136 181 153 198
rect 280 181 297 198
rect 424 181 441 198
rect 568 181 585 198
-<< pdiffc >>
-rect 184 221 201 238
-rect 208 221 225 238
-rect 352 221 369 238
-rect 376 221 393 238
-rect 616 221 633 238
-rect 88 262 105 279
-rect 472 289 489 306
-rect 496 289 513 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 208 19 225 36
-rect 352 19 369 36
-rect 376 19 393 36
-rect 472 19 489 36
-rect 496 19 513 36
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 568 86 585 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 608 279 641 287
+rect 608 262 616 279
+rect 633 262 641 279
+rect 608 254 641 262
+rect 80 238 113 246
+rect 80 221 88 238
+rect 105 221 113 238
+rect 320 238 353 246
+rect 320 223 328 238
+rect 80 213 113 221
+rect 322 221 328 223
+rect 345 221 353 238
+rect 464 238 497 246
+rect 464 223 472 238
+rect 322 213 353 221
+rect 466 221 472 223
+rect 489 221 497 238
+rect 466 213 497 221
+rect 130 198 161 206
+rect 130 196 136 198
+rect 128 181 136 196
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 593 206
+rect 560 181 568 198
+rect 585 181 593 198
+rect 560 173 593 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 88 593 103
+rect 585 86 591 88
+rect 560 78 591 86
+rect 80 63 111 71
+rect 80 46 88 63
+rect 105 61 111 63
+rect 608 63 641 71
+rect 105 46 113 61
+rect 80 38 113 46
+rect 608 46 616 63
+rect 633 46 641 63
+rect 320 36 353 44
+rect 608 38 641 46
+rect 320 11 328 36
+rect 345 11 353 36
+<< viali >>
+rect 184 289 201 306
+rect 616 262 633 279
+rect 88 221 105 238
+rect 328 221 345 238
+rect 472 221 489 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 568 181 585 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 568 86 585 103
rect 88 46 105 63
rect 616 46 633 63
-<< nplus >>
-<< pplus >>
+rect 328 19 345 22
+rect 328 5 345 19
+<< metal1 >>
+rect 0 309 720 357
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 610 279 639 285
+rect 610 277 616 279
+rect 329 263 616 277
+rect 329 244 343 263
+rect 610 262 616 263
+rect 633 262 639 279
+rect 610 256 639 262
+rect 82 238 111 244
+rect 82 221 88 238
+rect 105 237 111 238
+rect 322 238 351 244
+rect 322 237 328 238
+rect 105 223 328 237
+rect 105 221 111 223
+rect 82 215 111 221
+rect 322 221 328 223
+rect 345 221 351 238
+rect 322 215 351 221
+rect 466 238 495 244
+rect 466 221 472 238
+rect 489 221 495 238
+rect 466 215 495 221
+rect 130 198 159 204
+rect 130 181 136 198
+rect 153 181 159 198
+rect 130 175 159 181
+rect 274 198 303 204
+rect 274 181 280 198
+rect 297 181 303 198
+rect 274 175 303 181
+rect 418 198 447 204
+rect 418 181 424 198
+rect 441 181 447 198
+rect 418 175 447 181
+rect 137 109 151 175
+rect 281 109 295 175
+rect 425 109 439 175
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 86 159 103
+rect 130 80 159 86
+rect 274 103 303 109
+rect 274 86 280 103
+rect 297 86 303 103
+rect 274 80 303 86
+rect 418 103 447 109
+rect 418 86 424 103
+rect 441 86 447 103
+rect 418 80 447 86
+rect 82 63 111 69
+rect 82 46 88 63
+rect 105 61 111 63
+rect 473 61 487 215
+rect 562 198 591 204
+rect 562 181 568 198
+rect 585 181 591 198
+rect 562 175 591 181
+rect 569 109 583 175
+rect 562 103 591 109
+rect 562 86 568 103
+rect 585 86 591 103
+rect 562 80 591 86
+rect 610 63 639 69
+rect 610 61 616 63
+rect 105 47 616 61
+rect 105 46 111 47
+rect 82 40 111 46
+rect 610 46 616 47
+rect 633 46 639 63
+rect 610 40 639 46
+rect 322 24 351 28
+rect 0 22 720 24
+rect 0 5 328 22
+rect 345 5 720 22
+rect 0 -24 720 5
<< labels >>
-rlabel met1 0 309 720 357 0 VDD
+rlabel metal1 0 309 720 357 0 VDD
port 1 se
-rlabel met1 0 -24 720 24 0 GND
+rlabel metal1 0 -24 720 24 0 GND
port 2 se
-rlabel met1 82 40 111 47 0 Y
+rlabel metal1 82 40 111 47 0 Y
port 3 se
-rlabel met1 610 40 639 47 0 Y
+rlabel metal1 610 40 639 47 0 Y
port 4 se
-rlabel met1 82 47 639 61 0 Y
+rlabel metal1 82 47 639 61 0 Y
port 5 se
-rlabel met1 82 61 111 69 0 Y
+rlabel metal1 82 61 111 69 0 Y
port 6 se
-rlabel met1 610 61 639 69 0 Y
+rlabel metal1 610 61 639 69 0 Y
port 7 se
-rlabel met1 209 61 223 215 0 Y
+rlabel metal1 473 61 487 215 0 Y
port 8 se
-rlabel met1 178 215 231 244 0 Y
+rlabel metal1 466 215 495 244 0 Y
port 9 se
-rlabel met1 562 80 591 109 0 B
+rlabel metal1 130 80 159 109 0 B
port 10 se
-rlabel met1 569 109 583 175 0 B
+rlabel metal1 137 109 151 175 0 B
port 11 se
-rlabel met1 562 175 591 204 0 B
+rlabel metal1 130 175 159 204 0 B
port 12 se
-rlabel met1 274 80 303 109 0 C
+rlabel metal1 274 80 303 109 0 A
port 13 se
-rlabel met1 281 109 295 175 0 C
+rlabel metal1 281 109 295 175 0 A
port 14 se
-rlabel met1 274 175 303 204 0 C
+rlabel metal1 274 175 303 204 0 A
port 15 se
-rlabel met1 418 80 447 109 0 A
+rlabel metal1 418 80 447 109 0 C
port 16 se
-rlabel met1 425 109 439 175 0 A
+rlabel metal1 425 109 439 175 0 C
port 17 se
-rlabel met1 418 175 447 204 0 A
+rlabel metal1 418 175 447 204 0 C
port 18 se
-rlabel met1 130 80 159 109 0 D
+rlabel metal1 562 80 591 109 0 D
port 19 se
-rlabel met1 137 109 151 175 0 D
+rlabel metal1 569 109 583 175 0 D
port 20 se
-rlabel met1 130 175 159 204 0 D
+rlabel metal1 562 175 591 204 0 D
port 21 se
+<< properties >>
+string FIXED_BBOX 0 0 720 333
<< end >>
diff --git a/cells/mag/BUFX2.mag b/cells/mag/BUFX2.mag
index dfde1c5..0991872 100644
--- a/cells/mag/BUFX2.mag
+++ b/cells/mag/BUFX2.mag
@@ -1,111 +1,209 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621173095
+timestamp 1623602826
<< nwell >>
rect 0 179 432 333
-rect 27 333 406 340
-<< viali >>
-rect 184 19 201 36
-rect 208 19 225 36
-rect 64 46 81 63
-rect 328 46 345 63
-rect 136 86 153 103
-rect 280 86 297 103
-rect 280 181 297 198
-rect 64 221 81 238
-rect 328 221 345 238
-rect 184 289 201 306
-rect 208 289 225 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-<< properties >>
-string FIXED_BBOX 0 0 432 333
-<< li1 >>
-rect 176 11 233 44
-rect 56 38 89 71
-rect 320 38 353 71
-rect 272 78 305 111
-rect 128 78 161 111
-rect 136 111 153 173
-rect 128 173 161 206
-rect 272 173 305 206
-rect 56 213 89 246
-rect 320 213 353 246
-rect 176 281 233 314
-<< met1 >>
-rect 0 -24 432 24
-rect 178 24 231 42
-rect 130 80 159 109
-rect 58 40 87 69
-rect 274 80 303 109
-rect 281 109 295 175
-rect 65 69 79 182
-rect 274 175 303 182
-rect 65 182 303 196
-rect 274 196 303 204
-rect 65 196 79 215
-rect 58 215 87 244
-rect 322 40 351 69
-rect 329 69 343 215
-rect 322 215 351 244
-rect 178 283 231 309
-rect 0 309 432 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 432 24
-rect 130 80 159 109
-rect 322 40 351 69
-rect 329 69 343 215
-rect 322 215 351 244
-rect 0 309 432 357
-<< ndiffusion >>
-rect 178 13 231 24
-rect 58 24 375 66
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+<< ndiff >>
rect 58 66 87 69
rect 322 66 351 69
-<< pdiffusion >>
-rect 58 215 87 225
-rect 322 215 351 225
-rect 58 225 375 309
-rect 178 309 231 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 136 181 153 198
-rect 280 181 297 198
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 281 36
+rect 296 63 375 66
+rect 296 46 328 63
+rect 345 46 375 63
+rect 296 24 375 46
+rect 201 19 207 24
+rect 178 13 207 19
+<< pdiff >>
+rect 178 309 207 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 238 375 309
+rect 296 225 328 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 322 221 328 225
+rect 345 225 375 238
+rect 345 221 351 225
+rect 322 215 351 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 184 19 201 36
+rect 328 46 345 63
<< pdiffc >>
rect 64 221 81 238
-rect 328 221 345 238
rect 184 289 201 306
-rect 208 289 225 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 208 19 225 36
+rect 328 221 345 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 137 11 152 24
+rect 281 11 296 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 56 238 89 246
+rect 56 221 64 238
+rect 81 221 89 238
+rect 56 213 89 221
+rect 320 238 353 246
+rect 320 221 328 238
+rect 345 221 353 238
+rect 320 213 353 221
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 303 206
+rect 272 181 280 198
+rect 297 196 303 198
+rect 297 181 305 196
+rect 272 173 305 181
+rect 136 157 153 173
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 88 305 103
+rect 297 86 303 88
+rect 272 78 303 86
+rect 56 63 89 71
+rect 56 46 64 63
+rect 81 46 89 63
+rect 56 38 89 46
+rect 320 63 353 71
+rect 320 46 328 63
+rect 345 46 353 63
+rect 176 36 209 44
+rect 320 38 353 46
+rect 176 19 184 36
+rect 201 19 209 36
+rect 176 11 209 19
+<< viali >>
+rect 184 289 201 306
+rect 64 221 81 238
+rect 328 221 345 238
+rect 280 181 297 198
+rect 136 140 153 157
+rect 136 86 153 103
+rect 280 86 297 103
rect 64 46 81 63
rect 328 46 345 63
-<< nplus >>
-<< pplus >>
+rect 184 19 201 36
+<< metal1 >>
+rect 0 309 432 357
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 221 87 238
+rect 58 215 87 221
+rect 322 238 351 244
+rect 322 221 328 238
+rect 345 221 351 238
+rect 322 215 351 221
+rect 65 196 79 215
+rect 274 198 303 204
+rect 274 196 280 198
+rect 65 182 280 196
+rect 65 69 79 182
+rect 274 181 280 182
+rect 297 181 303 198
+rect 274 175 303 181
+rect 130 157 159 163
+rect 130 140 136 157
+rect 153 140 159 157
+rect 130 134 159 140
+rect 137 109 151 134
+rect 281 109 295 175
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 86 159 103
+rect 130 80 159 86
+rect 274 103 303 109
+rect 274 86 280 103
+rect 297 86 303 103
+rect 274 80 303 86
+rect 329 69 343 215
+rect 58 63 87 69
+rect 58 46 64 63
+rect 81 46 87 63
+rect 58 40 87 46
+rect 322 63 351 69
+rect 322 46 328 63
+rect 345 46 351 63
+rect 178 36 207 42
+rect 322 40 351 46
+rect 178 24 184 36
+rect 0 19 184 24
+rect 201 24 207 36
+rect 201 19 432 24
+rect 0 -24 432 19
<< labels >>
-rlabel met1 0 309 432 357 0 VDD
+rlabel metal1 0 309 432 357 0 VDD
port 1 se
-rlabel met1 0 -24 432 24 0 GND
+rlabel metal1 0 -24 432 24 0 GND
port 2 se
-rlabel met1 322 40 351 69 0 Y
+rlabel metal1 322 40 351 69 0 Y
port 3 se
-rlabel met1 329 69 343 215 0 Y
+rlabel metal1 329 69 343 215 0 Y
port 4 se
-rlabel met1 322 215 351 244 0 Y
+rlabel metal1 322 215 351 244 0 Y
port 5 se
-rlabel met1 130 80 159 109 0 A
+rlabel metal1 130 80 159 109 0 A
port 6 se
+rlabel metal1 137 109 151 134 0 A
+port 7 se
+rlabel metal1 130 134 159 163 0 A
+port 8 se
+<< properties >>
+string FIXED_BBOX 0 0 432 333
<< end >>
diff --git a/cells/mag/BUFX4.mag b/cells/mag/BUFX4.mag
deleted file mode 100644
index 9fb70c5..0000000
--- a/cells/mag/BUFX4.mag
+++ /dev/null
@@ -1,174 +0,0 @@
-magic
-# Generated by librecell
-tech sky130A
-timestamp 1621173301
-<< nwell >>
-rect 0 179 576 333
-rect 27 333 550 340
-<< viali >>
-rect 184 19 201 36
-rect 232 19 249 36
-rect 496 19 513 36
-rect 64 46 81 63
-rect 376 46 393 63
-rect 280 86 297 103
-rect 424 86 441 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 64 221 81 238
-rect 328 221 345 238
-rect 376 221 393 238
-rect 184 289 201 306
-rect 232 289 249 306
-rect 472 289 489 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-<< properties >>
-string FIXED_BBOX 0 0 576 333
-<< li1 >>
-rect 176 11 209 44
-rect 224 11 257 44
-rect 488 11 521 44
-rect 56 38 89 71
-rect 320 11 377 38
-rect 320 38 401 44
-rect 368 44 401 71
-rect 272 78 305 111
-rect 416 78 449 111
-rect 128 78 161 111
-rect 136 111 153 173
-rect 128 173 161 206
-rect 272 173 305 206
-rect 416 173 449 206
-rect 56 213 89 246
-rect 320 213 353 246
-rect 368 213 401 246
-rect 176 281 209 314
-rect 224 281 257 314
-rect 464 281 497 314
-<< met1 >>
-rect 0 -24 576 24
-rect 178 24 207 42
-rect 226 24 255 42
-rect 490 24 519 42
-rect 130 175 159 204
-rect 58 40 87 69
-rect 65 69 79 88
-rect 274 80 303 88
-rect 418 80 447 88
-rect 65 88 447 102
-rect 274 102 303 109
-rect 418 102 447 109
-rect 281 109 295 175
-rect 425 109 439 175
-rect 274 175 303 204
-rect 418 175 447 204
-rect 65 102 79 215
-rect 58 215 87 244
-rect 370 40 399 47
-rect 370 47 487 61
-rect 370 61 399 69
-rect 322 215 351 223
-rect 370 215 399 223
-rect 473 61 487 223
-rect 322 223 487 237
-rect 322 237 351 244
-rect 370 237 399 244
-rect 178 283 207 309
-rect 226 283 255 309
-rect 466 283 495 309
-rect 0 309 576 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 576 24
-rect 130 175 159 204
-rect 370 40 399 47
-rect 370 47 487 61
-rect 370 61 399 69
-rect 322 215 351 223
-rect 370 215 399 223
-rect 473 61 487 223
-rect 322 223 487 237
-rect 322 237 351 244
-rect 370 237 399 244
-rect 0 309 576 357
-<< ndiffusion >>
-rect 178 13 207 24
-rect 226 13 255 24
-rect 322 13 375 24
-rect 490 13 519 24
-rect 58 24 519 66
-rect 58 66 87 69
-rect 370 66 399 69
-<< pdiffusion >>
-rect 58 215 87 225
-rect 322 215 351 225
-rect 370 215 399 225
-rect 58 225 519 309
-rect 178 309 207 312
-rect 226 309 255 312
-rect 466 309 495 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-<< pdiffc >>
-rect 64 221 81 238
-rect 328 221 345 238
-rect 376 221 393 238
-rect 184 289 201 306
-rect 232 289 249 306
-rect 472 289 489 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 232 19 249 36
-rect 328 19 345 36
-rect 352 19 369 36
-rect 496 19 513 36
-rect 64 46 81 63
-rect 376 46 393 63
-<< nplus >>
-<< pplus >>
-<< labels >>
-rlabel met1 0 309 576 357 0 VDD
-port 1 se
-rlabel met1 0 -24 576 24 0 GND
-port 2 se
-rlabel met1 370 40 399 47 0 Y
-port 3 se
-rlabel met1 370 47 487 61 0 Y
-port 4 se
-rlabel met1 370 61 399 69 0 Y
-port 5 se
-rlabel met1 322 215 351 223 0 Y
-port 6 se
-rlabel met1 370 215 399 223 0 Y
-port 7 se
-rlabel met1 473 61 487 223 0 Y
-port 8 se
-rlabel met1 322 223 487 237 0 Y
-port 9 se
-rlabel met1 322 237 351 244 0 Y
-port 10 se
-rlabel met1 370 237 399 244 0 Y
-port 11 se
-rlabel met1 130 175 159 204 0 A
-port 12 se
-<< end >>
diff --git a/cells/mag/CLKBUF1.mag b/cells/mag/CLKBUF1.mag
deleted file mode 100644
index 277d143..0000000
--- a/cells/mag/CLKBUF1.mag
+++ /dev/null
@@ -1,370 +0,0 @@
-magic
-# Generated by librecell
-tech sky130A
-timestamp 1621174286
-<< nwell >>
-rect 0 179 1296 333
-rect 27 333 1270 340
-<< viali >>
-rect 616 5 633 22
-rect 904 5 921 22
-rect 64 19 81 36
-rect 328 19 345 36
-rect 352 19 369 36
-rect 1192 19 1209 36
-rect 184 46 201 63
-rect 520 46 537 63
-rect 808 46 825 63
-rect 1096 46 1113 63
-rect 136 86 153 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 712 86 729 103
-rect 856 86 873 103
-rect 1000 86 1017 103
-rect 1144 86 1161 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 568 181 585 198
-rect 712 181 729 198
-rect 856 181 873 198
-rect 1000 181 1017 198
-rect 1144 181 1161 198
-rect 184 221 201 238
-rect 232 221 249 238
-rect 472 221 489 238
-rect 520 221 537 238
-rect 784 221 801 238
-rect 808 221 825 238
-rect 1072 221 1089 238
-rect 1096 221 1113 238
-rect 64 289 81 306
-rect 328 289 345 306
-rect 376 289 393 306
-rect 616 289 633 306
-rect 664 289 681 306
-rect 904 289 921 306
-rect 928 289 945 306
-rect 1192 289 1209 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 569 11 584 78
-rect 560 78 593 111
-rect 713 11 728 78
-rect 704 78 737 111
-rect 857 11 872 78
-rect 848 78 881 111
-rect 1001 11 1016 78
-rect 992 78 1025 111
-rect 1145 11 1160 78
-rect 1136 78 1169 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-rect 560 173 593 206
-rect 569 206 584 330
-rect 704 173 737 206
-rect 713 206 728 330
-rect 848 173 881 206
-rect 857 206 872 330
-rect 992 173 1025 206
-rect 1001 206 1016 330
-rect 1136 173 1169 206
-rect 1145 206 1160 330
-<< properties >>
-string FIXED_BBOX 0 0 1296 333
-<< li1 >>
-rect 56 11 89 44
-rect 320 11 377 44
-rect 616 5 633 11
-rect 608 11 641 19
-rect 656 11 689 19
-rect 608 19 689 36
-rect 608 36 641 44
-rect 656 36 689 44
-rect 904 5 921 11
-rect 896 11 929 19
-rect 944 11 977 19
-rect 896 19 977 36
-rect 896 36 929 44
-rect 944 36 977 44
-rect 1184 11 1217 44
-rect 200 11 257 38
-rect 176 38 257 44
-rect 176 44 209 71
-rect 488 11 545 44
-rect 512 44 545 71
-rect 752 11 809 38
-rect 752 38 833 44
-rect 800 44 833 71
-rect 1040 11 1097 38
-rect 1040 38 1121 44
-rect 1088 44 1121 71
-rect 128 78 161 111
-rect 416 78 449 111
-rect 560 78 593 111
-rect 704 78 737 111
-rect 848 78 881 111
-rect 992 78 1025 111
-rect 1136 78 1169 111
-rect 128 173 161 206
-rect 272 78 305 111
-rect 280 111 297 173
-rect 272 173 305 206
-rect 416 173 449 206
-rect 560 173 593 206
-rect 704 173 737 206
-rect 848 173 881 206
-rect 992 173 1025 206
-rect 1136 173 1169 206
-rect 176 213 209 246
-rect 224 213 257 246
-rect 464 213 497 246
-rect 512 213 545 246
-rect 776 213 833 246
-rect 1064 213 1121 246
-rect 56 281 89 314
-rect 320 281 353 314
-rect 368 281 401 314
-rect 608 281 641 314
-rect 656 281 689 314
-rect 896 281 953 314
-rect 1184 281 1217 314
-<< met1 >>
-rect 0 -24 1296 24
-rect 610 24 639 28
-rect 898 24 927 28
-rect 58 24 87 42
-rect 322 24 375 42
-rect 1186 24 1215 42
-rect 178 40 207 69
-rect 185 69 199 88
-rect 418 80 447 88
-rect 562 80 591 88
-rect 185 88 591 102
-rect 418 102 447 109
-rect 562 102 591 109
-rect 425 109 439 175
-rect 569 109 583 175
-rect 418 175 447 204
-rect 562 175 591 204
-rect 185 102 199 215
-rect 178 215 207 223
-rect 226 215 255 223
-rect 178 223 255 237
-rect 178 237 207 244
-rect 226 237 255 244
-rect 514 40 543 47
-rect 514 47 727 61
-rect 514 61 543 69
-rect 713 61 727 80
-rect 706 80 735 109
-rect 850 80 879 109
-rect 713 109 727 175
-rect 857 109 871 175
-rect 706 175 735 182
-rect 850 175 879 182
-rect 706 182 879 196
-rect 706 196 735 204
-rect 850 196 879 204
-rect 466 215 495 223
-rect 514 215 543 223
-rect 713 204 727 223
-rect 466 223 727 237
-rect 466 237 495 244
-rect 514 237 543 244
-rect 802 40 831 47
-rect 802 47 1015 61
-rect 802 61 831 69
-rect 1001 61 1015 80
-rect 994 80 1023 88
-rect 1138 80 1167 88
-rect 994 88 1167 102
-rect 994 102 1023 109
-rect 1138 102 1167 109
-rect 1001 109 1015 175
-rect 1145 109 1159 175
-rect 994 175 1023 204
-rect 1138 175 1167 204
-rect 778 215 831 223
-rect 1001 204 1015 223
-rect 778 223 1015 237
-rect 778 237 831 244
-rect 1090 40 1119 47
-rect 1090 47 1183 61
-rect 1090 61 1119 69
-rect 1169 61 1207 75
-rect 1066 215 1119 223
-rect 1193 75 1207 223
-rect 1066 223 1207 237
-rect 1066 237 1119 244
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 175 303 204
-rect 137 204 151 263
-rect 281 204 295 263
-rect 137 263 295 277
-rect 58 283 87 309
-rect 322 283 351 309
-rect 370 283 399 309
-rect 610 283 639 309
-rect 658 283 687 309
-rect 898 283 951 309
-rect 1186 283 1215 309
-rect 0 309 1296 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 1296 24
-rect 1090 40 1119 47
-rect 1090 47 1183 61
-rect 1090 61 1119 69
-rect 1169 61 1207 75
-rect 1066 215 1119 223
-rect 1193 75 1207 223
-rect 1066 223 1207 237
-rect 1066 237 1119 244
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 274 175 303 204
-rect 137 204 151 263
-rect 281 204 295 263
-rect 137 263 295 277
-rect 0 309 1296 357
-<< ndiffusion >>
-rect 58 13 87 24
-rect 202 13 255 24
-rect 322 13 375 24
-rect 490 13 543 24
-rect 610 13 639 24
-rect 658 13 687 24
-rect 754 13 807 24
-rect 898 13 927 24
-rect 946 13 975 24
-rect 1042 13 1095 24
-rect 1186 13 1215 24
-rect 58 24 1239 66
-rect 178 66 207 69
-rect 514 66 543 69
-rect 802 66 831 69
-rect 1090 66 1119 69
-<< pdiffusion >>
-rect 178 215 207 225
-rect 226 215 255 225
-rect 466 215 495 225
-rect 514 215 543 225
-rect 778 215 831 225
-rect 1066 215 1119 225
-rect 58 225 1239 309
-rect 58 309 87 312
-rect 322 309 351 312
-rect 370 309 399 312
-rect 610 309 639 312
-rect 658 309 687 312
-rect 898 309 951 312
-rect 1186 309 1215 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 712 86 729 103
-rect 856 86 873 103
-rect 1000 86 1017 103
-rect 1144 86 1161 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 568 181 585 198
-rect 712 181 729 198
-rect 856 181 873 198
-rect 1000 181 1017 198
-rect 1144 181 1161 198
-<< pdiffc >>
-rect 184 221 201 238
-rect 232 221 249 238
-rect 472 221 489 238
-rect 520 221 537 238
-rect 784 221 801 238
-rect 808 221 825 238
-rect 1072 221 1089 238
-rect 1096 221 1113 238
-rect 64 289 81 306
-rect 328 289 345 306
-rect 376 289 393 306
-rect 616 289 633 306
-rect 664 289 681 306
-rect 904 289 921 306
-rect 928 289 945 306
-rect 1192 289 1209 306
-<< ndiffc >>
-rect 64 19 81 36
-rect 208 19 225 36
-rect 232 19 249 36
-rect 328 19 345 36
-rect 352 19 369 36
-rect 496 19 513 36
-rect 520 19 537 36
-rect 616 19 633 36
-rect 664 19 681 36
-rect 760 19 777 36
-rect 784 19 801 36
-rect 904 19 921 36
-rect 952 19 969 36
-rect 1048 19 1065 36
-rect 1072 19 1089 36
-rect 1192 19 1209 36
-rect 184 46 201 63
-rect 520 46 537 63
-rect 808 46 825 63
-rect 1096 46 1113 63
-<< nplus >>
-<< pplus >>
-<< labels >>
-rlabel met1 0 309 1296 357 0 VDD
-port 1 se
-rlabel met1 0 -24 1296 24 0 GND
-port 2 se
-rlabel met1 1090 40 1119 47 0 Y
-port 3 se
-rlabel met1 1090 47 1183 61 0 Y
-port 4 se
-rlabel met1 1090 61 1119 69 0 Y
-port 5 se
-rlabel met1 1169 61 1207 75 0 Y
-port 6 se
-rlabel met1 1066 215 1119 223 0 Y
-port 7 se
-rlabel met1 1193 75 1207 223 0 Y
-port 8 se
-rlabel met1 1066 223 1207 237 0 Y
-port 9 se
-rlabel met1 1066 237 1119 244 0 Y
-port 10 se
-rlabel met1 130 80 159 109 0 A
-port 11 se
-rlabel met1 137 109 151 175 0 A
-port 12 se
-rlabel met1 130 175 159 204 0 A
-port 13 se
-rlabel met1 274 175 303 204 0 A
-port 14 se
-rlabel met1 137 204 151 263 0 A
-port 15 se
-rlabel met1 281 204 295 263 0 A
-port 16 se
-rlabel met1 137 263 295 277 0 A
-port 17 se
-<< end >>
diff --git a/cells/mag/HAX1.mag b/cells/mag/HAX1.mag
index 1d38158..b9d9579 100644
--- a/cells/mag/HAX1.mag
+++ b/cells/mag/HAX1.mag
@@ -1,265 +1,243 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621175334
+timestamp 1623602949
<< nwell >>
rect 0 179 1584 333
-rect 27 333 1558 340
-<< viali >>
-rect 616 5 633 22
-rect 784 5 801 22
-rect 64 19 81 36
-rect 1360 19 1377 36
-rect 184 46 201 63
-rect 352 46 369 63
-rect 952 46 969 63
-rect 1192 46 1209 63
-rect 1480 46 1497 63
-rect 904 59 921 76
-rect 136 86 153 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 1144 86 1161 103
-rect 1432 86 1449 103
-rect 1048 140 1065 157
-rect 136 181 153 198
-rect 424 181 441 198
-rect 568 181 585 198
-rect 856 181 873 198
-rect 1144 181 1161 198
-rect 1432 181 1449 198
-rect 184 221 201 238
-rect 352 221 369 238
-rect 616 221 633 238
-rect 928 221 945 238
-rect 952 221 969 238
-rect 1480 221 1497 238
-rect 64 289 81 306
-rect 472 289 489 306
-rect 496 289 513 306
-rect 784 289 801 306
-rect 1192 289 1209 306
-rect 1360 289 1377 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 569 11 584 78
-rect 560 78 593 111
-rect 857 11 872 78
-rect 848 78 881 111
-rect 1001 11 1016 78
-rect 992 78 1025 111
-rect 1145 11 1160 78
-rect 1136 78 1169 111
-rect 1433 11 1448 78
-rect 1424 78 1457 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 416 173 449 206
-rect 425 206 440 330
-rect 560 173 593 206
-rect 569 206 584 330
-rect 848 173 881 206
-rect 857 206 872 330
-rect 992 173 1025 206
-rect 1001 206 1016 330
-rect 1136 173 1169 206
-rect 1145 206 1160 330
-rect 1424 173 1457 206
-rect 1433 206 1448 330
-<< properties >>
-string FIXED_BBOX 0 0 1584 333
-<< li1 >>
-rect 56 11 89 44
-rect 488 11 545 44
-rect 616 5 633 11
-rect 608 11 641 44
-rect 784 5 801 11
-rect 776 11 809 44
-rect 1352 11 1385 44
-rect 176 38 209 71
-rect 344 38 377 71
-rect 896 11 953 38
-rect 896 38 977 44
-rect 944 44 977 71
-rect 1184 38 1217 71
-rect 1472 38 1505 71
-rect 128 78 161 111
-rect 416 78 449 111
-rect 560 78 593 111
-rect 1136 78 1169 111
-rect 1424 78 1457 111
-rect 1040 11 1097 44
-rect 1040 44 1073 71
-rect 1048 71 1065 157
-rect 128 173 161 206
-rect 416 173 449 206
-rect 560 173 593 206
-rect 848 78 881 111
-rect 856 111 873 173
-rect 848 173 881 206
-rect 904 59 921 86
-rect 992 78 1025 86
-rect 904 86 1025 103
-rect 992 103 1025 111
-rect 1000 111 1017 173
-rect 992 173 1025 206
-rect 1136 173 1169 206
-rect 1424 173 1457 206
-rect 176 213 209 246
-rect 344 213 377 246
-rect 608 213 641 246
-rect 920 213 977 246
-rect 1040 213 1097 246
-rect 1472 213 1505 246
-rect 56 281 89 314
-rect 464 281 521 314
-rect 776 281 809 314
-rect 1184 281 1217 314
-rect 1352 281 1385 314
-<< met1 >>
-rect 0 -24 1584 24
-rect 610 24 639 28
-rect 778 24 807 28
-rect 58 24 87 42
-rect 1354 24 1383 42
-rect 946 40 975 47
-rect 1186 40 1215 47
-rect 946 47 1215 61
-rect 946 61 975 69
-rect 1186 61 1215 69
-rect 425 47 919 53
-rect 425 53 927 61
-rect 425 61 439 80
-rect 898 61 927 82
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 562 80 591 101
-rect 1138 80 1167 101
-rect 562 101 1167 109
-rect 569 109 1159 115
-rect 569 115 583 175
-rect 1145 115 1159 175
-rect 562 175 591 204
-rect 1138 175 1167 204
-rect 178 40 207 47
-rect 89 47 207 61
-rect 178 61 207 69
-rect 89 61 103 223
-rect 178 215 207 223
-rect 89 223 207 237
-rect 178 237 207 244
-rect 346 40 375 69
-rect 130 80 159 88
-rect 353 69 367 88
-rect 130 88 367 102
-rect 130 102 159 109
-rect 137 109 151 175
-rect 130 175 159 204
-rect 850 175 879 204
-rect 353 102 367 215
-rect 346 215 375 223
-rect 610 215 639 223
-rect 857 204 871 223
-rect 346 223 871 237
-rect 346 237 375 244
-rect 610 237 639 244
-rect 1426 80 1455 109
-rect 1042 134 1071 142
-rect 953 142 1071 156
-rect 1042 156 1071 163
-rect 1433 109 1447 175
-rect 1426 175 1455 204
-rect 953 156 967 215
-rect 922 215 975 223
-rect 1433 204 1447 223
-rect 922 223 1447 237
-rect 922 237 975 244
-rect 1474 40 1503 69
-rect 1481 69 1495 215
-rect 1474 215 1503 244
-rect 58 283 87 309
-rect 466 283 519 309
-rect 778 283 807 309
-rect 1186 283 1215 309
-rect 1354 283 1383 309
-rect 0 309 1584 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 1584 24
-rect 425 47 919 53
-rect 425 53 927 61
-rect 425 61 439 80
-rect 898 61 927 82
-rect 418 80 447 109
-rect 425 109 439 175
-rect 418 175 447 204
-rect 562 80 591 101
-rect 1138 80 1167 101
-rect 562 101 1167 109
-rect 569 109 1159 115
-rect 569 115 583 175
-rect 1145 115 1159 175
-rect 562 175 591 204
-rect 1138 175 1167 204
-rect 178 40 207 47
-rect 89 47 207 61
-rect 178 61 207 69
-rect 89 61 103 223
-rect 178 215 207 223
-rect 89 223 207 237
-rect 178 237 207 244
-rect 1474 40 1503 69
-rect 1481 69 1495 215
-rect 1474 215 1503 244
-rect 0 309 1584 357
-<< ndiffusion >>
-rect 58 13 87 24
-rect 58 24 231 66
-rect 178 66 207 69
-rect 490 13 543 24
-rect 610 13 639 24
-rect 346 24 663 66
+<< nmos >>
+rect 137 24 152 66
+rect 425 24 440 66
+rect 569 24 584 66
+rect 857 24 872 66
+rect 1001 24 1016 66
+rect 1145 24 1160 66
+rect 1433 24 1448 66
+<< pmos >>
+rect 137 225 152 309
+rect 425 225 440 309
+rect 569 225 584 309
+rect 857 225 872 309
+rect 1001 225 1016 309
+rect 1145 225 1160 309
+rect 1433 225 1448 309
+<< ndiff >>
+rect 58 66 87 69
rect 346 66 375 69
-rect 778 13 807 24
-rect 898 13 951 24
-rect 1042 13 1095 24
-rect 778 24 1239 66
-rect 946 66 975 69
rect 1042 66 1071 69
-rect 1186 66 1215 69
-rect 1354 13 1383 24
-rect 1354 24 1527 66
rect 1474 66 1503 69
-<< pdiffusion >>
-rect 178 215 207 225
-rect 58 225 231 309
-rect 58 309 87 312
-rect 346 215 375 225
-rect 610 215 639 225
-rect 346 225 663 309
-rect 466 309 519 312
-rect 922 215 975 225
-rect 1042 215 1095 225
-rect 778 225 1239 309
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 36 231 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 231 36
+rect 346 63 425 66
+rect 346 46 352 63
+rect 369 46 425 63
+rect 346 24 425 46
+rect 440 24 569 66
+rect 584 36 663 66
+rect 584 24 616 36
+rect 201 19 207 24
+rect 178 13 207 19
+rect 610 19 616 24
+rect 633 24 663 36
+rect 778 36 857 66
+rect 633 19 639 24
+rect 610 13 639 19
+rect 778 19 784 36
+rect 801 24 857 36
+rect 872 36 1001 66
+rect 872 24 952 36
+rect 801 19 807 24
+rect 778 13 807 19
+rect 946 19 952 24
+rect 969 24 1001 36
+rect 1016 63 1145 66
+rect 1016 46 1048 63
+rect 1065 46 1145 63
+rect 1016 24 1145 46
+rect 1160 36 1239 66
+rect 1160 24 1192 36
+rect 969 19 975 24
+rect 946 13 975 19
+rect 1186 19 1192 24
+rect 1209 24 1239 36
+rect 1354 36 1433 66
+rect 1209 19 1215 24
+rect 1186 13 1215 19
+rect 1354 19 1360 36
+rect 1377 24 1433 36
+rect 1448 63 1527 66
+rect 1448 46 1480 63
+rect 1497 46 1527 63
+rect 1448 24 1527 46
+rect 1377 19 1383 24
+rect 1354 13 1383 19
+<< pdiff >>
+rect 178 309 207 312
+rect 466 309 495 312
rect 778 309 807 312
rect 1186 309 1215 312
-rect 1474 215 1503 225
-rect 1354 225 1527 309
rect 1354 309 1383 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 231 309
+rect 152 289 184 306
+rect 201 289 231 306
+rect 152 225 231 289
+rect 346 238 425 309
+rect 81 221 87 225
+rect 58 215 87 221
+rect 346 221 352 238
+rect 369 225 425 238
+rect 440 306 569 309
+rect 440 289 472 306
+rect 489 289 569 306
+rect 440 225 569 289
+rect 584 238 663 309
+rect 584 225 616 238
+rect 369 221 375 225
+rect 346 215 375 221
+rect 610 221 616 225
+rect 633 225 663 238
+rect 778 306 857 309
+rect 778 289 784 306
+rect 801 289 857 306
+rect 778 225 857 289
+rect 872 238 1001 309
+rect 872 225 952 238
+rect 633 221 639 225
+rect 610 215 639 221
+rect 946 221 952 225
+rect 969 225 1001 238
+rect 1016 225 1145 309
+rect 1160 306 1239 309
+rect 1160 289 1192 306
+rect 1209 289 1239 306
+rect 1160 225 1239 289
+rect 1354 306 1433 309
+rect 1354 289 1360 306
+rect 1377 289 1433 306
+rect 1354 225 1433 289
+rect 1448 238 1527 309
+rect 1448 225 1480 238
+rect 969 221 975 225
+rect 946 215 975 221
+rect 1474 221 1480 225
+rect 1497 225 1527 238
+rect 1497 221 1503 225
+rect 1474 215 1503 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 184 19 201 36
+rect 352 46 369 63
+rect 616 19 633 36
+rect 784 19 801 36
+rect 952 19 969 36
+rect 1048 46 1065 63
+rect 1192 19 1209 36
+rect 1360 19 1377 36
+rect 1480 46 1497 63
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 352 221 369 238
+rect 472 289 489 306
+rect 616 221 633 238
+rect 784 289 801 306
+rect 952 221 969 238
+rect 1192 289 1209 306
+rect 1360 289 1377 306
+rect 1480 221 1497 238
+<< poly >>
+rect 137 309 152 330
+rect 425 309 440 330
+rect 569 309 584 330
+rect 857 309 872 330
+rect 1001 309 1016 330
+rect 1145 309 1160 330
+rect 1433 309 1448 330
+rect 137 206 152 225
+rect 425 206 440 225
+rect 569 206 584 225
+rect 857 206 872 225
+rect 1001 206 1016 225
+rect 1145 206 1160 225
+rect 1433 206 1448 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 593 206
+rect 560 181 568 198
+rect 585 181 593 198
+rect 560 173 593 181
+rect 848 198 881 206
+rect 848 181 856 198
+rect 873 181 881 198
+rect 848 173 881 181
+rect 992 198 1025 206
+rect 992 181 1000 198
+rect 1017 181 1025 198
+rect 992 173 1025 181
+rect 1136 198 1169 206
+rect 1136 181 1144 198
+rect 1161 181 1169 198
+rect 1136 173 1169 181
+rect 1424 198 1457 206
+rect 1424 181 1432 198
+rect 1449 181 1457 198
+rect 1424 173 1457 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
+rect 848 103 881 111
+rect 848 86 856 103
+rect 873 86 881 103
+rect 848 78 881 86
+rect 992 103 1025 111
+rect 992 86 1000 103
+rect 1017 86 1025 103
+rect 992 78 1025 86
+rect 1136 103 1169 111
+rect 1136 86 1144 103
+rect 1161 86 1169 103
+rect 1136 78 1169 86
+rect 1424 103 1457 111
+rect 1424 86 1432 103
+rect 1449 86 1457 103
+rect 1424 78 1457 86
+rect 137 66 152 78
+rect 425 66 440 78
+rect 569 66 584 78
+rect 857 66 872 78
+rect 1001 66 1016 78
+rect 1145 66 1160 78
+rect 1433 66 1448 78
+rect 137 11 152 24
+rect 425 11 440 24
+rect 569 11 584 24
+rect 857 11 872 24
+rect 1001 11 1016 24
+rect 1145 11 1160 24
+rect 1433 11 1448 24
<< polycont >>
-rect 136 86 153 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 856 86 873 103
-rect 1000 86 1017 103
-rect 1144 86 1161 103
-rect 1432 86 1449 103
rect 136 181 153 198
rect 424 181 441 198
rect 568 181 585 198
@@ -267,93 +245,396 @@
rect 1000 181 1017 198
rect 1144 181 1161 198
rect 1432 181 1449 198
-<< pdiffc >>
-rect 184 221 201 238
-rect 352 221 369 238
-rect 616 221 633 238
-rect 928 221 945 238
-rect 952 221 969 238
-rect 1048 221 1065 238
-rect 1072 221 1089 238
-rect 1480 221 1497 238
-rect 64 289 81 306
+rect 136 86 153 103
+rect 424 86 441 103
+rect 568 86 585 103
+rect 856 86 873 103
+rect 1000 86 1017 103
+rect 1144 86 1161 103
+rect 1432 86 1449 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 464 306 497 314
+rect 464 289 472 306
+rect 489 289 497 306
+rect 464 281 497 289
+rect 776 289 784 314
+rect 801 289 809 314
+rect 776 281 809 289
+rect 1184 306 1217 314
+rect 1184 289 1192 306
+rect 1209 289 1217 306
+rect 1184 281 1217 289
+rect 1352 306 1385 314
+rect 1352 289 1360 306
+rect 1377 289 1385 306
+rect 1352 281 1385 289
+rect 56 238 89 246
+rect 56 221 64 238
+rect 81 221 89 238
+rect 56 213 89 221
+rect 344 238 377 246
+rect 344 221 352 238
+rect 369 221 377 238
+rect 344 213 377 221
+rect 568 206 585 262
+rect 608 238 641 246
+rect 608 221 616 238
+rect 633 221 641 238
+rect 608 213 641 221
+rect 944 238 977 246
+rect 944 221 952 238
+rect 969 223 977 238
+rect 1472 238 1505 246
+rect 1472 223 1480 238
+rect 969 221 975 223
+rect 944 213 975 221
+rect 1474 221 1480 223
+rect 1497 221 1505 238
+rect 1474 213 1505 221
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 591 206
+rect 560 181 568 198
+rect 585 196 591 198
+rect 848 198 881 206
+rect 585 181 593 196
+rect 560 173 593 181
+rect 848 181 856 198
+rect 873 181 881 198
+rect 848 173 881 181
+rect 992 198 1025 206
+rect 992 181 1000 198
+rect 1017 181 1025 198
+rect 992 173 1025 181
+rect 1136 198 1169 206
+rect 1136 181 1144 198
+rect 1161 181 1169 198
+rect 1136 173 1169 181
+rect 1424 198 1457 206
+rect 1424 181 1432 198
+rect 1449 181 1457 198
+rect 1424 173 1457 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
+rect 848 103 881 111
+rect 848 86 856 103
+rect 873 86 881 103
+rect 848 78 881 86
+rect 992 103 1025 111
+rect 992 86 1000 103
+rect 1017 86 1025 103
+rect 992 78 1025 86
+rect 1136 103 1169 111
+rect 1136 86 1144 103
+rect 1161 86 1169 103
+rect 1136 78 1169 86
+rect 1424 103 1457 111
+rect 1424 86 1432 103
+rect 1449 88 1457 103
+rect 1449 86 1455 88
+rect 1424 78 1455 86
+rect 56 63 89 71
+rect 56 46 64 63
+rect 81 46 89 63
+rect 56 38 89 46
+rect 344 63 377 71
+rect 344 46 352 63
+rect 369 46 377 63
+rect 1042 63 1073 71
+rect 1042 61 1048 63
+rect 176 36 209 44
+rect 344 38 377 46
+rect 1040 46 1048 61
+rect 1065 46 1073 63
+rect 176 19 184 36
+rect 201 19 209 36
+rect 176 11 209 19
+rect 608 36 641 44
+rect 608 11 616 36
+rect 633 11 641 36
+rect 776 36 809 44
+rect 776 11 784 36
+rect 801 11 809 36
+rect 944 36 977 44
+rect 1040 39 1073 46
+rect 1472 63 1505 71
+rect 1472 46 1480 63
+rect 1497 46 1505 63
+rect 944 19 952 36
+rect 969 22 977 36
+rect 1184 36 1217 44
+rect 1184 22 1192 36
+rect 969 19 1192 22
+rect 1209 19 1217 36
+rect 944 11 1217 19
+rect 1352 36 1385 44
+rect 1472 38 1505 46
+rect 1352 11 1360 36
+rect 952 5 1209 11
+rect 1377 11 1385 36
+<< viali >>
+rect 184 289 201 306
rect 472 289 489 306
-rect 496 289 513 306
-rect 784 289 801 306
+rect 784 306 801 319
+rect 784 302 801 306
rect 1192 289 1209 306
rect 1360 289 1377 306
-<< ndiffc >>
-rect 64 19 81 36
-rect 496 19 513 36
-rect 520 19 537 36
-rect 616 19 633 36
-rect 784 19 801 36
-rect 904 19 921 36
-rect 928 19 945 36
-rect 1048 19 1065 36
-rect 1072 19 1089 36
-rect 1360 19 1377 36
-rect 184 46 201 63
+rect 568 262 585 279
+rect 64 221 81 238
+rect 352 221 369 238
+rect 616 221 633 238
+rect 952 221 969 238
+rect 1480 221 1497 238
+rect 136 181 153 198
+rect 424 181 441 198
+rect 568 181 585 198
+rect 856 181 873 198
+rect 1000 181 1017 198
+rect 1144 181 1161 198
+rect 1432 181 1449 198
+rect 136 86 153 103
+rect 424 86 441 103
+rect 568 86 585 103
+rect 856 86 873 103
+rect 1000 86 1017 103
+rect 1144 86 1161 103
+rect 1432 86 1449 103
+rect 64 46 81 63
rect 352 46 369 63
-rect 952 46 969 63
rect 1048 46 1065 63
-rect 1192 46 1209 63
+rect 184 19 201 36
+rect 616 19 633 22
+rect 616 5 633 19
+rect 784 19 801 22
+rect 784 5 801 19
rect 1480 46 1497 63
-<< nplus >>
-<< pplus >>
+rect 1360 19 1377 22
+rect 1360 5 1377 19
+<< metal1 >>
+rect 0 319 1584 357
+rect 0 309 784 319
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 466 306 495 309
+rect 466 289 472 306
+rect 489 289 495 306
+rect 778 302 784 309
+rect 801 309 1584 319
+rect 801 302 807 309
+rect 778 296 807 302
+rect 1186 306 1215 309
+rect 466 283 495 289
+rect 1186 289 1192 306
+rect 1209 289 1215 306
+rect 562 279 591 285
+rect 1186 283 1215 289
+rect 1354 306 1383 309
+rect 1354 289 1360 306
+rect 1377 289 1383 306
+rect 1354 283 1383 289
+rect 562 262 568 279
+rect 585 277 591 279
+rect 585 263 1159 277
+rect 585 262 591 263
+rect 562 256 591 262
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 221 87 238
+rect 58 215 87 221
+rect 346 238 375 244
+rect 346 221 352 238
+rect 369 237 375 238
+rect 610 238 639 244
+rect 610 237 616 238
+rect 369 223 616 237
+rect 369 221 375 223
+rect 346 215 375 221
+rect 610 221 616 223
+rect 633 237 639 238
+rect 946 238 975 244
+rect 633 223 871 237
+rect 633 221 639 223
+rect 610 215 639 221
+rect 65 69 79 215
+rect 130 198 159 204
+rect 130 181 136 198
+rect 153 181 159 198
+rect 130 175 159 181
+rect 137 109 151 175
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 102 159 103
+rect 353 102 367 215
+rect 857 204 871 223
+rect 946 221 952 238
+rect 969 237 975 238
+rect 969 223 1063 237
+rect 969 221 975 223
+rect 946 215 975 221
+rect 418 198 447 204
+rect 418 181 424 198
+rect 441 181 447 198
+rect 418 175 447 181
+rect 562 198 591 204
+rect 562 181 568 198
+rect 585 181 591 198
+rect 562 175 591 181
+rect 850 198 879 204
+rect 850 181 856 198
+rect 873 181 879 198
+rect 850 175 879 181
+rect 994 198 1023 204
+rect 994 181 1000 198
+rect 1017 181 1023 198
+rect 994 175 1023 181
+rect 425 109 439 175
+rect 569 109 583 175
+rect 857 109 871 175
+rect 1001 109 1015 175
+rect 153 88 367 102
+rect 153 86 159 88
+rect 130 80 159 86
+rect 353 69 367 88
+rect 418 103 447 109
+rect 418 86 424 103
+rect 441 86 447 103
+rect 418 80 447 86
+rect 562 103 591 109
+rect 562 86 568 103
+rect 585 86 591 103
+rect 562 80 591 86
+rect 850 103 879 109
+rect 850 86 856 103
+rect 873 86 879 103
+rect 850 80 879 86
+rect 994 103 1023 109
+rect 994 86 1000 103
+rect 1017 86 1023 103
+rect 994 80 1023 86
+rect 58 63 87 69
+rect 58 46 64 63
+rect 81 46 87 63
+rect 58 40 87 46
+rect 346 63 375 69
+rect 346 46 352 63
+rect 369 46 375 63
+rect 425 61 439 80
+rect 1001 61 1015 80
+rect 1049 69 1063 223
+rect 1145 204 1159 263
+rect 1474 238 1503 244
+rect 1474 221 1480 238
+rect 1497 221 1503 238
+rect 1474 215 1503 221
+rect 1138 198 1167 204
+rect 1138 181 1144 198
+rect 1161 181 1167 198
+rect 1138 175 1167 181
+rect 1426 198 1455 204
+rect 1426 181 1432 198
+rect 1449 181 1455 198
+rect 1426 175 1455 181
+rect 1145 109 1159 175
+rect 1433 109 1447 175
+rect 1138 103 1167 109
+rect 1138 86 1144 103
+rect 1161 86 1167 103
+rect 1138 80 1167 86
+rect 1426 103 1455 109
+rect 1426 86 1432 103
+rect 1449 86 1455 103
+rect 1426 80 1455 86
+rect 425 47 1015 61
+rect 1042 63 1071 69
+rect 178 36 207 42
+rect 346 40 375 46
+rect 1042 46 1048 63
+rect 1065 61 1071 63
+rect 1433 61 1447 80
+rect 1481 69 1495 215
+rect 1065 47 1447 61
+rect 1474 63 1503 69
+rect 1065 46 1071 47
+rect 1042 40 1071 46
+rect 1474 46 1480 63
+rect 1497 46 1503 63
+rect 1474 40 1503 46
+rect 178 24 184 36
+rect 0 19 184 24
+rect 201 24 207 36
+rect 610 24 639 28
+rect 778 24 807 28
+rect 1354 24 1383 28
+rect 201 22 1584 24
+rect 201 19 616 22
+rect 0 5 616 19
+rect 633 5 784 22
+rect 801 5 1360 22
+rect 1377 5 1584 22
+rect 0 -24 1584 5
<< labels >>
-rlabel met1 0 309 1584 357 0 VDD
+rlabel metal1 0 309 1584 357 0 VDD
port 1 se
-rlabel met1 0 -24 1584 24 0 GND
+rlabel metal1 0 -24 1584 24 0 GND
port 2 se
-rlabel met1 1474 40 1503 69 0 YS
+rlabel metal1 1474 40 1503 69 0 YS
port 3 se
-rlabel met1 1481 69 1495 215 0 YS
+rlabel metal1 1481 69 1495 215 0 YS
port 4 se
-rlabel met1 1474 215 1503 244 0 YS
+rlabel metal1 1474 215 1503 244 0 YS
port 5 se
-rlabel met1 178 40 207 47 0 YC
+rlabel metal1 58 40 87 69 0 YC
port 6 se
-rlabel met1 89 47 207 61 0 YC
+rlabel metal1 65 69 79 215 0 YC
port 7 se
-rlabel met1 178 61 207 69 0 YC
+rlabel metal1 58 215 87 244 0 YC
port 8 se
-rlabel met1 89 61 103 223 0 YC
+rlabel metal1 562 80 591 109 0 A
port 9 se
-rlabel met1 178 215 207 223 0 YC
+rlabel metal1 569 109 583 175 0 A
port 10 se
-rlabel met1 89 223 207 237 0 YC
+rlabel metal1 562 175 591 204 0 A
port 11 se
-rlabel met1 178 237 207 244 0 YC
+rlabel metal1 425 47 1015 61 0 B
port 12 se
-rlabel met1 425 47 919 53 0 B
+rlabel metal1 425 61 439 80 0 B
port 13 se
-rlabel met1 425 53 927 61 0 B
+rlabel metal1 1001 61 1015 80 0 B
port 14 se
-rlabel met1 425 61 439 80 0 B
+rlabel metal1 418 80 447 109 0 B
port 15 se
-rlabel met1 898 61 927 82 0 B
+rlabel metal1 994 80 1023 109 0 B
port 16 se
-rlabel met1 418 80 447 109 0 B
+rlabel metal1 425 109 439 175 0 B
port 17 se
-rlabel met1 425 109 439 175 0 B
+rlabel metal1 1001 109 1015 175 0 B
port 18 se
-rlabel met1 418 175 447 204 0 B
+rlabel metal1 418 175 447 204 0 B
port 19 se
-rlabel met1 562 80 591 101 0 A
+rlabel metal1 994 175 1023 204 0 B
port 20 se
-rlabel met1 1138 80 1167 101 0 A
-port 21 se
-rlabel met1 562 101 1167 109 0 A
-port 22 se
-rlabel met1 569 109 1159 115 0 A
-port 23 se
-rlabel met1 569 115 583 175 0 A
-port 24 se
-rlabel met1 1145 115 1159 175 0 A
-port 25 se
-rlabel met1 562 175 591 204 0 A
-port 26 se
-rlabel met1 1138 175 1167 204 0 A
-port 27 se
+<< properties >>
+string FIXED_BBOX 0 0 1584 333
<< end >>
diff --git a/cells/mag/INV.mag b/cells/mag/INV.mag
index dea8d67..721b65b 100644
--- a/cells/mag/INV.mag
+++ b/cells/mag/INV.mag
@@ -1,10 +1,9 @@
magic
# Generated by librecell
tech sky130A
-timestamp 1621175710
+timestamp 1623283835
<< nwell >>
rect 0 179 288 333
-rect 27 333 262 340
<< viali >>
rect 184 19 201 36
rect 64 46 81 63
@@ -66,8 +65,6 @@
<< ndiffc >>
rect 184 19 201 36
rect 64 46 81 63
-<< nplus >>
-<< pplus >>
<< labels >>
rlabel met1 0 309 288 357 0 VDD
port 1 se
diff --git a/cells/mag/INVX1.mag b/cells/mag/INVX1.mag
index 1c42d38..67f5507 100644
--- a/cells/mag/INVX1.mag
+++ b/cells/mag/INVX1.mag
@@ -1,17 +1,16 @@
magic
# Generated by librecell
tech sky130A
-timestamp 1620330136
+timestamp 1623283883
<< nwell >>
rect 0 179 288 333
-rect 27 333 262 340
<< viali >>
-rect 64 19 81 36
-rect 184 46 201 63
+rect 184 19 201 36
+rect 64 46 81 63
rect 136 86 153 103
rect 136 181 153 198
-rect 184 221 201 238
-rect 64 289 81 306
+rect 64 221 81 238
+rect 184 289 201 306
<< poly >>
rect 137 11 152 78
rect 128 78 161 111
@@ -20,22 +19,22 @@
<< properties >>
string FIXED_BBOX 0 0 288 333
<< li1 >>
-rect 56 11 89 44
-rect 176 38 209 71
+rect 176 11 209 44
+rect 56 38 89 71
rect 128 78 161 111
rect 128 173 161 206
-rect 176 213 209 246
-rect 56 281 89 314
+rect 56 213 89 246
+rect 176 281 209 314
<< met1 >>
rect 0 -24 288 24
-rect 58 24 87 42
+rect 178 24 207 42
rect 130 80 159 109
rect 137 109 151 175
rect 130 175 159 204
-rect 178 40 207 69
-rect 185 69 199 215
-rect 178 215 207 244
-rect 58 283 87 309
+rect 58 40 87 69
+rect 65 69 79 215
+rect 58 215 87 244
+rect 178 283 207 309
rect 0 309 288 357
<< li1 >>
<< met1 >>
@@ -45,39 +44,37 @@
rect 130 80 159 109
rect 137 109 151 175
rect 130 175 159 204
-rect 178 40 207 69
-rect 185 69 199 215
-rect 178 215 207 244
+rect 58 40 87 69
+rect 65 69 79 215
+rect 58 215 87 244
rect 0 309 288 357
<< ndiffusion >>
-rect 58 13 87 24
+rect 178 13 207 24
rect 58 24 231 66
-rect 178 66 207 69
+rect 58 66 87 69
<< pdiffusion >>
-rect 178 215 207 225
+rect 58 215 87 225
rect 58 225 231 309
-rect 58 309 87 312
+rect 178 309 207 312
<< polycont >>
rect 136 86 153 103
rect 136 181 153 198
<< pdiffc >>
-rect 184 221 201 238
-rect 64 289 81 306
+rect 64 221 81 238
+rect 184 289 201 306
<< ndiffc >>
-rect 64 19 81 36
-rect 184 46 201 63
-<< nplus >>
-<< pplus >>
+rect 184 19 201 36
+rect 64 46 81 63
<< labels >>
rlabel met1 0 309 288 357 0 VDD
port 1 se
rlabel met1 0 -24 288 24 0 GND
port 2 se
-rlabel met1 178 40 207 69 0 Y
+rlabel met1 58 40 87 69 0 Y
port 3 se
-rlabel met1 185 69 199 215 0 Y
+rlabel met1 65 69 79 215 0 Y
port 4 se
-rlabel met1 178 215 207 244 0 Y
+rlabel met1 58 215 87 244 0 Y
port 5 se
rlabel met1 130 80 159 109 0 A
port 6 se
diff --git a/cells/mag/INVX2.mag b/cells/mag/INVX2.mag
index 5105b3a..1c265a9 100644
--- a/cells/mag/INVX2.mag
+++ b/cells/mag/INVX2.mag
@@ -1,10 +1,9 @@
magic
# Generated by librecell
tech sky130A
-timestamp 1621175817
+timestamp 1623283932
<< nwell >>
rect 0 179 288 333
-rect 27 333 262 340
<< viali >>
rect 184 19 201 36
rect 64 46 81 63
@@ -66,8 +65,6 @@
<< ndiffc >>
rect 184 19 201 36
rect 64 46 81 63
-<< nplus >>
-<< pplus >>
<< labels >>
rlabel met1 0 309 288 357 0 VDD
port 1 se
diff --git a/cells/mag/INVX4.mag b/cells/mag/INVX4.mag
index 54aa9c6..1554e6a 100644
--- a/cells/mag/INVX4.mag
+++ b/cells/mag/INVX4.mag
@@ -1,164 +1,235 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621175965
+timestamp 1623602962
<< nwell >>
rect 0 179 432 333
-rect 27 333 406 340
-<< viali >>
-rect 184 19 201 36
-rect 232 19 249 36
-rect 64 46 81 63
-rect 328 46 345 63
-rect 136 86 153 103
-rect 280 86 297 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 64 221 81 238
-rect 328 221 345 238
-rect 184 289 201 306
-rect 232 289 249 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 128 173 161 206
-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-<< properties >>
-string FIXED_BBOX 0 0 432 333
-<< li1 >>
-rect 176 11 209 44
-rect 224 11 257 44
-rect 56 38 89 71
-rect 320 38 353 71
-rect 128 78 161 111
-rect 272 78 305 111
-rect 128 173 161 206
-rect 272 173 305 206
-rect 56 213 89 246
-rect 320 213 353 246
-rect 176 281 209 314
-rect 224 281 257 314
-<< met1 >>
-rect 0 -24 432 24
-rect 178 24 207 42
-rect 226 24 255 42
-rect 130 80 159 109
-rect 274 80 303 109
-rect 137 109 151 175
-rect 281 109 295 175
-rect 130 175 159 182
-rect 274 175 303 182
-rect 130 182 303 196
-rect 130 196 159 204
-rect 274 196 303 204
-rect 58 40 87 69
-rect 322 40 351 69
-rect 65 69 79 215
-rect 329 69 343 215
-rect 58 215 87 223
-rect 322 215 351 223
-rect 58 223 351 237
-rect 58 237 87 244
-rect 322 237 351 244
-rect 178 283 207 309
-rect 226 283 255 309
-rect 0 309 432 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 432 24
-rect 130 80 159 109
-rect 274 80 303 109
-rect 137 109 151 175
-rect 281 109 295 175
-rect 130 175 159 182
-rect 274 175 303 182
-rect 130 182 303 196
-rect 130 196 159 204
-rect 274 196 303 204
-rect 58 40 87 69
-rect 322 40 351 69
-rect 65 69 79 215
-rect 329 69 343 215
-rect 58 215 87 223
-rect 322 215 351 223
-rect 58 223 351 237
-rect 58 237 87 244
-rect 322 237 351 244
-rect 0 309 432 357
-<< ndiffusion >>
-rect 178 13 207 24
-rect 226 13 255 24
-rect 58 24 375 66
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+<< ndiff >>
rect 58 66 87 69
rect 322 66 351 69
-<< pdiffusion >>
-rect 58 215 87 225
-rect 322 215 351 225
-rect 58 225 375 309
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 281 36
+rect 296 63 375 66
+rect 296 46 328 63
+rect 345 46 375 63
+rect 296 24 375 46
+rect 201 19 207 24
+rect 178 13 207 19
+<< pdiff >>
rect 178 309 207 312
-rect 226 309 255 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 136 181 153 198
-rect 280 181 297 198
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 238 375 309
+rect 296 225 328 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 322 221 328 225
+rect 345 225 375 238
+rect 345 221 351 225
+rect 322 215 351 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 184 19 201 36
+rect 328 46 345 63
<< pdiffc >>
rect 64 221 81 238
-rect 328 221 345 238
rect 184 289 201 306
-rect 232 289 249 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 232 19 249 36
+rect 328 221 345 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
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+rect 297 181 305 198
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+rect 128 103 161 111
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+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 137 11 152 24
+rect 281 11 296 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 56 238 89 246
+rect 56 221 64 238
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+rect 56 213 89 221
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+rect 345 46 353 63
+rect 176 36 209 44
+rect 320 38 353 46
+rect 176 19 184 36
+rect 201 19 209 36
+rect 176 11 209 19
+<< viali >>
+rect 184 289 201 306
+rect 64 221 81 238
+rect 328 221 345 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
rect 64 46 81 63
rect 328 46 345 63
-<< nplus >>
-<< pplus >>
+rect 184 19 201 36
+<< metal1 >>
+rect 0 309 432 357
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 237 87 238
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+rect 322 237 328 238
+rect 81 223 328 237
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+rect 322 221 328 223
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+rect 65 69 79 215
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+rect 322 63 351 69
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+rect 178 36 207 42
+rect 322 40 351 46
+rect 178 24 184 36
+rect 0 19 184 24
+rect 201 24 207 36
+rect 201 19 432 24
+rect 0 -24 432 19
<< labels >>
-rlabel met1 0 309 432 357 0 VDD
+rlabel metal1 0 309 432 357 0 VDD
port 1 se
-rlabel met1 0 -24 432 24 0 GND
+rlabel metal1 0 -24 432 24 0 GND
port 2 se
-rlabel met1 58 40 87 69 0 Y
+rlabel metal1 58 40 87 69 0 Y
port 3 se
-rlabel met1 322 40 351 69 0 Y
+rlabel metal1 322 40 351 69 0 Y
port 4 se
-rlabel met1 65 69 79 215 0 Y
+rlabel metal1 65 69 79 215 0 Y
port 5 se
-rlabel met1 329 69 343 215 0 Y
+rlabel metal1 329 69 343 215 0 Y
port 6 se
-rlabel met1 58 215 87 223 0 Y
+rlabel metal1 58 215 87 223 0 Y
port 7 se
-rlabel met1 322 215 351 223 0 Y
+rlabel metal1 322 215 351 223 0 Y
port 8 se
-rlabel met1 58 223 351 237 0 Y
+rlabel metal1 58 223 351 237 0 Y
port 9 se
-rlabel met1 58 237 87 244 0 Y
+rlabel metal1 58 237 87 244 0 Y
port 10 se
-rlabel met1 322 237 351 244 0 Y
+rlabel metal1 322 237 351 244 0 Y
port 11 se
-rlabel met1 130 80 159 109 0 A
+rlabel metal1 130 80 159 88 0 A
port 12 se
-rlabel met1 274 80 303 109 0 A
+rlabel metal1 274 80 303 88 0 A
port 13 se
-rlabel met1 137 109 151 175 0 A
+rlabel metal1 130 88 303 102 0 A
port 14 se
-rlabel met1 281 109 295 175 0 A
+rlabel metal1 130 102 159 109 0 A
port 15 se
-rlabel met1 130 175 159 182 0 A
+rlabel metal1 274 102 303 109 0 A
port 16 se
-rlabel met1 274 175 303 182 0 A
+rlabel metal1 137 109 151 175 0 A
port 17 se
-rlabel met1 130 182 303 196 0 A
+rlabel metal1 281 109 295 175 0 A
port 18 se
-rlabel met1 130 196 159 204 0 A
+rlabel metal1 130 175 159 204 0 A
port 19 se
-rlabel met1 274 196 303 204 0 A
+rlabel metal1 274 175 303 204 0 A
port 20 se
+<< properties >>
+string FIXED_BBOX 0 0 432 333
<< end >>
diff --git a/cells/mag/INVX8.mag b/cells/mag/INVX8.mag
index cc3040a..1d6a1d5 100644
--- a/cells/mag/INVX8.mag
+++ b/cells/mag/INVX8.mag
@@ -1,278 +1,406 @@
magic
-# Generated by librecell
tech sky130A
-timestamp 1621176318
+timestamp 1623602966
<< nwell >>
rect 0 179 720 333
-rect 27 333 694 340
-<< viali >>
-rect 184 5 201 22
-rect 472 19 489 36
-rect 496 19 513 36
-rect 88 46 105 63
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+rect 569 24 584 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+rect 569 225 584 309
+<< ndiff >>
+rect 58 66 87 69
+rect 322 66 351 69
+rect 610 66 639 69
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 281 36
+rect 296 63 425 66
+rect 296 46 328 63
+rect 345 46 425 63
+rect 296 24 425 46
+rect 440 36 569 66
+rect 440 24 472 36
+rect 201 19 207 24
+rect 178 13 207 19
+rect 466 19 472 24
+rect 489 24 569 36
+rect 584 63 663 66
+rect 584 46 616 63
+rect 633 46 663 63
+rect 584 24 663 46
+rect 489 19 495 24
+rect 466 13 495 19
+<< pdiff >>
+rect 178 309 207 312
+rect 466 309 495 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 238 425 309
+rect 296 225 328 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 322 221 328 225
+rect 345 225 425 238
+rect 440 306 569 309
+rect 440 289 472 306
+rect 489 289 569 306
+rect 440 225 569 289
+rect 584 238 663 309
+rect 584 225 616 238
+rect 345 221 351 225
+rect 322 215 351 221
+rect 610 221 616 225
+rect 633 225 663 238
+rect 633 221 639 225
+rect 610 215 639 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 184 19 201 36
rect 328 46 345 63
-rect 352 46 369 63
+rect 472 19 489 36
rect 616 46 633 63
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 328 221 345 238
+rect 472 289 489 306
+rect 616 221 633 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 569 309 584 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 425 206 440 225
+rect 569 206 584 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
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+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 593 206
+rect 560 181 568 198
+rect 585 181 593 198
+rect 560 173 593 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 425 66 440 78
+rect 569 66 584 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
+rect 569 11 584 24
+<< polycont >>
rect 136 181 153 198
rect 280 181 297 198
rect 424 181 441 198
rect 568 181 585 198
-rect 88 221 105 238
-rect 328 221 345 238
-rect 376 221 393 238
-rect 616 221 633 238
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 568 86 585 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 464 306 497 314
+rect 464 289 472 306
+rect 489 289 497 306
+rect 464 281 497 289
+rect 56 238 89 246
+rect 56 221 64 238
+rect 81 221 89 238
+rect 320 238 353 246
+rect 320 223 328 238
+rect 56 213 89 221
+rect 322 221 328 223
+rect 345 221 353 238
+rect 608 238 641 246
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+rect 322 213 353 221
+rect 610 221 616 223
+rect 633 221 641 238
+rect 610 213 641 221
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
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+rect 416 198 449 206
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+rect 560 198 593 206
+rect 560 181 568 198
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+rect 560 173 593 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
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+rect 297 88 305 103
+rect 416 103 449 111
+rect 297 86 303 88
+rect 272 78 303 86
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
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+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
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+rect 81 46 89 63
+rect 56 38 89 46
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+rect 320 46 328 63
+rect 345 46 353 63
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+rect 610 61 616 63
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+rect 633 46 641 63
+rect 176 11 184 36
+rect 201 11 209 36
+rect 464 36 497 44
+rect 608 38 641 46
+rect 464 11 472 36
+rect 489 11 497 36
+<< viali >>
rect 184 289 201 306
-rect 232 289 249 306
rect 472 289 489 306
-rect 496 289 513 306
-<< poly >>
-rect 137 11 152 78
-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 569 11 584 78
-rect 560 78 593 111
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-rect 137 206 152 330
-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-rect 560 173 593 206
-rect 569 206 584 330
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+rect 64 46 81 63
+rect 328 46 345 63
+rect 616 46 633 63
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+rect 184 5 201 19
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+<< metal1 >>
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+rect 201 289 207 306
+rect 178 283 207 289
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+rect 466 289 472 306
+rect 489 289 495 306
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+rect 178 24 207 28
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+rect 0 22 720 24
+rect 0 5 184 22
+rect 201 5 472 22
+rect 489 5 720 22
+rect 0 -24 720 5
+<< labels >>
+rlabel metal1 0 309 720 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 720 24 0 GND
+port 2 se
+rlabel metal1 58 40 87 47 0 Y
+port 3 se
+rlabel metal1 322 40 351 47 0 Y
+port 4 se
+rlabel metal1 610 40 639 47 0 Y
+port 5 se
+rlabel metal1 58 47 639 61 0 Y
+port 6 se
+rlabel metal1 58 61 87 69 0 Y
+port 7 se
+rlabel metal1 322 61 351 69 0 Y
+port 8 se
+rlabel metal1 610 61 639 69 0 Y
+port 9 se
+rlabel metal1 65 69 79 215 0 Y
+port 10 se
+rlabel metal1 617 69 631 215 0 Y
+port 11 se
+rlabel metal1 58 215 87 223 0 Y
+port 12 se
+rlabel metal1 322 215 351 223 0 Y
+port 13 se
+rlabel metal1 58 223 351 237 0 Y
+port 14 se
+rlabel metal1 58 237 87 244 0 Y
+port 15 se
+rlabel metal1 322 237 351 244 0 Y
+port 16 se
+rlabel metal1 610 215 639 244 0 Y
+port 17 se
+rlabel metal1 130 80 159 109 0 A
+port 18 se
+rlabel metal1 274 80 303 109 0 A
+port 19 se
+rlabel metal1 418 80 447 109 0 A
+port 20 se
+rlabel metal1 562 80 591 109 0 A
+port 21 se
+rlabel metal1 137 109 151 175 0 A
+port 22 se
+rlabel metal1 281 109 295 175 0 A
+port 23 se
+rlabel metal1 425 109 439 175 0 A
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+rlabel metal1 569 109 583 175 0 A
+port 25 se
+rlabel metal1 130 175 159 182 0 A
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+rlabel metal1 274 175 303 182 0 A
+port 27 se
+rlabel metal1 418 175 447 182 0 A
+port 28 se
+rlabel metal1 562 175 591 182 0 A
+port 29 se
+rlabel metal1 130 182 591 196 0 A
+port 30 se
+rlabel metal1 130 196 159 204 0 A
+port 31 se
+rlabel metal1 274 196 303 204 0 A
+port 32 se
+rlabel metal1 418 196 447 204 0 A
+port 33 se
+rlabel metal1 562 196 591 204 0 A
+port 34 se
<< properties >>
string FIXED_BBOX 0 0 720 333
-<< li1 >>
-rect 184 5 201 11
-rect 176 11 209 19
-rect 224 11 257 19
-rect 176 19 257 36
-rect 176 36 209 44
-rect 224 36 257 44
-rect 464 11 521 44
-rect 80 38 113 71
-rect 320 38 377 71
-rect 608 38 641 71
-rect 128 78 161 111
-rect 272 78 305 111
-rect 416 78 449 111
-rect 560 78 593 111
-rect 128 173 161 206
-rect 272 173 305 206
-rect 416 173 449 206
-rect 560 173 593 206
-rect 80 213 113 246
-rect 320 213 353 246
-rect 368 213 401 246
-rect 608 213 641 246
-rect 176 281 209 314
-rect 224 281 257 314
-rect 464 281 521 314
-<< met1 >>
-rect 0 -24 720 24
-rect 178 24 207 28
-rect 466 24 519 42
-rect 130 80 159 88
-rect 274 80 303 88
-rect 418 80 447 88
-rect 562 80 591 88
-rect 130 88 591 102
-rect 130 102 159 109
-rect 274 102 303 109
-rect 418 102 447 109
-rect 562 102 591 109
-rect 137 109 151 175
-rect 281 109 295 175
-rect 425 109 439 175
-rect 569 109 583 175
-rect 130 175 159 204
-rect 274 175 303 204
-rect 418 175 447 204
-rect 562 175 591 204
-rect 82 40 111 47
-rect 322 40 375 47
-rect 82 47 375 61
-rect 82 61 111 69
-rect 322 61 375 69
-rect 610 40 639 69
-rect 89 69 103 215
-rect 617 69 631 215
-rect 82 215 111 223
-rect 322 215 351 223
-rect 370 215 399 223
-rect 610 215 639 223
-rect 82 223 639 237
-rect 82 237 111 244
-rect 322 237 351 244
-rect 370 237 399 244
-rect 610 237 639 244
-rect 178 283 207 309
-rect 226 283 255 309
-rect 466 283 519 309
-rect 0 309 720 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 720 24
-rect 130 80 159 88
-rect 274 80 303 88
-rect 418 80 447 88
-rect 562 80 591 88
-rect 130 88 591 102
-rect 130 102 159 109
-rect 274 102 303 109
-rect 418 102 447 109
-rect 562 102 591 109
-rect 137 109 151 175
-rect 281 109 295 175
-rect 425 109 439 175
-rect 569 109 583 175
-rect 130 175 159 204
-rect 274 175 303 204
-rect 418 175 447 204
-rect 562 175 591 204
-rect 82 40 111 47
-rect 322 40 375 47
-rect 82 47 375 61
-rect 82 61 111 69
-rect 322 61 375 69
-rect 610 40 639 69
-rect 89 69 103 215
-rect 617 69 631 215
-rect 82 215 111 223
-rect 322 215 351 223
-rect 370 215 399 223
-rect 610 215 639 223
-rect 82 223 639 237
-rect 82 237 111 244
-rect 322 237 351 244
-rect 370 237 399 244
-rect 610 237 639 244
-rect 0 309 720 357
-<< ndiffusion >>
-rect 178 13 207 24
-rect 226 13 255 24
-rect 466 13 519 24
-rect 58 24 663 66
-rect 82 66 111 69
-rect 322 66 375 69
-rect 610 66 639 69
-<< pdiffusion >>
-rect 82 215 111 225
-rect 322 215 351 225
-rect 370 215 399 225
-rect 610 215 639 225
-rect 58 225 663 309
-rect 178 309 207 312
-rect 226 309 255 312
-rect 466 309 519 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 424 181 441 198
-rect 568 181 585 198
-<< pdiffc >>
-rect 88 221 105 238
-rect 328 221 345 238
-rect 376 221 393 238
-rect 616 221 633 238
-rect 184 289 201 306
-rect 232 289 249 306
-rect 472 289 489 306
-rect 496 289 513 306
-<< ndiffc >>
-rect 184 19 201 36
-rect 232 19 249 36
-rect 472 19 489 36
-rect 496 19 513 36
-rect 88 46 105 63
-rect 328 46 345 63
-rect 352 46 369 63
-rect 616 46 633 63
-<< nplus >>
-<< pplus >>
-<< labels >>
-rlabel met1 0 309 720 357 0 VDD
-port 1 se
-rlabel met1 0 -24 720 24 0 GND
-port 2 se
-rlabel met1 82 40 111 47 0 Y
-port 3 se
-rlabel met1 322 40 375 47 0 Y
-port 4 se
-rlabel met1 82 47 375 61 0 Y
-port 5 se
-rlabel met1 82 61 111 69 0 Y
-port 6 se
-rlabel met1 322 61 375 69 0 Y
-port 7 se
-rlabel met1 610 40 639 69 0 Y
-port 8 se
-rlabel met1 89 69 103 215 0 Y
-port 9 se
-rlabel met1 617 69 631 215 0 Y
-port 10 se
-rlabel met1 82 215 111 223 0 Y
-port 11 se
-rlabel met1 322 215 351 223 0 Y
-port 12 se
-rlabel met1 370 215 399 223 0 Y
-port 13 se
-rlabel met1 610 215 639 223 0 Y
-port 14 se
-rlabel met1 82 223 639 237 0 Y
-port 15 se
-rlabel met1 82 237 111 244 0 Y
-port 16 se
-rlabel met1 322 237 351 244 0 Y
-port 17 se
-rlabel met1 370 237 399 244 0 Y
-port 18 se
-rlabel met1 610 237 639 244 0 Y
-port 19 se
-rlabel met1 130 80 159 88 0 A
-port 20 se
-rlabel met1 274 80 303 88 0 A
-port 21 se
-rlabel met1 418 80 447 88 0 A
-port 22 se
-rlabel met1 562 80 591 88 0 A
-port 23 se
-rlabel met1 130 88 591 102 0 A
-port 24 se
-rlabel met1 130 102 159 109 0 A
-port 25 se
-rlabel met1 274 102 303 109 0 A
-port 26 se
-rlabel met1 418 102 447 109 0 A
-port 27 se
-rlabel met1 562 102 591 109 0 A
-port 28 se
-rlabel met1 137 109 151 175 0 A
-port 29 se
-rlabel met1 281 109 295 175 0 A
-port 30 se
-rlabel met1 425 109 439 175 0 A
-port 31 se
-rlabel met1 569 109 583 175 0 A
-port 32 se
-rlabel met1 130 175 159 204 0 A
-port 33 se
-rlabel met1 274 175 303 204 0 A
-port 34 se
-rlabel met1 418 175 447 204 0 A
-port 35 se
-rlabel met1 562 175 591 204 0 A
-port 36 se
<< end >>
diff --git a/cells/mag/LATCH.mag b/cells/mag/LATCH.mag
deleted file mode 100644
index c1efe44..0000000
--- a/cells/mag/LATCH.mag
+++ /dev/null
@@ -1,254 +0,0 @@
-magic
-# Generated by librecell
-tech sky130A
-timestamp 1621176781
-<< nwell >>
-rect 0 179 1008 333
-rect 27 333 982 340
-<< viali >>
-rect 184 19 201 36
-rect 208 19 225 36
-rect 760 19 777 36
-rect 784 19 801 36
-rect 64 46 81 63
-rect 472 46 489 63
-rect 904 46 921 63
-rect 136 86 153 103
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-rect 280 127 297 144
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-rect 64 221 81 238
-rect 352 221 369 238
-rect 376 221 393 238
-rect 472 221 489 238
-rect 496 221 513 238
-rect 640 221 657 238
-rect 664 221 681 238
-rect 904 221 921 238
-rect 184 289 201 306
-rect 208 289 225 306
-rect 760 289 777 306
-rect 784 289 801 306
-<< poly >>
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-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 425 11 440 78
-rect 416 78 449 111
-rect 569 11 584 78
-rect 560 78 593 111
-rect 713 11 728 78
-rect 704 78 737 111
-rect 857 11 872 78
-rect 848 78 881 111
-rect 128 173 161 206
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-rect 272 173 305 206
-rect 281 206 296 330
-rect 416 173 449 206
-rect 425 206 440 330
-rect 560 173 593 206
-rect 569 206 584 330
-rect 704 173 737 206
-rect 713 206 728 330
-rect 848 173 881 206
-rect 857 206 872 330
-<< properties >>
-string FIXED_BBOX 0 0 1008 333
-<< li1 >>
-rect 176 11 233 44
-rect 344 11 401 44
-rect 632 11 689 44
-rect 752 11 809 44
-rect 56 38 89 71
-rect 488 11 545 38
-rect 464 38 545 44
-rect 464 44 497 71
-rect 896 38 929 71
-rect 848 78 881 111
-rect 560 78 593 111
-rect 568 111 585 157
-rect 128 78 161 111
-rect 136 111 153 173
-rect 128 173 161 206
-rect 272 78 305 111
-rect 280 111 297 173
-rect 272 173 305 206
-rect 416 173 449 206
-rect 416 78 449 86
-rect 416 86 489 103
-rect 416 103 449 111
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-rect 472 181 593 198
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-rect 704 78 737 111
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-rect 704 173 737 206
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-rect 56 213 89 246
-rect 344 213 401 246
-rect 464 213 521 246
-rect 632 213 689 246
-rect 896 213 929 246
-rect 176 281 233 314
-rect 752 281 809 314
-<< met1 >>
-rect 0 -24 1008 24
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-rect 130 80 159 88
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-rect 130 102 159 109
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-rect 58 215 87 244
-rect 425 204 439 263
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-rect 425 263 583 277
-rect 178 283 231 309
-rect 754 283 807 309
-rect 0 309 1008 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 1008 24
-rect 130 80 159 88
-rect 418 80 447 88
-rect 130 88 447 102
-rect 130 102 159 109
-rect 418 102 447 109
-rect 274 121 303 150
-rect 898 40 927 69
-rect 706 175 735 204
-rect 905 69 919 215
-rect 713 204 727 223
-rect 898 215 927 223
-rect 713 223 927 237
-rect 898 237 927 244
-rect 0 309 1008 357
-<< ndiffusion >>
-rect 178 13 231 24
-rect 346 13 399 24
-rect 490 13 543 24
-rect 634 13 687 24
-rect 754 13 807 24
-rect 58 24 951 66
-rect 58 66 87 69
-rect 466 66 495 69
-rect 898 66 927 69
-<< pdiffusion >>
-rect 58 215 87 225
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-rect 466 215 519 225
-rect 634 215 687 225
-rect 898 215 927 225
-rect 58 225 951 309
-rect 178 309 231 312
-rect 754 309 807 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 424 86 441 103
-rect 568 86 585 103
-rect 712 86 729 103
-rect 856 86 873 103
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-rect 280 181 297 198
-rect 424 181 441 198
-rect 568 181 585 198
-rect 712 181 729 198
-rect 856 181 873 198
-<< pdiffc >>
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-rect 352 221 369 238
-rect 376 221 393 238
-rect 472 221 489 238
-rect 496 221 513 238
-rect 640 221 657 238
-rect 664 221 681 238
-rect 904 221 921 238
-rect 184 289 201 306
-rect 208 289 225 306
-rect 760 289 777 306
-rect 784 289 801 306
-<< ndiffc >>
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-rect 352 19 369 36
-rect 376 19 393 36
-rect 496 19 513 36
-rect 520 19 537 36
-rect 640 19 657 36
-rect 664 19 681 36
-rect 760 19 777 36
-rect 784 19 801 36
-rect 64 46 81 63
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-rect 904 46 921 63
-<< nplus >>
-<< pplus >>
-<< labels >>
-rlabel met1 0 309 1008 357 0 VDD
-port 1 se
-rlabel met1 0 -24 1008 24 0 GND
-port 2 se
-rlabel met1 898 40 927 69 0 Q
-port 3 se
-rlabel met1 706 175 735 204 0 Q
-port 4 se
-rlabel met1 905 69 919 215 0 Q
-port 5 se
-rlabel met1 713 204 727 223 0 Q
-port 6 se
-rlabel met1 898 215 927 223 0 Q
-port 7 se
-rlabel met1 713 223 927 237 0 Q
-port 8 se
-rlabel met1 898 237 927 244 0 Q
-port 9 se
-rlabel met1 274 121 303 150 0 D
-port 10 se
-rlabel met1 130 80 159 88 0 CLK
-port 11 se
-rlabel met1 418 80 447 88 0 CLK
-port 12 se
-rlabel met1 130 88 447 102 0 CLK
-port 13 se
-rlabel met1 130 102 159 109 0 CLK
-port 14 se
-rlabel met1 418 102 447 109 0 CLK
-port 15 se
-<< end >>
diff --git a/cells/mag/LOFTY.mag b/cells/mag/LOFTY.mag
deleted file mode 100644
index 39ac33f..0000000
--- a/cells/mag/LOFTY.mag
+++ /dev/null
@@ -1,670 +0,0 @@
-magic
-# Generated by librecell
-tech sky130A
-timestamp 1621192485
-<< nwell >>
-rect 0 179 2160 333
-rect 27 333 1990 340
-<< viali >>
-rect 1336 19 1353 36
-rect 1360 19 1377 36
-rect 1768 19 1785 36
-rect 1792 19 1809 36
-rect 88 46 105 63
-rect 208 46 225 63
-rect 352 46 369 63
-rect 472 46 489 63
-rect 520 46 537 63
-rect 712 46 729 63
-rect 760 46 777 63
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-rect 2056 46 2073 63
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-rect 2008 59 2025 76
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-rect 1432 140 1449 157
-rect 1624 140 1641 157
-rect 1864 140 1881 157
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-rect 568 181 585 198
-rect 664 181 681 198
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-rect 1192 181 1209 198
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-rect 1864 181 1881 198
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-rect 1600 221 1617 238
-rect 1912 221 1929 238
-rect 208 235 225 252
-rect 232 235 249 252
-rect 352 235 369 252
-rect 568 235 585 252
-rect 760 235 777 252
-rect 928 248 945 265
-rect 952 248 969 265
-rect 1480 248 1497 265
-rect 1504 248 1521 265
-rect 88 275 105 292
-rect 544 275 561 292
-<< poly >>
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-rect 128 78 161 111
-rect 281 11 296 78
-rect 272 78 305 111
-rect 569 11 584 78
-rect 560 78 593 111
-rect 713 11 728 78
-rect 704 78 737 111
-rect 857 11 872 78
-rect 848 78 881 111
-rect 1001 11 1016 78
-rect 992 78 1025 111
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-rect 1136 78 1169 111
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-rect 1712 78 1745 111
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-rect 1856 78 1889 111
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-rect 272 173 305 206
-rect 281 206 296 330
-rect 560 173 593 206
-rect 569 206 584 330
-rect 704 173 737 206
-rect 713 206 728 330
-rect 848 173 881 206
-rect 857 206 872 330
-rect 992 173 1025 206
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-rect 1568 173 1601 206
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-rect 1712 173 1745 206
-rect 1721 206 1736 330
-rect 1856 173 1889 206
-rect 1865 206 1880 330
-<< properties >>
-string FIXED_BBOX 0 0 2160 333
-<< li1 >>
-rect 1184 11 1241 44
-rect 1328 11 1385 44
-rect 1760 11 1817 44
-rect 1904 11 1961 44
-rect 472 5 657 11
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-rect 1040 19 1121 36
-rect 1040 36 1073 44
-rect 1088 36 1121 44
-rect 712 9 729 63
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-rect 200 11 257 44
-rect 200 44 233 71
-rect 344 38 377 71
-rect 512 38 545 71
-rect 752 38 785 71
-rect 800 38 833 71
-rect 920 24 977 57
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-rect 2048 38 2081 71
-rect 128 78 161 111
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-rect 560 78 593 111
-rect 704 78 737 111
-rect 2008 59 2025 78
-rect 2000 78 2033 111
-rect 328 127 681 144
-rect 1640 11 1697 38
-rect 1616 38 1697 44
-rect 1616 44 1649 71
-rect 1624 71 1641 157
-rect 1856 78 1889 111
-rect 1864 111 1881 157
-rect 560 173 593 181
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-rect 560 198 593 206
-rect 712 140 729 173
-rect 704 173 737 206
-rect 848 78 881 111
-rect 856 111 873 173
-rect 848 173 881 206
-rect 1000 167 1089 173
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-rect 1072 184 1089 198
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-rect 1000 111 1017 127
-rect 1000 127 1161 144
-rect 1144 144 1161 167
-rect 1144 167 1209 173
-rect 1136 173 1209 184
-rect 1192 184 1209 198
-rect 1136 184 1169 206
-rect 1280 78 1313 111
-rect 1288 111 1305 173
-rect 1280 173 1313 206
-rect 1424 78 1457 111
-rect 1432 111 1449 173
-rect 1424 173 1457 206
-rect 1576 59 1593 78
-rect 1568 78 1601 111
-rect 1576 111 1593 173
-rect 1568 173 1601 206
-rect 1712 78 1745 111
-rect 1720 111 1737 173
-rect 1712 173 1745 206
-rect 1856 173 1889 206
-rect 128 173 161 194
-rect 272 173 305 194
-rect 128 194 305 206
-rect 160 206 273 211
-rect 1136 78 1169 86
-rect 1136 86 1257 103
-rect 1136 103 1169 111
-rect 1168 208 1185 221
-rect 1240 103 1257 221
-rect 1168 221 1257 238
-rect 1456 208 1545 221
-rect 1456 221 1617 225
-rect 1528 225 1617 238
-rect 1384 208 1401 213
-rect 1352 213 1409 246
-rect 1640 213 1697 246
-rect 1784 213 1841 246
-rect 1904 213 1937 246
-rect 776 213 833 235
-rect 568 235 833 246
-rect 568 246 777 252
-rect 200 227 257 260
-rect 344 227 377 260
-rect 1048 208 1065 213
-rect 1040 213 1073 227
-rect 1040 227 1121 246
-rect 1064 246 1121 260
-rect 920 240 977 273
-rect 1472 240 1529 273
-rect 1184 254 1241 287
-rect 80 267 113 300
-rect 608 267 665 275
-rect 544 275 665 281
-rect 512 281 665 292
-rect 608 292 665 300
-rect 512 292 545 314
-rect 1616 281 1649 314
-rect 520 314 545 316
-rect 1616 314 1641 316
-rect 520 316 1641 333
-<< met1 >>
-rect 0 -24 2160 24
-rect 1330 24 1383 42
-rect 1762 24 1815 42
-rect 346 40 375 47
-rect 466 40 495 47
-rect 346 47 495 61
-rect 346 61 375 69
-rect 466 61 495 69
-rect 946 40 975 61
-rect 1474 40 1527 61
-rect 946 61 1527 69
-rect 953 69 1495 75
-rect 1570 53 1599 61
-rect 2002 53 2031 61
-rect 1570 61 2031 75
-rect 1570 75 1599 82
-rect 2002 75 2031 82
-rect 754 40 783 47
-rect 802 40 831 47
-rect 754 47 831 61
-rect 754 61 783 69
-rect 802 61 831 69
-rect 2050 40 2079 69
-rect 809 69 823 101
-rect 2057 69 2071 101
-rect 809 101 2071 115
-rect 706 40 735 47
-rect 665 47 735 61
-rect 706 61 735 69
-rect 665 61 679 121
-rect 658 121 687 150
-rect 706 80 735 109
-rect 713 109 727 134
-rect 706 134 735 163
-rect 1426 134 1455 163
-rect 562 80 591 109
-rect 569 109 583 175
-rect 562 175 591 204
-rect 1282 134 1311 142
-rect 809 142 1311 156
-rect 1282 156 1311 163
-rect 658 175 687 182
-rect 809 156 823 182
-rect 658 182 823 196
-rect 658 196 687 204
-rect 850 175 879 204
-rect 1714 175 1743 204
-rect 1858 134 1887 204
-rect 1378 202 1407 209
-rect 1450 202 1479 209
-rect 1378 209 1479 223
-rect 1378 223 1407 231
-rect 1450 223 1479 231
-rect 82 40 111 69
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 188
-rect 130 188 183 204
-rect 154 204 183 217
-rect 89 69 103 223
-rect 154 217 175 223
-rect 89 223 175 237
-rect 274 80 303 109
-rect 322 121 351 150
-rect 281 109 295 175
-rect 274 175 303 188
-rect 250 188 303 204
-rect 250 204 279 217
-rect 257 217 279 223
-rect 329 150 343 223
-rect 257 223 343 237
-rect 1594 215 1623 223
-rect 1906 215 1935 223
-rect 1594 223 1935 237
-rect 1594 237 1623 244
-rect 1906 237 1935 244
-rect 202 40 231 69
-rect 209 69 223 229
-rect 202 229 255 258
-rect 346 229 375 236
-rect 562 229 591 236
-rect 346 236 591 250
-rect 346 250 375 258
-rect 562 250 591 258
-rect 1066 175 1095 182
-rect 1066 182 1111 202
-rect 1186 175 1215 202
-rect 1162 202 1215 204
-rect 1042 202 1111 204
-rect 1042 204 1071 209
-rect 1097 204 1111 209
-rect 1162 204 1191 209
-rect 1097 209 1191 223
-rect 905 209 1071 223
-rect 1042 223 1071 231
-rect 1162 223 1191 231
-rect 754 229 783 236
-rect 905 223 919 236
-rect 754 236 919 250
-rect 754 250 783 258
-rect 922 242 975 250
-rect 1474 242 1527 250
-rect 922 250 1527 264
-rect 922 264 975 271
-rect 1474 264 1527 271
-rect 82 269 111 277
-rect 538 269 567 277
-rect 82 277 567 291
-rect 82 291 111 298
-rect 538 291 567 298
-rect 514 40 543 47
-rect 514 47 631 61
-rect 514 61 543 69
-rect 1618 134 1647 142
-rect 1553 142 1647 156
-rect 1618 156 1647 163
-rect 617 61 631 290
-rect 1553 156 1567 290
-rect 617 290 1567 304
-rect 0 309 2160 357
-<< li1 >>
-<< met1 >>
-<< li1 >>
-<< met1 >>
-rect 0 -24 2160 24
-rect 1570 53 1599 61
-rect 2002 53 2031 61
-rect 1570 61 2031 75
-rect 1570 75 1599 82
-rect 2002 75 2031 82
-rect 706 80 735 109
-rect 713 109 727 134
-rect 706 134 735 163
-rect 1426 134 1455 163
-rect 562 80 591 109
-rect 569 109 583 175
-rect 562 175 591 204
-rect 1714 175 1743 204
-rect 1858 134 1887 204
-rect 82 40 111 69
-rect 130 80 159 109
-rect 137 109 151 175
-rect 130 175 159 188
-rect 130 188 183 204
-rect 154 204 183 217
-rect 89 69 103 223
-rect 154 217 175 223
-rect 89 223 175 237
-rect 274 80 303 109
-rect 322 121 351 150
-rect 281 109 295 175
-rect 274 175 303 188
-rect 250 188 303 204
-rect 250 204 279 217
-rect 257 217 279 223
-rect 329 150 343 223
-rect 257 223 343 237
-rect 202 40 231 69
-rect 209 69 223 229
-rect 202 229 255 258
-rect 1066 175 1095 182
-rect 1066 182 1111 202
-rect 1186 175 1215 202
-rect 1162 202 1215 204
-rect 1042 202 1111 204
-rect 1042 204 1071 209
-rect 1097 204 1111 209
-rect 1162 204 1191 209
-rect 1097 209 1191 223
-rect 905 209 1071 223
-rect 1042 223 1071 231
-rect 1162 223 1191 231
-rect 754 229 783 236
-rect 905 223 919 236
-rect 754 236 919 250
-rect 754 250 783 258
-rect 0 309 2160 357
-<< ndiffusion >>
-rect 202 13 255 24
-rect 58 24 375 66
-rect 82 66 111 69
-rect 202 66 231 69
-rect 346 66 375 69
-rect 634 13 687 24
-rect 1042 13 1071 24
-rect 1090 13 1119 24
-rect 1186 13 1239 24
-rect 1330 13 1383 24
-rect 1642 13 1695 24
-rect 1762 13 1815 24
-rect 1906 13 1959 24
-rect 490 24 2103 66
-rect 514 66 543 69
-rect 754 66 783 69
-rect 802 66 831 69
-rect 946 66 975 69
-rect 1474 66 1527 69
-rect 1618 66 1647 69
-rect 2050 66 2079 69
-<< pdiffusion >>
-rect 58 225 375 309
-rect 778 215 831 225
-rect 1042 215 1071 225
-rect 1354 215 1407 225
-rect 1642 215 1695 225
-rect 1786 215 1839 225
-rect 1906 215 1935 225
-rect 490 225 1959 309
-rect 514 309 543 312
-rect 1618 309 1647 312
-<< polycont >>
-rect 136 86 153 103
-rect 280 86 297 103
-rect 568 86 585 103
-rect 712 86 729 103
-rect 856 86 873 103
-rect 1000 86 1017 103
-rect 1144 86 1161 103
-rect 1288 86 1305 103
-rect 1432 86 1449 103
-rect 1576 86 1593 103
-rect 1720 86 1737 103
-rect 1864 86 1881 103
-rect 2008 86 2025 103
-rect 136 181 153 198
-rect 280 181 297 198
-rect 568 181 585 198
-rect 712 181 729 198
-rect 856 181 873 198
-rect 1000 181 1017 198
-rect 1144 181 1161 198
-rect 1288 181 1305 198
-rect 1432 181 1449 198
-rect 1576 181 1593 198
-rect 1720 181 1737 198
-rect 1864 181 1881 198
-<< pdiffc >>
-rect 784 221 801 238
-rect 808 221 825 238
-rect 1048 221 1065 238
-rect 1360 221 1377 238
-rect 1384 221 1401 238
-rect 1648 221 1665 238
-rect 1672 221 1689 238
-rect 1792 221 1809 238
-rect 1816 221 1833 238
-rect 1912 221 1929 238
-rect 208 235 225 252
-rect 232 235 249 252
-rect 352 235 369 252
-rect 1072 235 1089 252
-rect 1096 235 1113 252
-rect 928 248 945 265
-rect 952 248 969 265
-rect 1480 248 1497 265
-rect 1504 248 1521 265
-rect 1192 262 1209 279
-rect 1216 262 1233 279
-rect 88 275 105 292
-rect 616 275 633 292
-rect 640 275 657 292
-rect 520 289 537 306
-rect 1624 289 1641 306
-<< ndiffc >>
-rect 208 19 225 36
-rect 232 19 249 36
-rect 640 19 657 36
-rect 664 19 681 36
-rect 1048 19 1065 36
-rect 1096 19 1113 36
-rect 1192 19 1209 36
-rect 1216 19 1233 36
-rect 1336 19 1353 36
-rect 1360 19 1377 36
-rect 1648 19 1665 36
-rect 1672 19 1689 36
-rect 1768 19 1785 36
-rect 1792 19 1809 36
-rect 1912 19 1929 36
-rect 1936 19 1953 36
-rect 928 32 945 49
-rect 88 46 105 63
-rect 208 46 225 63
-rect 352 46 369 63
-rect 520 46 537 63
-rect 760 46 777 63
-rect 808 46 825 63
-rect 952 32 969 63
-rect 1480 46 1497 63
-rect 1504 46 1521 63
-rect 1624 46 1641 63
-rect 2056 46 2073 63
-<< nplus >>
-<< pplus >>
-<< labels >>
-rlabel met1 0 309 2160 357 0 VDD
-port 1 se
-rlabel met1 0 -24 2160 24 0 GND
-port 2 se
-rlabel met1 202 40 231 69 0 Q
-port 3 se
-rlabel met1 209 69 223 229 0 Q
-port 4 se
-rlabel met1 202 229 255 258 0 Q
-port 5 se
-rlabel met1 562 80 591 109 0 ASEL_P
-port 6 se
-rlabel met1 569 109 583 175 0 ASEL_P
-port 7 se
-rlabel met1 562 175 591 204 0 ASEL_P
-port 8 se
-rlabel met1 1570 53 1599 61 0 USEXOR_N
-port 9 se
-rlabel met1 2002 53 2031 61 0 USEXOR_N
-port 10 se
-rlabel met1 1570 61 2031 75 0 USEXOR_N
-port 11 se
-rlabel met1 1570 75 1599 82 0 USEXOR_N
-port 12 se
-rlabel met1 2002 75 2031 82 0 USEXOR_N
-port 13 se
-rlabel met1 82 40 111 69 0 USEMUX_N
-port 14 se
-rlabel met1 130 80 159 109 0 USEMUX_N
-port 15 se
-rlabel met1 137 109 151 175 0 USEMUX_N
-port 16 se
-rlabel met1 130 175 159 188 0 USEMUX_N
-port 17 se
-rlabel met1 130 188 183 204 0 USEMUX_N
-port 18 se
-rlabel met1 154 204 183 217 0 USEMUX_N
-port 19 se
-rlabel met1 89 69 103 223 0 USEMUX_N
-port 20 se
-rlabel met1 154 217 175 223 0 USEMUX_N
-port 21 se
-rlabel met1 89 223 175 237 0 USEMUX_N
-port 22 se
-rlabel met1 850 175 879 204 0 USEXOR_P
-port 23 se
-rlabel met1 1714 175 1743 204 0 USEXOR_P
-port 24 se
-rlabel met1 706 80 735 109 0 ASEL_N
-port 25 se
-rlabel met1 713 109 727 134 0 ASEL_N
-port 26 se
-rlabel met1 706 134 735 163 0 ASEL_N
-port 27 se
-rlabel met1 1858 134 1887 204 0 BSEL_N
-port 28 se
-rlabel met1 1426 134 1455 163 0 BSEL_P
-port 29 se
-rlabel met1 1066 175 1095 182 0 MUXSEL_P
-port 30 se
-rlabel met1 1066 182 1111 202 0 MUXSEL_P
-port 31 se
-rlabel met1 1186 175 1215 202 0 MUXSEL_P
-port 32 se
-rlabel met1 1162 202 1215 204 0 MUXSEL_P
-port 33 se
-rlabel met1 1042 202 1111 204 0 MUXSEL_P
-port 34 se
-rlabel met1 1042 204 1071 209 0 MUXSEL_P
-port 35 se
-rlabel met1 1097 204 1111 209 0 MUXSEL_P
-port 36 se
-rlabel met1 1162 204 1191 209 0 MUXSEL_P
-port 37 se
-rlabel met1 1097 209 1191 223 0 MUXSEL_P
-port 38 se
-rlabel met1 905 209 1071 223 0 MUXSEL_P
-port 39 se
-rlabel met1 1042 223 1071 231 0 MUXSEL_P
-port 40 se
-rlabel met1 1162 223 1191 231 0 MUXSEL_P
-port 41 se
-rlabel met1 754 229 783 236 0 MUXSEL_P
-port 42 se
-rlabel met1 905 223 919 236 0 MUXSEL_P
-port 43 se
-rlabel met1 754 236 919 250 0 MUXSEL_P
-port 44 se
-rlabel met1 754 250 783 258 0 MUXSEL_P
-port 45 se
-rlabel met1 274 80 303 109 0 USEMUX_P
-port 46 se
-rlabel met1 322 121 351 150 0 USEMUX_P
-port 47 se
-rlabel met1 281 109 295 175 0 USEMUX_P
-port 48 se
-rlabel met1 274 175 303 188 0 USEMUX_P
-port 49 se
-rlabel met1 250 188 303 204 0 USEMUX_P
-port 50 se
-rlabel met1 250 204 279 217 0 USEMUX_P
-port 51 se
-rlabel met1 257 217 279 223 0 USEMUX_P
-port 52 se
-rlabel met1 329 150 343 223 0 USEMUX_P
-port 53 se
-rlabel met1 257 223 343 237 0 USEMUX_P
-port 54 se
-rlabel met1 1066 175 1095 182 0 MUXSEL_N
-port 55 se
-rlabel met1 1066 182 1111 202 0 MUXSEL_N
-port 56 se
-rlabel met1 1186 175 1215 202 0 MUXSEL_N
-port 57 se
-rlabel met1 1162 202 1215 204 0 MUXSEL_N
-port 58 se
-rlabel met1 1042 202 1111 204 0 MUXSEL_N
-port 59 se
-rlabel met1 1042 204 1071 209 0 MUXSEL_N
-port 60 se
-rlabel met1 1097 204 1111 209 0 MUXSEL_N
-port 61 se
-rlabel met1 1162 204 1191 209 0 MUXSEL_N
-port 62 se
-rlabel met1 1097 209 1191 223 0 MUXSEL_N
-port 63 se
-rlabel met1 905 209 1071 223 0 MUXSEL_N
-port 64 se
-rlabel met1 1042 223 1071 231 0 MUXSEL_N
-port 65 se
-rlabel met1 1162 223 1191 231 0 MUXSEL_N
-port 66 se
-rlabel met1 754 229 783 236 0 MUXSEL_N
-port 67 se
-rlabel met1 905 223 919 236 0 MUXSEL_N
-port 68 se
-rlabel met1 754 236 919 250 0 MUXSEL_N
-port 69 se
-rlabel met1 754 250 783 258 0 MUXSEL_N
-port 70 se
-<< end >>
diff --git a/cells/mag/LOFTY2.mag b/cells/mag/LOFTY2.mag
deleted file mode 100644
index 77b8b65..0000000
--- a/cells/mag/LOFTY2.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 1621276817
-<< end >>
diff --git a/cells/mag/MUX2X1.mag b/cells/mag/MUX2X1.mag
index 4a9106a..4518a35 100644
--- a/cells/mag/MUX2X1.mag
+++ b/cells/mag/MUX2X1.mag
@@ -1,4 +1,375 @@
magic
tech sky130A
-timestamp 1621276911
+timestamp 1623602976
+<< nwell >>
+rect 0 179 864 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+rect 569 24 584 66
+rect 713 24 728 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+rect 569 225 584 309
+rect 713 225 728 309
+<< ndiff >>
+rect 58 66 87 69
+rect 514 66 543 69
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
+rect 178 19 184 24
+rect 201 24 281 36
+rect 296 24 425 66
+rect 440 63 569 66
+rect 440 46 520 63
+rect 537 46 569 63
+rect 440 24 569 46
+rect 584 24 713 66
+rect 728 36 807 66
+rect 728 24 760 36
+rect 201 19 207 24
+rect 178 13 207 19
+rect 754 19 760 24
+rect 777 24 807 36
+rect 777 19 783 24
+rect 754 13 783 19
+<< pdiff >>
+rect 178 309 207 312
+rect 754 309 783 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 225 425 309
+rect 440 238 569 309
+rect 440 225 520 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 514 221 520 225
+rect 537 225 569 238
+rect 584 225 713 309
+rect 728 306 807 309
+rect 728 289 760 306
+rect 777 289 807 306
+rect 728 225 807 289
+rect 537 221 543 225
+rect 514 215 543 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 184 19 201 36
+rect 520 46 537 63
+rect 760 19 777 36
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 520 221 537 238
+rect 760 289 777 306
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 569 309 584 330
+rect 713 309 728 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 425 206 440 225
+rect 569 206 584 225
+rect 713 206 728 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 416 173 449 181
+rect 560 198 593 206
+rect 560 181 568 198
+rect 585 181 593 198
+rect 560 173 593 181
+rect 704 198 737 206
+rect 704 181 712 198
+rect 729 181 737 198
+rect 704 173 737 181
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 560 103 593 111
+rect 560 86 568 103
+rect 585 86 593 103
+rect 560 78 593 86
+rect 704 103 737 111
+rect 704 86 712 103
+rect 729 86 737 103
+rect 704 78 737 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 425 66 440 78
+rect 569 66 584 78
+rect 713 66 728 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
+rect 569 11 584 24
+rect 713 11 728 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 568 181 585 198
+rect 712 181 729 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 568 86 585 103
+rect 712 86 729 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
+rect 752 306 785 314
+rect 752 289 760 306
+rect 777 289 785 306
+rect 752 281 785 289
+rect 56 238 89 246
+rect 56 221 64 238
+rect 81 221 89 238
+rect 56 213 89 221
+rect 512 238 545 246
+rect 512 221 520 238
+rect 537 221 545 238
+rect 512 213 545 221
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
+rect 272 198 305 206
+rect 272 181 280 198
+rect 297 181 305 198
+rect 272 173 305 181
+rect 416 198 449 206
+rect 416 181 424 198
+rect 441 181 449 198
+rect 562 198 593 206
+rect 562 196 568 198
+rect 416 173 449 181
+rect 560 181 568 196
+rect 585 181 593 198
+rect 560 173 593 181
+rect 704 198 737 206
+rect 704 181 712 198
+rect 729 181 737 198
+rect 704 173 737 181
+rect 136 111 153 173
+rect 280 144 297 173
+rect 280 111 297 127
+rect 128 103 161 111
+rect 128 86 136 103
+rect 153 86 161 103
+rect 128 78 161 86
+rect 272 103 305 111
+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 416 103 449 111
+rect 416 86 424 103
+rect 441 86 449 103
+rect 416 78 449 86
+rect 520 71 537 127
+rect 560 103 593 111
+rect 560 88 568 103
+rect 562 86 568 88
+rect 585 86 593 103
+rect 562 78 593 86
+rect 704 103 737 111
+rect 704 86 712 103
+rect 729 86 737 103
+rect 704 78 737 86
+rect 56 63 89 71
+rect 56 46 64 63
+rect 81 46 89 63
+rect 56 38 89 46
+rect 512 63 545 71
+rect 512 46 520 63
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+rect 176 36 209 44
+rect 512 38 545 46
+rect 176 19 184 36
+rect 201 19 209 36
+rect 176 11 209 19
+rect 752 36 785 44
+rect 752 19 760 36
+rect 777 19 785 36
+rect 752 11 785 19
+<< viali >>
+rect 184 289 201 306
+rect 760 289 777 306
+rect 64 221 81 238
+rect 520 221 537 238
+rect 424 181 441 198
+rect 568 181 585 198
+rect 712 181 729 198
+rect 280 127 297 144
+rect 520 127 537 144
+rect 136 86 153 103
+rect 424 86 441 103
+rect 568 86 585 103
+rect 712 86 729 103
+rect 64 46 81 63
+rect 184 19 201 36
+rect 760 19 777 36
+<< metal1 >>
+rect 0 309 864 357
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 754 306 783 309
+rect 754 289 760 306
+rect 777 289 783 306
+rect 754 283 783 289
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 221 87 238
+rect 58 215 87 221
+rect 514 238 543 244
+rect 514 221 520 238
+rect 537 221 543 238
+rect 514 215 543 221
+rect 65 196 79 215
+rect 418 198 447 204
+rect 418 196 424 198
+rect 65 182 424 196
+rect 65 69 79 182
+rect 418 181 424 182
+rect 441 196 447 198
+rect 441 182 487 196
+rect 441 181 447 182
+rect 418 175 447 181
+rect 274 144 303 150
+rect 274 127 280 144
+rect 297 127 303 144
+rect 274 121 303 127
+rect 130 103 159 109
+rect 130 86 136 103
+rect 153 102 159 103
+rect 418 103 447 109
+rect 418 102 424 103
+rect 153 88 424 102
+rect 153 86 159 88
+rect 130 80 159 86
+rect 418 86 424 88
+rect 441 86 447 103
+rect 473 102 487 182
+rect 521 150 535 215
+rect 562 198 591 204
+rect 562 181 568 198
+rect 585 196 591 198
+rect 706 198 735 204
+rect 585 182 631 196
+rect 585 181 591 182
+rect 562 175 591 181
+rect 514 144 543 150
+rect 514 127 520 144
+rect 537 127 543 144
+rect 514 121 543 127
+rect 562 103 591 109
+rect 562 102 568 103
+rect 473 88 568 102
+rect 418 80 447 86
+rect 562 86 568 88
+rect 585 86 591 103
+rect 562 80 591 86
+rect 58 63 87 69
+rect 58 46 64 63
+rect 81 46 87 63
+rect 425 61 439 80
+rect 617 61 631 182
+rect 706 181 712 198
+rect 729 181 735 198
+rect 706 175 735 181
+rect 713 109 727 175
+rect 706 103 735 109
+rect 706 86 712 103
+rect 729 86 735 103
+rect 706 80 735 86
+rect 425 47 631 61
+rect 58 40 87 46
+rect 178 36 207 42
+rect 178 24 184 36
+rect 0 19 184 24
+rect 201 24 207 36
+rect 754 36 783 42
+rect 754 24 760 36
+rect 201 19 760 24
+rect 777 24 783 36
+rect 777 19 864 24
+rect 0 -24 864 19
+<< labels >>
+rlabel metal1 0 309 864 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 864 24 0 GND
+port 2 se
+rlabel metal1 514 121 543 150 0 Y
+port 3 se
+rlabel metal1 521 150 535 215 0 Y
+port 4 se
+rlabel metal1 514 215 543 244 0 Y
+port 5 se
+rlabel metal1 425 47 631 61 0 S
+port 6 se
+rlabel metal1 425 61 439 80 0 S
+port 7 se
+rlabel metal1 130 80 159 88 0 S
+port 8 se
+rlabel metal1 418 80 447 88 0 S
+port 9 se
+rlabel metal1 130 88 447 102 0 S
+port 10 se
+rlabel metal1 130 102 159 109 0 S
+port 11 se
+rlabel metal1 418 102 447 109 0 S
+port 12 se
+rlabel metal1 562 175 591 182 0 S
+port 13 se
+rlabel metal1 617 61 631 182 0 S
+port 14 se
+rlabel metal1 562 182 631 196 0 S
+port 15 se
+rlabel metal1 562 196 591 204 0 S
+port 16 se
+rlabel metal1 706 80 735 109 0 B
+port 17 se
+rlabel metal1 713 109 727 175 0 B
+port 18 se
+rlabel metal1 706 175 735 204 0 B
+port 19 se
+rlabel metal1 274 121 303 150 0 A
+port 20 se
+<< properties >>
+string FIXED_BBOX 0 0 864 333
<< end >>
diff --git a/cells/mag/NAND2X1.mag b/cells/mag/NAND2X1.mag
index 77a1451..d8b5538 100644
--- a/cells/mag/NAND2X1.mag
+++ b/cells/mag/NAND2X1.mag
@@ -1,4 +1,206 @@
magic
tech sky130A
-timestamp 1621277091
+timestamp 1623602980
+<< nwell >>
+rect 0 179 432 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+<< ndiff >>
+rect 58 66 87 69
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 24 281 66
+rect 296 36 375 66
+rect 296 24 328 36
+rect 322 19 328 24
+rect 345 24 375 36
+rect 345 19 351 24
+rect 322 13 351 19
+<< pdiff >>
+rect 178 309 207 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
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+rect 296 225 328 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 322 221 328 225
+rect 345 225 375 238
+rect 345 221 351 225
+rect 322 215 351 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 328 19 345 36
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 328 221 345 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
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+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 137 11 152 24
+rect 281 11 296 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+<< locali >>
+rect 176 306 209 314
+rect 176 289 184 306
+rect 201 289 209 306
+rect 176 281 209 289
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+rect 81 221 89 238
+rect 56 213 89 221
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+rect 56 46 64 63
+rect 81 46 89 63
+rect 56 38 89 46
+rect 320 36 353 44
+rect 320 19 328 36
+rect 345 19 353 36
+rect 320 11 353 19
+<< viali >>
+rect 184 289 201 306
+rect 64 221 81 238
+rect 328 221 345 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 64 46 81 63
+rect 328 19 345 36
+<< metal1 >>
+rect 0 309 432 357
+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 237 87 238
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+rect 322 237 328 238
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+rect 345 221 351 238
+rect 322 215 351 221
+rect 65 69 79 215
+rect 130 198 159 204
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+rect 274 198 303 204
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+rect 130 86 136 103
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+rect 130 80 159 86
+rect 274 103 303 109
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+rect 58 63 87 69
+rect 58 46 64 63
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+rect 58 40 87 46
+rect 322 36 351 42
+rect 322 24 328 36
+rect 0 19 328 24
+rect 345 24 351 36
+rect 345 19 432 24
+rect 0 -24 432 19
+<< labels >>
+rlabel metal1 0 309 432 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 432 24 0 GND
+port 2 se
+rlabel metal1 58 40 87 69 0 Y
+port 3 se
+rlabel metal1 65 69 79 215 0 Y
+port 4 se
+rlabel metal1 58 215 87 223 0 Y
+port 5 se
+rlabel metal1 322 215 351 223 0 Y
+port 6 se
+rlabel metal1 58 223 351 237 0 Y
+port 7 se
+rlabel metal1 58 237 87 244 0 Y
+port 8 se
+rlabel metal1 322 237 351 244 0 Y
+port 9 se
+rlabel metal1 130 80 159 109 0 B
+port 10 se
+rlabel metal1 137 109 151 175 0 B
+port 11 se
+rlabel metal1 130 175 159 204 0 B
+port 12 se
+rlabel metal1 274 80 303 109 0 A
+port 13 se
+rlabel metal1 281 109 295 175 0 A
+port 14 se
+rlabel metal1 274 175 303 204 0 A
+port 15 se
+<< properties >>
+string FIXED_BBOX 0 0 432 333
<< end >>
diff --git a/cells/mag/NAND3X1.mag b/cells/mag/NAND3X1.mag
index 2ec7a05..7e1bf03 100644
--- a/cells/mag/NAND3X1.mag
+++ b/cells/mag/NAND3X1.mag
@@ -1,4 +1,263 @@
magic
tech sky130A
-timestamp 1621277170
+timestamp 1623602984
+<< nwell >>
+rect 0 179 576 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+<< ndiff >>
+rect 58 66 87 69
+rect 58 63 137 66
+rect 58 46 64 63
+rect 81 46 137 63
+rect 58 24 137 46
+rect 152 24 281 66
+rect 296 24 425 66
+rect 440 36 519 66
+rect 440 24 472 36
+rect 466 19 472 24
+rect 489 24 519 36
+rect 489 19 495 24
+rect 466 13 495 19
+<< pdiff >>
+rect 178 309 207 312
+rect 466 309 495 312
+rect 58 238 137 309
+rect 58 221 64 238
+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 238 425 309
+rect 296 225 328 238
+rect 81 221 87 225
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+rect 322 221 328 225
+rect 345 225 425 238
+rect 440 306 519 309
+rect 440 289 472 306
+rect 489 289 519 306
+rect 440 225 519 289
+rect 345 221 351 225
+rect 322 215 351 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 472 19 489 36
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 328 221 345 238
+rect 472 289 489 306
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 137 206 152 225
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+rect 425 206 440 225
+rect 128 198 161 206
+rect 128 181 136 198
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+rect 137 66 152 78
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+rect 425 66 440 78
+rect 137 11 152 24
+rect 281 11 296 24
+rect 425 11 440 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+<< locali >>
+rect 176 306 209 314
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+rect 176 281 209 289
+rect 464 306 497 314
+rect 464 289 472 306
+rect 489 289 497 306
+rect 464 281 497 289
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+rect 464 36 497 44
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+rect 464 11 497 19
+<< viali >>
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+rect 64 221 81 238
+rect 328 221 345 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
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+rect 424 86 441 103
+rect 64 46 81 63
+rect 472 19 489 36
+<< metal1 >>
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+rect 178 283 207 289
+rect 466 306 495 309
+rect 466 289 472 306
+rect 489 289 495 306
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+rect 466 36 495 42
+rect 466 24 472 36
+rect 0 19 472 24
+rect 489 24 495 36
+rect 489 19 576 24
+rect 0 -24 576 19
+<< labels >>
+rlabel metal1 0 309 576 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 576 24 0 GND
+port 2 se
+rlabel metal1 58 40 87 69 0 Y
+port 3 se
+rlabel metal1 65 69 79 215 0 Y
+port 4 se
+rlabel metal1 58 215 87 223 0 Y
+port 5 se
+rlabel metal1 322 215 351 223 0 Y
+port 6 se
+rlabel metal1 58 223 351 237 0 Y
+port 7 se
+rlabel metal1 58 237 87 244 0 Y
+port 8 se
+rlabel metal1 322 237 351 244 0 Y
+port 9 se
+rlabel metal1 418 80 447 109 0 A
+port 10 se
+rlabel metal1 425 109 439 175 0 A
+port 11 se
+rlabel metal1 418 175 447 204 0 A
+port 12 se
+rlabel metal1 130 80 159 109 0 C
+port 13 se
+rlabel metal1 137 109 151 175 0 C
+port 14 se
+rlabel metal1 130 175 159 204 0 C
+port 15 se
+rlabel metal1 274 80 303 109 0 B
+port 16 se
+rlabel metal1 281 109 295 175 0 B
+port 17 se
+rlabel metal1 274 175 303 204 0 B
+port 18 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/NOR2.mag b/cells/mag/NOR2.mag
deleted file mode 100644
index c4ccf29..0000000
--- a/cells/mag/NOR2.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 1621277262
-<< end >>
diff --git a/cells/mag/NOR2X1.mag b/cells/mag/NOR2X1.mag
index a621033..9b9e078 100644
--- a/cells/mag/NOR2X1.mag
+++ b/cells/mag/NOR2X1.mag
@@ -1,4 +1,207 @@
magic
tech sky130A
-timestamp 1621277284
+timestamp 1623602988
+<< nwell >>
+rect 0 179 432 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+<< ndiff >>
+rect 82 66 111 69
+rect 322 66 351 69
+rect 58 63 137 66
+rect 58 46 88 63
+rect 105 46 137 63
+rect 58 24 137 46
+rect 152 36 281 66
+rect 152 24 184 36
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+rect 201 24 281 36
+rect 296 63 375 66
+rect 296 46 328 63
+rect 345 46 375 63
+rect 296 24 375 46
+rect 201 19 207 24
+rect 178 13 207 19
+<< pdiff >>
+rect 58 309 87 312
+rect 58 306 137 309
+rect 58 289 64 306
+rect 81 289 137 306
+rect 58 225 137 289
+rect 152 225 281 309
+rect 296 238 375 309
+rect 296 225 328 238
+rect 322 221 328 225
+rect 345 225 375 238
+rect 345 221 351 225
+rect 322 215 351 221
+<< ndiffc >>
+rect 88 46 105 63
+rect 184 19 201 36
+rect 328 46 345 63
+<< pdiffc >>
+rect 64 289 81 306
+rect 328 221 345 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 137 206 152 225
+rect 281 206 296 225
+rect 128 198 161 206
+rect 128 181 136 198
+rect 153 181 161 198
+rect 128 173 161 181
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+rect 272 86 280 103
+rect 297 86 305 103
+rect 272 78 305 86
+rect 137 66 152 78
+rect 281 66 296 78
+rect 137 11 152 24
+rect 281 11 296 24
+<< polycont >>
+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+<< locali >>
+rect 56 306 89 314
+rect 56 289 64 306
+rect 81 289 89 306
+rect 56 281 89 289
+rect 320 238 353 246
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+rect 345 221 353 238
+rect 320 213 353 221
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+rect 176 11 184 36
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+<< viali >>
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+rect 136 181 153 198
+rect 280 181 297 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 88 46 105 63
+rect 328 46 345 63
+rect 184 19 201 22
+rect 184 5 201 19
+<< metal1 >>
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+rect 58 306 87 309
+rect 58 289 64 306
+rect 81 289 87 306
+rect 58 283 87 289
+rect 322 238 351 244
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+rect 345 221 351 238
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+rect 345 46 351 63
+rect 322 40 351 46
+rect 178 24 207 28
+rect 0 22 432 24
+rect 0 5 184 22
+rect 201 5 432 22
+rect 0 -24 432 5
+<< labels >>
+rlabel metal1 0 309 432 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 432 24 0 GND
+port 2 se
+rlabel metal1 82 40 111 47 0 Y
+port 3 se
+rlabel metal1 322 40 351 47 0 Y
+port 4 se
+rlabel metal1 82 47 351 61 0 Y
+port 5 se
+rlabel metal1 82 61 111 69 0 Y
+port 6 se
+rlabel metal1 322 61 351 69 0 Y
+port 7 se
+rlabel metal1 329 69 343 215 0 Y
+port 8 se
+rlabel metal1 322 215 351 244 0 Y
+port 9 se
+rlabel metal1 130 80 159 109 0 A
+port 10 se
+rlabel metal1 137 109 151 175 0 A
+port 11 se
+rlabel metal1 130 175 159 204 0 A
+port 12 se
+rlabel metal1 274 80 303 109 0 B
+port 13 se
+rlabel metal1 281 109 295 175 0 B
+port 14 se
+rlabel metal1 274 175 303 204 0 B
+port 15 se
+<< properties >>
+string FIXED_BBOX 0 0 432 333
<< end >>
diff --git a/cells/mag/NOR3X1.mag b/cells/mag/NOR3X1.mag
deleted file mode 100644
index b8cf1f1..0000000
--- a/cells/mag/NOR3X1.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 1621277354
-<< end >>
diff --git a/cells/mag/OAI21X1.mag b/cells/mag/OAI21X1.mag
index 713ad5a..2fb5398 100644
--- a/cells/mag/OAI21X1.mag
+++ b/cells/mag/OAI21X1.mag
@@ -1,4 +1,281 @@
magic
tech sky130A
-timestamp 1621277438
+timestamp 1623602995
+<< nwell >>
+rect 0 179 576 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+<< ndiff >>
+rect 58 66 87 69
+rect 226 66 255 69
+rect 466 66 495 69
+rect 58 63 137 66
+rect 58 46 64 63
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+rect 58 24 137 46
+rect 152 63 281 66
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+rect 345 24 425 36
+rect 440 63 519 66
+rect 440 46 472 63
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+rect 440 24 519 46
+rect 345 19 351 24
+rect 322 13 351 19
+<< pdiff >>
+rect 178 309 207 312
+rect 58 238 137 309
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+rect 81 225 137 238
+rect 152 306 281 309
+rect 152 289 184 306
+rect 201 289 281 306
+rect 152 225 281 289
+rect 296 225 425 309
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+rect 440 225 472 238
+rect 81 221 87 225
+rect 58 215 87 221
+rect 466 221 472 225
+rect 489 225 519 238
+rect 489 221 495 225
+rect 466 215 495 221
+<< ndiffc >>
+rect 64 46 81 63
+rect 232 46 249 63
+rect 328 19 345 36
+rect 472 46 489 63
+<< pdiffc >>
+rect 64 221 81 238
+rect 184 289 201 306
+rect 472 221 489 238
+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
+rect 137 206 152 225
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+rect 425 206 440 225
+rect 128 198 161 206
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+rect 416 78 449 86
+rect 137 66 152 78
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+rect 137 11 152 24
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+rect 425 11 440 24
+<< polycont >>
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+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+<< locali >>
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+rect 176 281 209 289
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+rect 56 213 89 221
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+rect 320 11 328 36
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+<< viali >>
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+rect 64 221 81 238
+rect 472 221 489 238
+rect 136 181 153 198
+rect 280 181 297 198
+rect 424 181 441 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 64 46 81 63
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+rect 328 19 345 22
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+<< metal1 >>
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+rect 178 306 207 309
+rect 178 289 184 306
+rect 201 289 207 306
+rect 178 283 207 289
+rect 58 238 87 244
+rect 58 221 64 238
+rect 81 237 87 238
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+rect 489 46 495 63
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+rect 322 24 351 28
+rect 0 22 576 24
+rect 0 5 328 22
+rect 345 5 576 22
+rect 0 -24 576 5
+<< labels >>
+rlabel metal1 0 309 576 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 576 24 0 GND
+port 2 se
+rlabel metal1 58 40 87 69 0 Y
+port 3 se
+rlabel metal1 65 69 79 215 0 Y
+port 4 se
+rlabel metal1 58 215 87 223 0 Y
+port 5 se
+rlabel metal1 466 215 495 223 0 Y
+port 6 se
+rlabel metal1 58 223 495 237 0 Y
+port 7 se
+rlabel metal1 58 237 87 244 0 Y
+port 8 se
+rlabel metal1 466 237 495 244 0 Y
+port 9 se
+rlabel metal1 274 80 303 109 0 A
+port 10 se
+rlabel metal1 281 109 295 175 0 A
+port 11 se
+rlabel metal1 274 175 303 204 0 A
+port 12 se
+rlabel metal1 130 80 159 109 0 C
+port 13 se
+rlabel metal1 137 109 151 175 0 C
+port 14 se
+rlabel metal1 130 175 159 204 0 C
+port 15 se
+rlabel metal1 418 80 447 109 0 B
+port 16 se
+rlabel metal1 425 109 439 175 0 B
+port 17 se
+rlabel metal1 418 175 447 204 0 B
+port 18 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/OAI22X1.mag b/cells/mag/OAI22X1.mag
index 56ac095..2a3d094 100644
--- a/cells/mag/OAI22X1.mag
+++ b/cells/mag/OAI22X1.mag
@@ -1,4 +1,346 @@
magic
tech sky130A
-timestamp 1621277560
+timestamp 1623602999
+<< nwell >>
+rect 0 179 720 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+rect 569 24 584 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+rect 569 225 584 309
+<< ndiff >>
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+rect 584 63 663 66
+rect 584 46 616 63
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+rect 201 19 207 24
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+<< pdiff >>
+rect 322 309 351 312
+rect 58 238 137 309
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+rect 105 225 137 238
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+rect 296 306 425 309
+rect 296 289 328 306
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+rect 105 221 111 225
+rect 82 215 111 221
+rect 610 221 616 225
+rect 633 225 663 238
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+rect 610 215 639 221
+<< ndiffc >>
+rect 88 46 105 63
+rect 184 19 201 36
+rect 376 46 393 63
+rect 520 46 537 63
+rect 616 46 633 63
+<< pdiffc >>
+rect 88 221 105 238
+rect 328 289 345 306
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+<< poly >>
+rect 137 309 152 330
+rect 281 309 296 330
+rect 425 309 440 330
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+<< polycont >>
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+rect 280 181 297 198
+rect 424 181 441 198
+rect 568 181 585 198
+rect 136 86 153 103
+rect 280 86 297 103
+rect 424 86 441 103
+rect 568 86 585 103
+<< locali >>
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+rect 320 281 353 289
+rect 80 238 113 246
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+rect 608 238 641 246
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+rect 176 11 184 36
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+<< viali >>
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+rect 616 221 633 238
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+<< metal1 >>
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+rect 633 46 639 63
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+rect 178 24 207 28
+rect 0 22 720 24
+rect 0 5 184 22
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+rect 0 -24 720 5
+<< labels >>
+rlabel metal1 0 309 720 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 720 24 0 GND
+port 2 se
+rlabel metal1 514 80 543 109 0 Y
+port 3 se
+rlabel metal1 82 215 111 223 0 Y
+port 4 se
+rlabel metal1 521 109 535 223 0 Y
+port 5 se
+rlabel metal1 610 215 639 223 0 Y
+port 6 se
+rlabel metal1 82 223 639 237 0 Y
+port 7 se
+rlabel metal1 82 237 111 244 0 Y
+port 8 se
+rlabel metal1 610 237 639 244 0 Y
+port 9 se
+rlabel metal1 130 80 159 109 0 B
+port 10 se
+rlabel metal1 137 109 151 175 0 B
+port 11 se
+rlabel metal1 130 175 159 204 0 B
+port 12 se
+rlabel metal1 562 80 591 109 0 D
+port 13 se
+rlabel metal1 569 109 583 175 0 D
+port 14 se
+rlabel metal1 562 175 591 204 0 D
+port 15 se
+rlabel metal1 418 80 447 109 0 C
+port 16 se
+rlabel metal1 425 109 439 175 0 C
+port 17 se
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+port 18 se
+rlabel metal1 274 80 303 109 0 A
+port 19 se
+rlabel metal1 281 109 295 175 0 A
+port 20 se
+rlabel metal1 274 175 303 204 0 A
+port 21 se
+<< properties >>
+string FIXED_BBOX 0 0 720 333
<< end >>
diff --git a/cells/mag/OR2X1.mag b/cells/mag/OR2X1.mag
index 2ae6dcd..c258f6e 100644
--- a/cells/mag/OR2X1.mag
+++ b/cells/mag/OR2X1.mag
@@ -1,4 +1,261 @@
magic
tech sky130A
-timestamp 1621277831
+timestamp 1623603004
+<< nwell >>
+rect 0 179 576 333
+<< nmos >>
+rect 137 24 152 66
+rect 281 24 296 66
+rect 425 24 440 66
+<< pmos >>
+rect 137 225 152 309
+rect 281 225 296 309
+rect 425 225 440 309
+<< ndiff >>
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+<< pdiff >>
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+<< ndiffc >>
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+<< pdiffc >>
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+<< poly >>
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+<< polycont >>
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+<< locali >>
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+<< viali >>
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+<< metal1 >>
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+<< labels >>
+rlabel metal1 0 309 576 357 0 VDD
+port 1 se
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+port 2 se
+rlabel metal1 466 40 495 69 0 Y
+port 3 se
+rlabel metal1 473 69 487 215 0 Y
+port 4 se
+rlabel metal1 466 215 495 244 0 Y
+port 5 se
+rlabel metal1 274 175 303 204 0 B
+port 6 se
+rlabel metal1 130 80 159 109 0 A
+port 7 se
+rlabel metal1 137 109 151 175 0 A
+port 8 se
+rlabel metal1 130 175 159 204 0 A
+port 9 se
+<< properties >>
+string FIXED_BBOX 0 0 576 333
<< end >>
diff --git a/cells/mag/OR2X2.mag b/cells/mag/OR2X2.mag
deleted file mode 100644
index 8baa737..0000000
--- a/cells/mag/OR2X2.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 1621277891
-<< end >>
diff --git a/cells/mag/XNOR2X1.mag b/cells/mag/XNOR2X1.mag
index f454691..e2af6ad 100644
--- a/cells/mag/XNOR2X1.mag
+++ b/cells/mag/XNOR2X1.mag
@@ -1,4 +1,472 @@
magic
tech sky130A
-timestamp 1621277951
+timestamp 1623603012
+<< nwell >>
+rect 0 179 1008 333
+<< nmos >>
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+<< pmos >>
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+<< metal1 >>
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+rect 0 5 760 19
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+rect 0 -24 1008 5
+<< labels >>
+rlabel metal1 0 309 1008 357 0 VDD
+port 1 se
+rlabel metal1 0 -24 1008 24 0 GND
+port 2 se
+rlabel space 466 175 495 204 0 Y
+port 3 se
+rlabel metal1 473 204 487 215 0 Y
+port 4 se
+rlabel nwell 466 215 495 244 0 Y
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+rlabel metal1 370 40 399 47 0 A
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+rlabel metal1 370 47 871 61 0 A
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+rlabel metal1 130 182 303 196 0 B
+port 19 se
+rlabel metal1 130 196 159 204 0 B
+port 20 se
+rlabel metal1 274 196 303 204 0 B
+port 21 se
+<< properties >>
+string FIXED_BBOX 0 0 1008 333
<< end >>
diff --git a/cells/mag/XOR2X1.mag b/cells/mag/XOR2X1.mag
deleted file mode 100644
index fa9c48a..0000000
--- a/cells/mag/XOR2X1.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 1621278052
-<< end >>
diff --git a/cells/mag/corr.INVX1.mag b/cells/mag/corr.INVX1.mag
deleted file mode 100644
index 1c42d38..0000000
--- a/cells/mag/corr.INVX1.mag
+++ /dev/null
@@ -1,88 +0,0 @@
-magic
-# Generated by librecell
-tech sky130A
-timestamp 1620330136
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-rect 27 333 262 340
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-rect 0 309 288 357
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-<< met1 >>
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-<< met1 >>
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-rect 0 309 288 357
-<< ndiffusion >>
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-<< pdiffusion >>
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-rect 58 309 87 312
-<< polycont >>
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-rect 136 181 153 198
-<< pdiffc >>
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-<< ndiffc >>
-rect 64 19 81 36
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-<< pplus >>
-<< labels >>
-rlabel met1 0 309 288 357 0 VDD
-port 1 se
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-port 2 se
-rlabel met1 178 40 207 69 0 Y
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-rlabel met1 130 80 159 109 0 A
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-rlabel met1 137 109 151 175 0 A
-port 7 se
-rlabel met1 130 175 159 204 0 A
-port 8 se
-<< end >>
