commit	a44a60b225e824c4eeb61bd99fed0d6da25ee6b0	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Wed Apr 28 14:05:41 2021 -0400
committer	Tim Edwards <tim@opencircuitdesign.com>	Wed Apr 28 14:05:41 2021 -0400
tree	f283a100f106709d046072587377dee6e5656f78
parent	6af7408dc6bbf5dde440266476933cebd69f3ba7 [diff]

Preliminary work on the analog user project example.  Added verilog RTL and
testbench.  The design passes the testbench.

info.yaml[diff]
mag/simple_por.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Added - diff]
mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Added - diff]
mag/user_analog_proj_example.mag[Added - diff]
mag/user_analog_project_wrapper.mag[Added - diff]
mag/user_analog_project_wrapper_empty.mag[Added - diff]
verilog/dv/mprj_por/Makefile[Added - diff]
verilog/dv/mprj_por/mprj_por.c[Added - diff]
verilog/dv/mprj_por/mprj_por_tb.v[Added - diff]
verilog/rtl/example_por.v[Added - diff]
verilog/rtl/uprj_analog_netlists.v[Added - diff]
verilog/rtl/uprj_netlists.v[Deleted - diff]
verilog/rtl/user_analog_proj_example.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[Renamed from verilog/rtl/user_project_wrapper.v - diff]

24 files changed

tree: f283a100f106709d046072587377dee6e5656f78

README.md

Caravel Analog User

NOTE

Fill this README with your caravel user project documentation.

Refer to README for this sample project documentation.