commit	c879bef71d8434e5dc0f82294787a1552547ad6d	[log] [tgz]
author	Mariano Alvira <mar@devl.org>	Wed May 19 22:07:19 2021 -0600
committer	Mariano Alvira <mar@devl.org>	Wed May 19 22:07:19 2021 -0600
tree	3c3aae2d50a30f42a4fd46110aa1332a0abeec8e
parent	727bf6f88939be0327c3d950f5c8a31f067e8bc8 [diff]

made a layout and named some ports (incorrectly) but extract then ext2spice produces a subckt. lvs isn't running correctly (can't detect the cell in the xschem netlist for some reason)

mag/cellA.mag[Added - diff]
mag/cellA.spice[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_CEXLE5.mag[Added - diff]
mag/sky130_fd_pr__res_high_po_0p35_L6NJBM.mag[Added - diff]
netgen/comp.out[Deleted - diff]
netgen/lvs_cellA.sh[Added - diff]
xschem/cellA.spice[diff]

7 files changed

tree: 3c3aae2d50a30f42a4fd46110aa1332a0abeec8e

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.