layout complete and passes LVS. turn off parasitics: extract no capacitance, resistance, coupling. extract all.
14 files changed
tree: 6c054756eb3e634d14fbd0537a255411f044d7f7
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitmodules
  10. info.yaml
  11. LICENSE
  12. Makefile
  13. README.md
README.md

Caravel Analog User

License UPRJ_CI Caravan Build


:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.