pull the test circuit out into a subckt and make a testbench for it. getting ready to layout and lvs just the cell.
diff --git a/xschem/cellA.sym b/xschem/cellA.sym
new file mode 100644
index 0000000..5a0d1f4
--- /dev/null
+++ b/xschem/cellA.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -40.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -42 0 0 0.2 0.2 {}
+L 4 -130 -30 130 -30 {}
+L 4 -130 30 130 30 {}
+L 4 -130 -30 -130 30 {}
+L 4 130 -30 130 30 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=VDD dir=inout }
+L 7 130 -20 150 -20 {}
+T {VDD} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=in dir=in }
+L 4 -150 -20 -130 -20 {}
+T {in} -125 -24 0 0 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=VSS dir=inout }
+L 7 130 20 150 20 {}
+T {VSS} 125 16 0 1 0.2 0.2 {}
