Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-038/4fb49018947775d20e67e5a0ebc126a1fa86543d
commit
4fb49018947775d20e67e5a0ebc126a1fa86543d
[log] [tgz]
author
Mariano Alvira <mar@devl.org>
Sun Jun 13 13:55:02 2021 -0600
committer
Mariano Alvira <mar@devl.org>
Sun Jun 13 13:55:02 2021 -0600
tree
69363760dfe528ca77ceaeab9e424ca123297951
parent
4b7b1f91df2d6deed0b7f963b11191910a0ed975 [diff]
top level LVS passes. There is a weird bug where xschem subckt ordering in cellA gets messed from the cell to the analog tb. But that's a xschem problem not the layout.
10 files changed
tree: 69363760dfe528ca77ceaeab9e424ca123297951
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. caravel
  10. .gitmodules
  11. info.yaml
  12. LICENSE
  13. Makefile
  14. README.md
  15. source.this
README.md

Caravel Analog User

License UPRJ_CI Caravan Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.